The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.
In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).
Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[Linux commit: ba78ee00e1ff84de9b3ad33edbd3ec599099ee82]
[masahiro: of_property_read_bool -> fdt_getprop for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Same macros are defined in various places. Collect them into
include/linux/bitops.h like Linux.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Read dma address using fdtdec_get_addr as it checks for
address cells and size cells and reads the address
properly. fdtdec_get_int always assume address is of int
size which goes wrong if using it on 64-bit architecture.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In legacy method, 1st stage bootloader was used to configure the HW
setting such as NAND timing. Hence, adding a config option in Zynq
NAND driver for the compatibility of device that using 1st stage
bootloder instead of U-boot SPL.
This commit is to add config option
CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use
timing values set by the 1st stage bootloader, instead of the hard-coded
values in the Zynq NAND driver.
Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
While the USB HW in the RZ/A is basically the same, there are some
differences from the original versions that were in the SH SoCs.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
before relocation pinctrl data BSS is overlapping DT area,
when .data is using uninitialized global variable,
imx6_pinctrl_soc_info. So assign them flags ZERO_OFFSET_VALID
to prevent BSS overlap
Suggested-by: Lokesh Vutla <lokeshvutla@ti.com>
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Existing FPGA program write is always assume RBF data >= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size >= 4 bytes.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This prevents board resets when calling sdp command on boards which have a watchdog.
Signed-off-by: Vincent Prince <vincent.prince.fr@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Increase the buffer length to be just above maximum permissible value
of 128 kiB . This increases the performance of the UMS and alike by a
factor of 2 - 2.5 as the buffers are less fragmented.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
Its a valid use case to call ehci_submit_async() with a NULL buffer
with length 0. E.g. from usb_set_configuration().
As invalidate_dcache_range() isn't able to judge if the address
NULL is valid or not (depending on the SoC hardware configuration it
might be valid) do the check in ehci_submit_async() as here we know
that we don't have to invalidate such a buffer.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Currently we check in ehci_shutdown() if ctrl is NULL after
dereferencing it.
Before this we have already dereferenced ctrl, ctrl->hccr,
and ctrl->hcor in ehci_get_portsc_register(), ehci_submit_root(),
and hci_common_init().
A better approach is to already check ctrl, ctrl->hccr, and ctrl->hcor
during the initialization in ehci_register() and usb_lowlevel_init()
and signal an error here via the return code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add firmware V3, firmware loader and XHCI glue for the Renesas R-Car
Gen3 SoCs XHCI controller. Thus far only the R-Car Gen3 R8A7795 ES2.0+
and R8A7796 are supported.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Commit 9000eddbae0d ("drivers/usb/ehci: Use platform-specific accessors")
broke USB 2.0 on big-endian platforms because for them writel/readl()
does automatic conversion of BE data to LE.
Proper implementation requires to use "raw" variant of these accessors
which read/write data without messing with endianess.
While at it replace cpu_to_be32() to be32_to_cpu() in readl() to
keep sane semantics.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Reported-by: Vladimir Boroda <boroda@yahoo.com>
The RK3399 has a total of 9 I2C controllers. To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.
For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The RK3399 clk driver still has a left-over use of extract_bits, which
can be replaced by using bitfield_extract from include/bitfield.h.
This rewrites the invocation to use the shared function.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The HSDK can manage some pins via CREG registers block.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
fix typo
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Using priv for new sysreset driver binding.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
After applying the merged sysreset driver, there are build failures
due to an out-of-sync Makefile. This updates drivers/sysreset/Makefile
to address these build failures.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Use a common driver for all Rockchip SOC instead of one for each SoC.
Use driver_data for reg offset.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The dra7xx series of SOCs contain a temperature sensor and an
associated analog-to-digital converter (ADC) which produces
an output which is proportional to the SOC temperature.
Add support for this temperature sensor.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a driver for the I2C controller available on Amlogic Meson SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Add support for S35392A RTC. The driver supports both U-Boot driver
models.
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: Heiko Schocher <hs@denx.de>
Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Tweak the i2c transfer to work for devices that want to read data
without addressing a register.
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In U-boot, serial_tstc was use to determine is there have a character in
serial console that pending for read. If there is no "pending" function
implemented in serial driver, the serial-uclass will return "true(1)"
to indicate there have a character pending to read.
Thus, read a character from nulldev serial will result in continuous
getting -EAGAIN return which might lead system to hang.
This commit is to fix a bug in nulldev serial which implement "pending"
function in nulldev serial to always indicate there is no character in
console that pending for read.
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Fix clock division factor initialization for RCC_PLLCFGR
registers.
PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert this driver to driver model.
This driver is also used by VEXPRESS platforms which doesn't
use driver model.
Tested on STM32F746 and STM32F769 platforms.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Update arm_pl180_mmci_init() prototype by adding struct mmc**
param. This is needed before converting this driver to driver model
in order to use arm_pl180_mmci_init() in driver model and in none
driver model implementation
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This option provides better performance and should really always be
enabled. Make this be default y.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY.
The PHY acts as a generic PHY but needs a slight configuration right
before it's configuration.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the Amlogic Meson GXL pinctrl support based on the GXBB driver and
the synchronized DTS from Linux 4.13.5
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
This currently causes a warning in sandbox and will not do the right
thing:
drivers/core/read.c: In function ‘dev_read_addr_ptr’:
drivers/core/read.c:64:44: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
Use map_sysmem() which is the correct way to convert an address to a
pointer.
Fixes: c131c8bca8 (dm: core: add dev_read_addr_ptr())
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
