At present this BIOS emulator uses a bus/device/function number. Change
it to use a device if CONFIG_DM_PCI is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We have a way to find a regmap by its syscon driver data value. Add the same
for syscon itself.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a compatible string to allow this to be specified in the device tree
if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not
compiled in. Display the error number to make this easier to spot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The trace is seldom useful for basic debugging. Allow it to be enabled
separately so that it is easier to see the more important init and error
debug messages.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.
We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is only available for compatibility with old code. Avoid
using it in the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver-model version of the pci_write_bar32 function so that this is
supported in the new API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function should not be used by driver-model code, so move it to the
compatibility portion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds basic support for the LCD controller of the Marvell
Armada XP SoC.
An AXP based custom board port will be added later, to use this
driver to display a splash screen via the bmp command later.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
[agust: rebased]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This patch adds driver support for the Realtek RTL8152B/RTL8153 USB
network adapters.
Signed-off-by: Ted Chen <tedchen at realtek.com>
[swarren, fixed a few compiler warnings]
[swarren, with permission, converted license header to SPDX]
[swarren, removed printf() spew during probe()]
Signed-off-by: Stephen Warren <swarren at nvidia.com>
USB protocol allows for 16 IN and 16 OUT endpoints (USB 2.0 Spec,
8.3.2.2 Endpoint Field). A function may have an EP 1 for both IN and OUT,
so these two should be kept separate. As EPs are either BULK or INTERRUPT
(or ISO), it is fine to have one array per direction for all transfer
types (also see e236519b7365ef75c5da6a5623f0b03d9c00cfae).
USB device address is 7 bits, so a bus may have more than 16 devices.
Check the device number, as the DWC2 driver only supports BULK/ISO for
the first 16 devices.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
CSPLITs for INTERRUPT transactions have to be scheduled in each microframe
following the SSPLIT. INTERRUPT transfers are executed in the next even/
odd microframe depending on the HCCHAR_ODDFRM flag.
As there are no handshakes for INTERRUPT SSPLITs the SSPLIT may have
failed (transport error) without the error being detected by the host
driver. If the last CSPLIT is not received within 4 microframes after the
SSPLIT there was a transaction error and the complete transaction has
to be restarted.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
In contrast to non-SPLIT transfers each transaction has to be submitted
as an individual chunk.
The transaction state machine proceeds from SSPLIT to CSPLIT if the ACK
flag is set. CSPLIT has to be repeated while NYET is set.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
The split register setting is used for both SSPLIT and CSPLIT transactions,
the bit for CSPLIT has to be set seperately.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Split the movement of data between CPU and Host Controller from the
status handling and tracking of transfer progress.
This will also simplify adding of SPLIT transaction support.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
A transfer is completed if the XFERCOMP flag is set, irrespective of the
ACK flag. BULK OUT transfers to some HS devices complete without having
the ACK flag set, which signal the devices has responded with an NYET
to the transfer (PING protocol).
The new behaviour matches the Linux kernel minus any PING protocol.
Also see 5966defabdcc (usb: dwc2: fix bulk transfers)
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Fix two errors in transfer len calculation, move loop invariant code out
of loop.
If xfer_len is equal to CONFIG_DWC2_MAX_TRANSFER_SIZE (or slightly
smaller), the xfer_len will be to large, e.g.:
xfer_len = MAX_TRANSFER_SIZE = 65535
max packet size = 512
=> num_packets = 128
=> IN xfer_len = 65536
For OUT transactions larger than (65536 - mps) bytes, the xfer_len
determination is quite awkward, it is only correct due to:
- max_packet_size for control/bulk/interrupt is required to be
power-of-two.
- (CONFIG_DWC2_MAX_TRANSFER_SIZE + 1) % max-packet-size is zero
for all allowed (2^3 ... 2^9) packet sizes
As the max xfer len is loop invariant, it can be moved out of the loop.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: Simon Glass <sjg@chromium.org>
Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.
Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
The displays need to use NPLL and also select some new peripheral clocks.
Add support for these to the clock driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.
Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.
Also update nyan-big which is affected by this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most panels are very simple - they just have a power supply and a backlight.
Add a driver which supports this and implements the enable_backlight()
method.
Signed-off-by: Simon Glass <sjg@chromium.org>
LCD panels can usefully be modelled as their own uclass. They can be probed
(which powers them up ready for use). If they have a backlight, this can be
enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Many backlights need to use a PWM to control the brightness. Add a driver
for this. It understands the standard device tree binding.
Signed-off-by: Simon Glass <sjg@chromium.org>
LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a uclass that supports Pulse Width Modulation (PWM) devices. It
provides methods to enable/disable and configure the device.
Signed-off-by: Simon Glass <sjg@chromium.org>
We must use the console name in the 'stdout' variable to select the one
we want. At present the name is formed from the driver name with a suffix
indicating the rotation value.
It seems better to name them sequentially since this can be controlled by
driver order. So adjust the code to use 'vidconsole' for the first,
'vidconsole1' for the second, etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
The correct pinctrl is handled automatically so we don't need to do it in
the driver. The exception is when we want to use a different chip select
(other than 0). But this isn't used at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there is an incorrect call to rkspi_enable_chip(). It should
be disabling the chip, not enabling it. Correct this and ensure that the
chip is disabled when releasing the bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some devices need delays before and after activiation. Implement these
features in the SPI driver so that we will be able to enable the Chrome
OS EC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Provide this method so that 'gpio status' works fully. It now shows
whether a pin is used for input, output or some other function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement this so that the GPIO command will be able to report whether a
GPIO is used for input or output.
Signed-off-by: Simon Glass <sjg@chromium.org>
This file has many features that are not needed by SPL. Use #ifdef to
remove the unused features and reduce the code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.
Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.
Signed-off-by: Simon Glass <sjg@chromium.org>
Two of the init values are created locally so cannot be out of range.
The masking is unnecessary and in one case is incorrect. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than changing the clock to the same value on every transaction,
remember the last value and don't adjust the clock unless it is necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function adds quite a bit of code to SPL and we probably don't need
all the features in SPL. Add a simple version (for SPL only) to save space.
Signed-off-by: Simon Glass <sjg@chromium.org>
