14594 Commits

Author SHA1 Message Date
Siva Durga Prasad Paladugu
b88a7a4c56 mmc: sdhci: Handle execute tuning command in sdhci_send_command
This patch upadted sdhci_send_command to handle execute tuning
command.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:27 +02:00
Siva Durga Prasad Paladugu
2a2d7efe77 mmc: sdhci: Add support for disabling clock
This patch adds support to disable clock if clk_disable
was set and then enable or set clock if the clock was changed
or clock was disabled when clock needs to be enabled.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:27 +02:00
Vipul Kumar
36332b6e4b mmc: Changed the datatype of the variable to handle 64-bit arch
This patch changed the datatype of variable "start" from uint to ulong
to work properly on 64-bit machines as well. Also the return type of
get_timer() function is ulong.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:27 +02:00
Michal Simek
1d6c54ecb3 arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.

This configuration with uart1 was tested on zcu100-revC.

U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)

Model: Xilinx ZynqMP R5
DRAM:  512 MiB
WARNING: Caches not enabled
MMC:
In:    serial@ff010000
Out:   serial@ff010000
Err:   serial@ff010000
Net:   Net Initialization Skipped
No ethernet found.
ZynqMP r5>

There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split

2. Load via jtag when directly to R5

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:23 +02:00
Michal Simek
5b410deac6 watchdog: cadence: Show used timeout value
Debug message was showing timeout value which was passed to start
function but there is a checking if this value can be setup.
The patch is moving this debug printf function below checking.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Siva Durga Prasad Paladugu
9fdde6c4bb nand: zynq: Send address cycles as per onfi parameter page
Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Siva Durga Prasad Paladugu
9ca8388059 nand: zynq: Add support for 16-bit buswidth
This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
d93c666c4c serial: zynq: Remove header depedency on arm header structure
There is no need to have arm hardware header in this driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
72c37d1221 timer: Add Cadence TTC timer counter support
This driver was tested on Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
c3898a8891 scsi: ceva: Convert driver to use UCLASS_AHCI instead of SCSI
In v2018 the patch
"dm: ahci: Correct uclass private data"
(sha1: bfc1c6b4838501d10aa48c0e92eaf70976f4b2dd)
was causing an issue for ceva_sata.
But this issue is not in v2018.05-rc1 but still converting to
UCLASS_AHCI would make more sense.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Tom Rini
f739fcd831 SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed.  These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict.  This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.

Fixes: 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style")
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-10 20:38:35 -04:00
Lukasz Majewski
afa9609eca bootcount: spl: Enable bootcount support in SPL
New, SPL related config option - CONFIG_SPL_BOOTCOUNT_LIMIT has been
added to allow drivers/bootcount code re-usage in SPL.

This code is necessary to use and setup bootcount in SPL in the case of
falcon boot mode.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-05-10 20:37:05 -04:00
Marcel Ziswiler
355560d588 pci: tegra: introduce weak tegra_pcie_board_port_reset() function
Introduce a weak tegra_pcie_board_port_reset() function by default
calling the existing tegra_pcie_port_reset() function. Additionally add
a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe
port index if required. This allows overriding the PCIe port reset
functionality from board specific code as e.g. required for Apalis T30
and Apalis TK1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-10 16:34:21 -07:00
Marcel Ziswiler
4616e33b6a power: as3722: fix ldo_get/set_enable for ldo index bigger than 7
Fix ldo_get_enable() and ldo_set_enable() functions for LDOs with an
index > 7. Turns out there are actually two separate AS3722_LDO_CONTROL
registers AS3722_LDO_CONTROL0 and AS3722_LDO_CONTROL1. Actually make use
of both. While at it also actually use the enable parameter of the
ldo_set_enable() function which now truly allows disabling as opposed to
only enabling LDOs.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-10 16:34:20 -07:00
Marcel Ziswiler
4b11a6296a mtd: nand: tegra: convert to driver model and live tree
The Tegra NAND driver recently got broken by ongoing driver model resp.
live tree migration work:

NAND:  Could not decode nand-flash in device tree
Tegra NAND init failed
0 MiB

A patch for NAND uclass support was proposed about a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

This commit just provides a driver model probe hook to retrieve further
configuration from the live device tree. As there is no NAND ulass as of
yet (ab)using UCLASS_MTD. Once UCLASS_NAND is supported, it would be
possible to migrate to it.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-10 16:34:10 -07:00
Yogesh Gaur
a6f2a6eafe driver: net: fsl-mc: updated copyright info
Updated copyright info for the issues reported after running
check-legal test.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Jagdish Gediya
e8c669a3e6 mtd: nand: fsl_ifc: Fix nand waitfunc return value
As per the IFC hardware manual, Most significant byte in nand_fsr
register is the outcome of NAND READ STATUS command.

So status value need to be shifted as per the nand framework
requirement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Jagdish Gediya
f195fad178 mtd: nand: fsl_ifc: Fix eccstat array overflow for IFC ver >= 2.0.0
Number of ECC status registers i.e. (ECCSTATx) has been increased in
IFC version 2.0.0 due to increase in SRAM size. This is causing
eccstat array to over flow.

So, replace eccstat array with u32 variable to make it fail-safe and
independent of number of ECC status registers or SRAM size.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Rajat Srivastava
1f55356411 spi: fsl_qspi: Introduce is_controller_busy function
Some SoCs have different endianness of QSPI IP if compared
to endianness of core. The function is_controller_busy()
checks if the QSPI controller is busy or not, considering
the endianness of the QSPI IP.

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Mario Six
e097ce4304 pci: Don't use pci_indirect when DM is active
Declaration of indirect PCI bridges is not compatible with DM: Both
define PCI operations, but in different ways. Hence, don't use indirect
bridges if DM is active.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-08 18:50:23 -04:00
Mario Six
86da8c12ef gdsys: drivers: Add gdsys_rxaui_ctrl driver
Add a driver for RXAUI control on IHS FPGAs.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-08 18:50:23 -04:00
Mario Six
f0bcbe6c18 clk: Add ICS8N3QV01 driver
Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-05-08 18:50:23 -04:00
Tom Rini
14249635b6 Merge git://git.denx.de/u-boot-mmc 2018-05-08 13:47:39 -04:00
Tom Rini
1ccd3f14ca Merge git://git.denx.de/u-boot-uniphier 2018-05-08 13:47:26 -04:00
Neil Armstrong
59beb238d5 adc: add Amlogic Meson SAR ADC driver
This patch adds the driver for the Amlogic Meson Successive Approximation
Register (SAR) A/D Converter based on the Linux IIO driver thanks to the
great work of Martin Blumenstingl.
The driver has been adapted to U-Boot and the ADC UClass.

This patch depends on the regmap "regmap: add regmap_update_bits() helper"
patch and has been tested using the newly introducted "adc" CLI command
in the "cmd: add ADC cli commands" patch.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-05-08 09:07:40 -04:00
Neil Armstrong
285cbcf97f regmap: add regmap_update_bits() helper
Add the regmap_update_bits() to simply the read/modify/write of registers
in a single command. The function is taken from Linux regmap
implementation.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-08 09:07:40 -04:00
Fabrice Gasnier
f198bbac66 clk: stm32mp1: Add VREF clock gating
Add VREF clock gating, that may be used by STM32 VREFBUF regulator.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:39 -04:00
Fabrice Gasnier
93cf0ae775 power: regulator: Add support for stm32-vrefbuf
Add regulator driver for STM32 voltage reference buffer which can be
used as voltage reference for ADCs, DACs and external components through
dedicated VREF+ pin.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:39 -04:00
Patrice Chotard
1f0dfa1fa0 power: pmic: stpmu1: Add regulator bindings
Add regulator bindings to get access to regulator managed
by drivers/power/regulator/stpmu1.c regulator driver.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:38 -04:00
Christophe Kerello
069f0b6354 power: regulator: stpmu1: Introduce stpmu1 driver
Enable support for the regulator functions of the STPMU1X PMIC. The
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:38 -04:00
Ludovic Desroches
8ee54672df gpio: atmel_pio4: give a full configuration when muxing pins
When a pin is muxed to a peripheral or as a GPIO, the only
configuration that can be set is the pullup. It is too restrictive
so this patch allows to give a full configuration.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-05-08 09:07:36 -04:00
Ley Foon Tan
7c45862f22 pci: intel: Add Intel FPGA PCIe controller driver
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in
rootport mode only, the EP mode is not supported. The driver is tested
with the Intel e1000e NIC driver.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-08 09:07:35 -04:00
Neil Armstrong
42de652272 pinctrl: meson: Update pinmux with new Linux bindings
The pinctrl bindings has changed for Amlogic Meson SoCs since Linux 4.13,
update the pinctrl driver to take this in account.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-05-08 09:07:34 -04:00
Patrice Chotard
8b41464547 clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock
On all STM32F4 and F7 SoCs  family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>
2018-05-08 09:07:34 -04:00
Patrick Bruenn
bc882f5d5c dm: led: auto probe() LEDs with "default-state"
To avoid board specificy LED activation code, automatically
activate gpio-leds with "default-state" property during bind().

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2018-05-08 09:07:33 -04:00
Patrick Bruenn
d90f0d4cae dm: led: Support "default-state" property
Add support for the device tree property "default-state". This feature
might be useful for LEDs indicating "power on" or similar states.

Note: Even with this commit gpio-leds remain in reset state. That's
because the led_gpio is not probed until DM_FLAG_ACTIVATED is set.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2018-05-08 09:07:33 -04:00
Andy Yan
e1fd9e6bb8 power: pwm regulator: support live tree
Use live tree compatible api for pwm regulator.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2018-05-08 13:12:33 +09:00
Patrick Bruenn
55118ec90c dm: mmc: socfpga: call dwmci_probe()
On a socfpga_cyclone5 based board the SD card, was never powered up. For
other dw_mmc based SoCs dwmci_probe() is called in the platform specific
probe(). It seems this call is missing for socfpga_dw_mmc.

With this change DWMCI_PWREN is set by dmwci_init().

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08 13:12:33 +09:00
Jaehoon Chung
72b5a0371d mmc: Kconfig: add the MMC_TRACE config in Kconfig
Add the MMC_TRACE config in Kconfig.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08 13:12:33 +09:00
Jaehoon Chung
d2faadb59c mmc: add the debug message in mmc_set_clock
Add the debug message for checking the mmc clock status.
It's helpful to debug the controlling clock.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08 13:12:33 +09:00
Jaehoon Chung
6511718254 mmc: add the MMC_CLK_ENABLE/DISABLE macro in mmc.h
mmc_set_clock() function has the disable argument as bool type.
When mmc_set_clock is called, it might be passed to "true" or "false".
But it's too confusion whether clock is enabled or disabled with only
"true" and "false".
To prevent the confusion, replace to MMC_CLK_ENABLE/DISABLE macro from
true/false.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08 13:12:33 +09:00
Jaehoon Chung
9c67c4491e power: pmic_max77686: remove the old pmic_max77686 file
max77686 pmic is supporting with max77686.c under pmic/ and regulator/
direnctroy. Remove pmic_max77686.c what didn't use anywhere.
Instead, enable CONFIG_DM_REGULATOR_MAX77686 and
CONFIG_DM_PMIC_MAX77686.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08 13:12:33 +09:00
Masahiro Yamada
57a6c1bf87 pinctrl: uniphier: add ethernet TX pin data for LD20
These are necessary to optimize the drive-strength of the pins.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:15 +09:00
Masahiro Yamada
150997a44b pinctrl: uniphier: support drive-strength configuration
This allows our DT to specify drive-strength property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:15 +09:00
Masahiro Yamada
603fd9ead6 pinctrl: uniphier: support per-pin configuration via DT
Currently, the UniPhier pinctrl drivers expose only the pin-group
interface to device tree.

Provide .get_pins_count, .get_pin_name, .pinconf_set hooks to support
pin configuration via 'pins' DT property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:15 +09:00
Masahiro Yamada
03cfc80134 pinctrl: uniphier: include <linux/build_bug.h> instead of <linux/bug.h>
The #include <linux/bug.h> is here to use BUILD_BUG_ON_ZERO().

By replacing it with <linux/build_bug.h>, we can reduce the number of
headers pulled in.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:14 +09:00
Masahiro Yamada
7629d0b9bc pinctrl: uniphier: replace printf() with dev_err()
dev_err() is more suitable for printing error messages.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:14 +09:00
Masahiro Yamada
d5c0d9a12a pinctrl: uniphier: remove unneeded pin data of LD6b SoC
Since commit f73cfb4d0dee ("pinctrl: uniphier: simplify input enable
and delete pin arrays"), these data are no longer used in any useful
way.  Remove.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:11 +09:00
Lokesh Vutla
acf1500138 arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:24 -04:00
Masahiro Yamada
e151a1c288 syscon: add Linux-compatible syscon API
The syscon implementation in U-Boot is different from that in Linux.
Thus, DT files imported from Linux do not work for U-Boot.

In U-Boot driver model, each node is bound to a dedicated driver
that is the most compatible to it.  This design gets along with the
concept of DT, and the syscon in Linux originally worked like that.

However, Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon
interface from platform devices") changed the behavior because it is
useful to let a device bind to another driver, but still work as a
syscon provider.

That change had happened before U-Boot initially supported the syscon
driver by commit 6f98b7504f70 ("dm: Add support for generic system
controllers (syscon)").  So, the U-Boot's syscon works differently
from the beginning.  I'd say this is mis-implementation given that
DT is not oriented to a particular project, but Linux is the canon
of DT in practice.

The problem typically arises in the combination of "syscon" and
"simple-mfd" compatibles.

In Linux, they are orthogonal, i.e., the order between "syscon" and
"simple-mfd" does not matter at all.

Assume the following compatible.

   compatible = "foo,bar-syscon", "syscon", "simple-mfd";

In U-Boot, this device node is bound to the syscon driver
(driver/core/syscon-uclass.c) since the "syscon" is found to be the
most compatible.  Then, syscon_get_regmap() succeeds.

However,

   compatible = "foo,bar-syscon", "simple-mfd", "syscon";

does not work because this node is bound to the simple-bus driver
(drivers/core/simple-bus.c) in favor of "simple-mfd" compatible.
The compatible string "syscon" is just dismissed.

Moreover,

   compatible = "foo,bar-syscon", "syscon";

works like the first case because the syscon driver populates the
child devices.  This is wrong because populating children is the job
of "simple-mfd" (or "simple-bus").

This commit ports syscon_node_to_regmap() from Linux.  This API
does not require the given node to be bound to a driver in any way.

Reported-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-07 15:49:52 -04:00