TI's J784S4 SoC has two instances of PCIe Controller namely PCIe0 and
PCIe1 which are Cadence PCIe Controllers. Add support to configure PCIe
instances in Endpoint mode of operation.
While at it disable all endpoint functions except function 0 during
probe to prevent the Root Complex from enumerating unconfigured
functions. This ensures only properly configured endpoint functions
are visible to the host and avoids enumeration issues with
multi-function devices.
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Probe the mux device early in the SERDES configuration flow to ensure
proper lane routing before PHY initialization. This is required for SoCs
where SERDES lanes can be muxed between different controllers
(PCIe, USB, etc), and different mux configurations are required between
different boot phases.
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Add a 1ms delay after powering on the PCIe power domain to ensure
the controller stabilizes before subsequent operations. This prevents
potential timing issues during PCIe endpoint initialization.
The delay allows sufficient time for the power domain to fully come
up and the hardware to be in a stable state before configuration
begins.
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
The commit under fixes tag includes "pcie-cadence.h" using angle
brackets. Since the header file is not in standard include path change
it to double quotes to ensure proper inclusion and avoid build issues,
especially on older compilers.
Fixes: a4a0edc6046 ("pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driver")
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Add support for Endpoint mode of operation in the Cadence PCIe
Controller present on TI's K3 SoCs. This driver is an adaptation of the
Linux kernel v6.15 driver (drivers/pci/controller/cadence/pci-j721e.c).
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
