STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Move the code making sure that the timer is initialized only once into
orion_timer_init(), which is called from timer_early_init() and from
orion_timer_probe(). This way the timer is not re-initialized.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michael Walle <michael@walle.cc>
Cc: Pali Rohár <pali@kernel.org>
This patch add general-purpose timer support for MediaTek MT7981/MT7986.
These two SoCs uses a newer version of timer with its register definition
slightly changed.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Add timer_get_boot_us() to support boards, that have CONFIG_BOOTSTAGE
enabled, like pogo_v4.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
This patch adds support for other Marvell Armada SoC's, supporting the
25MHz fixed clock operation, like the Armada XP etc.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
While testing on some Kirkwood platforms it was noticed that the timer
did not function correctly all the time. The driver did not correctly
handle 32bit timer value wrap arounds. Using the timer_conv_64()
conversion function fixes this issue.
Fixes: e9e73d78a8 ("timer: add orion-timer support")
Suggested-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier-oss@weidmueller.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
Move arm twd timer driver from zynq to generic location.
DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add timer support for Kirkwood and MVEBU devices.
Cc: Pali Rohár <pali@kernel.org>
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
cpu:
- Add driver for microblaze cpu
net:
- Add support for DM_ETH_PHY to AXI emac and emaclite
xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS
zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize
versal:
- Enable loading app at EL1
serial:
- Setup default address and clock rates for DEBUG uarts
pinctrl:
- Add support for tri state and output enable properties
relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze
microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support
timer:
- Extract axi timer driver from Microblaze to generic location
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Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.10
cpu:
- Add driver for microblaze cpu
net:
- Add support for DM_ETH_PHY to AXI emac and emaclite
xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS
zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize
versal:
- Enable loading app at EL1
serial:
- Setup default address and clock rates for DEBUG uarts
pinctrl:
- Add support for tri state and output enable properties
relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze
microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support
timer:
- Extract axi timer driver from Microblaze to generic location
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.
CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
This is always defined to 2, and referenced in two places. Move the
define to <asm/omap_common.h> and make sure the code that uses this
includes that file. Make <asm/arch-omap*/clock.h> not include that
file, as we don't need to be doing so.
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 0.3 KBytes.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This commit allows the ATMEL_TCB driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 1 KByte.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
As removal of nds32 has been ack'd for the Linux kernel, remove support
here as well.
Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The line with .of_to_plat in the U_BOOT_DRIVER structure
of dw-apb-timer.c is not aligned with the rest.
Add an extra TAB to fix the whitespace.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Rockchip rk3066 SoC has 3 dw-apb-timer nodes.
U-boot is compiled with OF_PLATDATA TPL/SPL options,
so add OF_PLATDATA support for the dw-apb-timer.
Also change driver name to be able to compile with
U-boot scripts. No reset OF_PLATDATA support was added,
because the rk3066 nodes don't need/have them.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
xilinx:
- Allow booting bigger kernels till 100MB
zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device
serial_zynq:
- Change fifo behavior in DEBUG mode
zynq_sdhci:
- Fix BASECLK setting calculation
clk_zynqmp:
- Add support for showing video clock
gpio:
- Update slg driver to handle DT flags
net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver
pwm:
- Add driver for cadence PWM
versal:
- Add support for reserved memory
firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations
include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
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Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc1 v2
xilinx:
- Allow booting bigger kernels till 100MB
zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device
serial_zynq:
- Change fifo behavior in DEBUG mode
zynq_sdhci:
- Fix BASECLK setting calculation
clk_zynqmp:
- Add support for showing video clock
gpio:
- Update slg driver to handle DT flags
net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver
pwm:
- Add driver for cadence PWM
versal:
- Add support for reserved memory
firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations
include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
Add a driver for the timer counter block that can be found on sama5d2.
This driver will be used when booting under OP-TEE since the pit timer
which is part of the SYSC is secured. Channel 1 & 2 are configured to
be chained together which allows to have a 64bits counter.
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
To make the OMAP DM timer driver useful for the timing of
bootstages, we need to implement timer_get_boot_us(..).
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
In order to finish moving this symbol to Kconfig for all platforms, we
need to do a few more things. First, for all platforms that define this
to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to
CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails
also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk()
and updating a few preprocessor tests.
With that done, all platforms that define a value here can be converted
to Kconfig, and a fall-back of zero is sufficiently safe to use (and
what is used today in cases where code may or may not have this
available). Make sure that code which calls this function includes
<clock_legacy.h> to get the prototype.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Disable bi_boot_params for STM32 MCU and MPU boards
- Update stm32-usbphyc node management
- Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards
- Convert some USB config flags to Kconfig for various boards
- Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board
- Remove specific CONFIG_STV0991 flags
- Remove unused CONFIG_USER_LOWLEVEL_INIT flag
- Add ofdata_to_platdata() callback for stm32_spi driver
- Update for stm32f7_i2c driver
- Remove gpio_hog_probe_all() from STM32 MP1 board
- Fix bind command
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Merge tag 'u-boot-stm32-20211012' of https://source.denx.de/u-boot/custodians/u-boot-stm
- Disable ATAGS for STM32 MCU and MPU boards
- Disable bi_boot_params for STM32 MCU and MPU boards
- Update stm32-usbphyc node management
- Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards
- Convert some USB config flags to Kconfig for various boards
- Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board
- Remove specific CONFIG_STV0991 flags
- Remove unused CONFIG_USER_LOWLEVEL_INIT flag
- Add ofdata_to_platdata() callback for stm32_spi driver
- Update for stm32f7_i2c driver
- Remove gpio_hog_probe_all() from STM32 MP1 board
- Fix bind command
Signed-off-by: Tom Rini <trini@konsulko.com>
Fix a regression brings by commit 84f8e36f03 ("cmd: bind: allow to
bind driver with driver data")
As example, the following bind command doesn't work:
bind /soc/usb-otg@49000000 usb_ether
As usb_ether driver has no compatible string, it can't be find by
lists_bind_fdt(). In bind_by_node_path(), which called lists_bind_fdt(),
the driver entry is known, pass it to lists_bind_fdt() to force the driver
entry selection.
For this, add a new parameter struct *driver to lists_bind_fdt().
Fix also all lists_bind_fdt() callers.
Fixes: 84f8e36f03 ("cmd: bind: allow to bind driver with driver data")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reported-by: Herbert Poetzl <herbert@13thfloor.at>
Cc: Marek Vasut <marex@denx.de>
Cc: Herbert Poetzl <herbert@13thfloor.at>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert some of these occurences to C code, where it is easy to do. This
should help encourage this approach to be used in new code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.
Signed-off-by: Simon Glass <sjg@chromium.org>
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.
This may potentially create an inconsistent config where the 2 values
do not match. Let's use the one specified in Kconfig in the device
tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simplify the code a bit by using dev_read_addr_ptr() instead of
dev_read_addr(). This avoids having to cast explicitly to the
struct nomadik_mtu_regs.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Define LOG_CATEGORY for all uclass to allow filtering with
log command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This timer driver uses GPT Timer (General Purpose Timer) available on
a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator
as well as peripheral clock.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
[Giulio: added the driver's stub and handled peripheral clock prescaler
setting making driver to work correctly]
Signed-off-by: Jesse Taube <mr.bossman075@gmail.com>
[Jesse: added init, setting prescaler for 24Mhz support and enabling
timer]
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Having WATCHDOG_RESET() called automatically from the timer interrupt
runs counter to the idea of a watchdog device - if the board runs into
an infinite loops with interrupts still enabled, the watchdog will
never fire.
When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more
complicated than just poking a few SOC-specific registers - it
involves accessing all kinds of global data, and if the interrupt
happens at the wrong time (say, in the middle of an WATCHDOG_RESET()
call from ordinary code), that can end up corrupting said global data.
Allow the board to opt out of calling WATCHDOG_RESET() from the timer
interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that
setting is currently nonsensical (it would be compile-time
divide-by-zero), it cannot affect any existing boards.
Add documentation for both the existing and extended meaning of
CONFIG_SYS_WATCHDOG_FREQ.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The code, which is likely copied from arch/powerpc/lib/interrupts.c,
lacks a fallback definition of CONFIG_SYS_WATCHDOG_FREQ and refers to
a non-existing timestamp variable - obviously priv->timestamp is
meant.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The _SUPPORT suffix is from an earlier time and interferes with use of
the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix.
Tidy up the TODO that prompted this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function only exists if CPU is enabled. Update the code to take
account of this, so that it does not have to be enabled on all sandbox
builds.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
At present long delays such as msleep(2000) can cause an overflow in this
function. There is no need for this, since it already uses a 64-bit int.
Add a cast to correct this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The timer being used by this driver may have already been used by first
stage bootloader (e.g. ATF/preloader), and it's settings may differ from
what this driver is going to use.
This may cause issues, such as inaccurate timer frequency due to
incorrect clock divider.
This patch adds the initialization code to avoid them.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The prescaler (PTV) setting must be taken into account even when the
timer input clock frequency has been set.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
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Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next
Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
The current macro is a misnomer since it does not declare a device
directly. Instead, it declares driver_info record which U-Boot uses at
runtime to create a device.
The distinction seems somewhat minor most of the time, but is becomes
quite confusing when we actually want to declare a device, with
of-platdata. We are left trying to distinguish between a device which
isn't actually device, and a device that is (perhaps an 'instance'?)
It seems better to rename this macro to describe what it actually is. The
macros is not widely used, since boards should use devicetree to declare
devices.
Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is
declaring a new driver_info record, not a device.
Signed-off-by: Simon Glass <sjg@chromium.org>
We have two functions which do the same thing. Standardise on
dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in
normal operation: it is either null or missing.
Also move the functions into one place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Update various drivers to use of_match_ptr() and to avoid including debug
strings in TPL. Omit the WiFi driver entirely, since it is not used in
TPL.
This reduces the TPL binary size by about 608 bytes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most drivers use these access methods but a few do not. Update them.
In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: Simon Glass <sjg@chromium.org>
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).
Rename some of the latter variables to end with 'plat' for consistency.
Signed-off-by: Simon Glass <sjg@chromium.org>
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.
Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update Patrick and my email address with the one dedicated to
upstream activities.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
This uclass is intended to provide a way to obtain information about a
U-Boot board. But the concept of a U-Boot 'board' is the whole system,
not just one circuit board, meaning that 'board' is something of a
misnomer for this uclass.
In addition, the name 'board' is a bit overused in U-Boot and we want to
use the same uclass to provide SMBIOS information.
The obvious name is 'system' but that is so vague as to be meaningless.
Use 'sysinfo' instead, since this uclass is aimed at providing information
on the system.
Rename everything accordingly.
Note: Due to the patch delta caused by the symbol renames, this patch
shows some renamed files as being deleted in one place and created in
another.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present there are a lot of dtoc warnings reported when building
chromebook_coral, of the form:
WARNING: the driver intel_apl_lpc was not found in the driver list
Correct these by using driver names that matches their compatible string.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
This matches the naming scheme of other timer drivers.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
This is a regular timer driver, and should live with the other timer
drivers.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next
First set of u-boot-atmel features for 2021.01 cycle:
This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
To test this function, sandbox CPU must set cpu_platdata.timebase_freq on
bind. It also needs to expose a method to set the current cpu. I also make
some most members of cpu_sandbox_ops static.
On the timer side, the device tree property
sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe
falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This function is designed to be used when a timer used to be initialized by
the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In
such a case, the timer may prefer to use the clocks and clock-frequency
properties, but should be able to fall back on using the cpu's
timebase-frequency.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.
This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Add support for Microchip PIT64B timer. The timer is 64 bit length and
is used as a free running counter (in continuous mode with highest values
for period registers). The clock feeding the timer would be no more
than 12.5MHz.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.
To help this tedious work, this commit converts devfdt_get_addr_ptr()
to dev_read_addr_ptr() by coccinelle. I also removed redundant casts
because dev_read_addr_ptr() returns an opaque pointer.
To generate this commit, I ran the following semantic patch
excluding include/dm/.
<smpl>
@@
type T;
expression dev;
@@
-(T *)devfdt_get_addr_ptr(dev)
+dev_read_addr_ptr(dev)
@@
expression dev;
@@
-devfdt_get_addr_ptr(dev)
+dev_read_addr_ptr(dev)
</smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
According to the description of devfdt_get_addr_ptr, this function should
return NULL on failure, but currently it returns (void *)FDT_ADDR_T_NONE.
Fix this by making devfdt_get_addr_ptr return NULL on failure, as
described in the function comments. Also, update the drivers currently
checking (void *)FDT_ADDR_T_NONE to check for NULL.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.
To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/
The semantic patch that makes this change is as follows:
<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.
To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/
The semantic patch that makes this change is as follows:
<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The timers compatible string in upstream is called
mt6577-timer. Add this compatible to the driver.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Retrieve clock rate through device tree. This mimics the behavior of
arm_global_timer in Linux.
Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Update STI timer to support a live tree
Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
The Nomadik Multi Timer Unit (MTU) provides 4 decrementing
free-running timers. It is used in ST-Ericsson Ux500 SoCs.
The driver uses the first timer to implement UCLASS_TIMER.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.
Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as
39146a2e0b x86: Move CPU init to before spl_init()
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.
Change the default to not read the timer base, leaving it at 0. Add an
option for when U-Boot is the secondary bootloader.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These functions do not use driver model but are fairly widely used in
U-Boot. But it is not clear that they will use driver model anytime soon,
so we don't want to label them as 'legacy'.
Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it
is widely used in U-Boot already.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is only used by a few files so it should not be in the common header.
Move it out.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
To use this DM timer on socfpga as system tick, it needs to take itself
out of reset.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.
Update the code to use a separate flag instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function can be called before the timer is set up. Make sure that the
init function is called so that it works correctly.
This is needed so that bootstage can work correctly in TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
