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5 Commits

Author SHA1 Message Date
Chanho Park
8ef2d7926f clk: starfive: jh7110: Add watchdog clocks 
Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110
watchdog device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-12-05 16:40:16 +08:00
Chanho Park
88af85cf92 clk: starfive: jh7110: Add security clocks 
Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-11-02 17:45:53 +08:00
Xingyu Wu
9adf1cf609 clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion 
Modify the drivers to add of_xlate ops and transform clock id.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-07-24 13:21:16 +08:00
Xingyu Wu
2d7a578791 clk: starfive: jh7110: Separate the PLL driver 
Drop the PLL part in SYSCRG driver and separate to be a single
PLL driver of which the compatible is "starfive,jh7110-pll".

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-07-24 13:20:44 +08:00
Yanhong Wang
c13fe7c034 clk: starfive: Add StarFive JH7110 clock driver 
Add a DM clock driver for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
 2023-04-20 16:08:44 +08:00