The SCLK_SFC can be set to a rate of 24, 50, 75, 100, 125 or 150 MHz.
However, clk_set_rate() will fail unless one of those exact rates are
used, and with newer and updated device tree files that contain
spi-max-frequency values that does not exactly match these rates use of
SPI flash may fail.
Fix this by using the highest possible rate that exceeds or is equal to
the requested rate.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The CLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of CLK_USB3OTGx_REF clocks to fix
reference clock period configuration.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The different macros use writel which is defined in asm/io.h, so let's
include the header so users of hardware.h do not need to include
asm/io.h as well.
While at it, remove asm/io.h includes wherever
asm/arch-rockchip/hardware.h is included already.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.
The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.
Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.
ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Fix this by including support for UART clocks in SPL.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix use of wrong clk selection for CLK_PWM1 on RK3568.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock
in assigned-clocks, add dummy support to set parent of this clock to the
rk3568 cru driver.
Fixes probe of pmic driver and missing regulators on affected boards,
rk3568-evb and rk3568-rock-3a.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Device tree contains assigned-clock-rates property for these,
but default value will work just fine
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.
Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
fix up ppll init freq.
support tclk_emmc.
add freq (26M) for mmc device.
fix up the sfc clk rate unit error.
Change in V2:
remove change id.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
