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2 Commits

Author SHA1 Message Date
Kongyang Liu
c21dfcb556 riscv: cache: Implement dcache for cv1800b 
Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2024-04-09 11:30:02 +08:00
Kongyang Liu
ae800aa79a riscv: cpu: cv1800b: Add support for cv1800b SoC 
Add Sophgo cv1800b SoC to support RISC-V arch.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2024-04-09 11:30:02 +08:00