The restoration of GPT table (both primary and secondary) is now possible.
Function 'gpt_restore' presents example of partition restoration process.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Custom definitions of le_XX_to_int functions have been replaced with
standard ones, defined at <compiler.h>
Replacement of several GPT related structures members with ones
indicating its endianness and proper size.
Signed-off-by: Chang Hyun Park <heartinpiece@outlook.com>
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This move is necessary to export gpt header and GPT partition entries to be
used with other commands or subsystems.
Additionally the part_efi.h file has been cleaned-up to supress checkpatch's
warnings.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
The ustrtoul shall convert string defined size (e.g. 1GiB) to unsigned
long type (as its name implies).
Up till now it had returned int, which might cause problems with large
numbers (GiB range), when interpreted as U2 signed numbers.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This implements a library for accessing EDID data from an LCD panel.
This is used to obtain information about the panel such as its
resolution and type.
This is a tidied-up version of the original code pulled from
https://github.com/ynezz/u-boot-edid.
The changes we made are:
- removed bit fields in the struct;
- removed endianness cases in the struct;
- fixed some wrong definitions;
- fixed to fit 80 columns;
- fixed some code styles.
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This new command supports hashing SHA1 and SHA256. It could be extended
to others such as MD5 and the CRC algorithms. The syntax is modeled on
those:
hash <algorithm> <address> <length> [*<dest_addr> | <dest_envvar>]
to calculate a hash, and:
hash -v <algorithm> <address> <length> [*<verify_addr> | <verify_envvar>]
to verify a hash.
Use CONFIG_CMD_HASH to enable the command, CONFIG_SHA1 to enable SHA1 and
CONFIG_SHA256 to enable SHA256.
The existing sha1sum command remains.
Signed-off-by: Simon Glass <sjg@chromium.org>
We have a SHA1 command and want to add a SHA256 command also. Instead of
duplicating the code, create a generic hash API which can process
commands for different algorithms.
Signed-off-by: Simon Glass <sjg@chromium.org>
strncasecmp() is present as strnicmp() but disabled. Make it available
and define strcasecmp() also. There is a only a small performance penalty
to having strcasecmp() call strncasecmp(), so do this instead of a
standalone function, to save code space.
Update the prototype in arch-specific headers as needed to avoid warnings.
Signed-off-by: Simon Glass <sjg@chromium.org>
In preparation for making the hash function common, we may as well use
const where we can.
Also add a watchdog version of the hashing function.
Signed-off-by: Simon Glass <sjg@chromium.org>
In preparation for making the hash function common, we may as well use
const where we can. Also the input length cannot be negative, but may
be very large, so use unsigned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sometimes data is on a block device and within a partition, but not in a
particular filesystem.
This commands permits reading raw data from a partition.
Signed-off-by: Kenneth Waters <kwaters@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Gettime returns the current timer value. If CONFIG_SYS_HZ is defined
then the timer value is also converted to seconds.
Tegra20 (SeaBoard) # gettime
Timer val: 7754
Seconds : 7
Remainder : 754
sys_hz = 1000
There has been some discussion about whether this is useful enough to
be included in U-Boot. The following boards do not have CONFIG_SYS_HZ
defined:
M52277EVB
M52277EVB_stmicro
M53017EVB
M54418TWR
M54418TWR_nand_mii
M54418TWR_nand_rmii
M54418TWR_nand_rmii_lowfreq
M54418TWR_serial_mii
M54418TWR_serial_rmii
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Make the necessary adaptions for the new PMIC framework, so that mx25pdk can
be built again.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Moved the pmic_max77686.c max77686_pmic.h to drivers/power
and made required changes accordingly
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We handle i2c_write return code and complain in case of error. We propagate the
error, too, to allow better handling at the upper level in the future.
Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Conflicts:
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/woodburn_common.h
board/woodburn/woodburn.c
These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.
Fix all conflicts and update woodburn to use Power Framework.
Signed-off-by: Stefano Babic <sbabic@denx.de>
The config is current broken. It compiles but does not boot because IDE is
enabled. Remove all IDE options, and enable SCSI instead.
Also add a working boot command and Linux bootargs, and enable command
line editing to make it easier to work with.
Signed-off-by: Simon Glass <sjg@chromium.org>
This allows u-boot to figure out the partitions of a chrome-os install.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
The default implementation of this function is just memset, but other
implementations will be needed when physical memory isn't accessible by
U-Boot using normal addressing mechanisms.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch fixes an issue with overlapping PCI regions
on boards with more than 64MB RAM.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch builds upon the recently introduced CBMEM console
feature of coreboot.
CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.
Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.
>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:
vvvvvvvvvvvvvvvvv
SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^
Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
When __BYTEORDER_HAS_U64__ is not defined, we got warning following:
-----
/tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’:
/tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’
[-Wimplicit-function-declaration]
-----
Usually, __arch__swab64* required for __fswab64, __swab64p and __swab64s
is defined. Therefore, __BYTEORDER_HAS_U64__ is unnecessary.
This removes __BYTEORDER_HAS_U64__.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
