2 Commits

Author	SHA1	Message	Date
Bai Ping	7b14cc991b	imx8mq: Update the ddrc QoS setting for B1 chip ... Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>	2019-10-08 16:36:37 +02:00
Peng Fan	e3963c0943	drivers: ddr: introduce DDR driver for i.MX8M ... Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>	2019-01-01 14:12:18 +01:00