There is a clock associated with this phy, but it's always from the
rpmhcc and isn't actually needed for the hardware to work.
Drop all the clock handling from the driver.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add a driver for the new Synopsys eUSB2 PHY found in the SM8550
and SM8650 SoCs.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
driver, notable the SM8250 SoC which will gain U-Boot support in
upcoming patches.
Introduce a driver based on the Linux driver.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[code cleanup, align symbol names with Linux, switch to clk/reset_bulk APIs]
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
The Snapdragon 845 and several other Qualcomm SoCs feature this
USB high-speed phy. Add a driver for it based on the Linux driver, with
support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain
support in U-Boot in future patches.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[code cleanup, switch to clk_bulk]
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
The USB2PHY regs already contain working default reset values for RK3328
and RK35xx as evidenced by the fact that this driver never has changed a
single value for these SoCs.
Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
what is currently done on RK3399. Also add missing clkout_ctl for RK3588.
When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
use otg/host controller utmi interface to phy. When disabled
utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
interface to phy.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs
that is supported by this driver have the USB2PHY regs in a different
GRF.
When support for RK356x, RK3588 and RK3328 was added this driver was
never updated to use correct GRF and have instead incorrectly written
to wrong GRF for these SoCs.
The default reset values for the USB2PHY have made USB mostly working
even when wrong GRF was used, however, following have been observed:
scanning bus usb@fd840000 for devices...
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
unable to get device descriptor (error=-1)
Fix this by using a regmap from rockchip,usbgrf prop and fall back to
getting a regmap for parent udevice instead of always getting the
common GRF.
Also protect against accidental clear of bit 0 in a reg with offset 0,
only bind driver to enabled otg/host-ports and remove unused headers.
Fixes: 3da15f0b49 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568")
Fixes: cdf9010f6e ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY")
Fixes: 9aa93d8403 ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use the root compatible strings from upstream Linux, add missing
'#clock-cells' property to the gcc node.
Adjust some of the msm8916/apq8016 drivers to use the correct upstream
compatible properties and DT bindings.
This prepares us to switch to upstream DT in a future patch.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add properties to improve eye diagram which sometimes need adjust
some parameters of u2phy;
Add a property to tune disconnect threshold;
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Currently, when running "ums 0 mmc 2" and breaking it via
CTRL + C, the following message is seen:
u-boot=> ums 0 mmc 1
UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x1dacc00
CTRL+C - Operation aborted
clk usb_phy_root_clk already disabled
The USB PHY clock is disabled twice: first it gets disabled
inside imx8mq_usb_phy_power_off(), then it is disabled again
inside imx8mq_usb_phy_exit().
Let the USB PHY clock be disabled only once inside
imx8mq_usb_phy_power_off() by removing the .exit operation.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni
Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patch which add A1 SoC support create a regression on khadas vim3/vim3l
boards when we try to use fastboot command:
=> fastboot usb 0
failed to get power domain
failed to get power domain
No USB device found
USB init failed: -19
Add ENOENT check on ret in probe function.
Fixes: 5533c883ce ("phy: support Amlogic A1 family")
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on vim3
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231017185725.809524-1-glaroque@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
A follow-up to commit 842fb5de42
("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer")
and commit 320a1938b6
("drivers: use devfdt_get_addr_index_ptr when cast to pointer").
In addition to using the *_ptr variants of these functions where the
address is cast to a pointer, this also changes devfdt_get_addr_*() to
dev_read_addr_*() in a few places. Some variable and field types are
changed from fdt_addr_t or phys_addr_t to void* where the cast was
happening later.
This patch fixes a number of compile warnings when building a 32bit
U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error
handling where the return value of dev_read_addr() etc. was checked for
NULL instead of FDT_ADDR_T_NONE.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Setting G12A and A1 is similar, so we can use G12A phy
driver with little changes.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-6-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
It is better to use defines instead of write raw
hex values in regmap.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-4-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Route signal from comb PHY instead of PCIe3 PHY to PCIe1l0 and PCIe1l1.
Fixes use of pcie2x1l0 on ROCK 5B.
Code imported from mainline linux driver.
Fixes: c5b4a012bc ("phy: rockchip: naneng-combphy: Support rk3588")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for the RK3588 variant to the driver.
Code imported almost 1:1 from mainline linux driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Configure aggregation or bifurcation mode on RK3568 based on the value
of data-lanes property.
Code imported almost 1:1 from mainline linux driver.
Fixes: 6ec62b6ca6 ("phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a phy_init ops in preparation for upcoming support of a RK3588
variant in the driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change to use clk_bulk API and syscon_regmap_lookup_by_phandle to
simplify in preparation for upcoming support of a RK3588 variant.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Refactor generic_{setup,shutdown}_phy() to reduce complexity and
indentation. This have no intended functional change.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Restore the old behavior of ehci_setup_phy() and ohci_setup_phy() to
return success when generic_phy_get_by_index() return -ENOENT.
Fixes: 84e561407a ("phy: Add generic_{setup,shutdown}_phy() helpers")
Fixes: 10005004db ("usb: ohci: Make usage of generic_{setup,shutdown}_phy() helpers")
Fixes: 083f8aa978 ("usb: ehci: Make usage of generic_{setup,shutdown}_phy() helpers")
Fixes: 75341e9c16 ("usb: ehci: Remove unused ehci_{setup,shutdown}_phy() helpers")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
generic_phy_exit() typically return 0 for a struct phy that has been
initialized with a generic_phy_init() call.
generic_setup_phy() returns the value from a generic_phy_exit() call
when generic_phy_power_on() fails. This hides the failed state of the
power_on ops from the caller of generic_setup_phy().
Fix this by ignoring the return value of the generic_phy_exit() call and
return the value from the generic_phy_power_on() call.
Fixes: 84e561407a ("phy: Add generic_{setup,shutdown}_phy() helpers")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Generic phy helpers typically use generic_phy_valid() to determine if
the helper should perform its function on a passed struct phy.
generic_phy_valid() treat any struct phy having phy->dev set as valid.
With generic_phy_get_by_index_nodev() setting phy->dev to a valid struct
udevice early, there can be situations where the struct phy is returned
as valid when initialization in fact failed and returned an error.
Fix this by setting phy->dev back to NULL when any of the calls to
of_xlate ops, device_get_supply_regulator or phy_alloc_counts fail. Also
extend the dm_test_phy_base test with a test where of_xlate ops fail.
Fixes: 72e5016f87 ("drivers: phy: add generic PHY framework")
Fixes: b9688df3cb ("drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
generic_phy_get_by_name() does not initialize phy->dev to NULL before
returning when dev_read_stringlist_search() fails. This can lead to an
uninitialized or reused struct phy erroneously be report as valid by
generic_phy_valid().
Fix this issue by initializing phy->dev to NULL, also extend the
dm_test_phy_base test with calls to generic_phy_valid().
Fixes: b9688df3cb ("drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() fails")
Fixes: 868d58f69c ("usb: dwc3: Fix non-usb3 configurations")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
use CONFIG_IS_ENABLED for clock enable/disable and change printf's
to dev_err. Additionlly remove the comment that does not make sense.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add support for enabling and disabling vbus-supply regulator found
on several imx8mp boards in the usb3_phy0 and usb3_phy1 nodes.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Select the same mac divider for SGMII too as the one being used for
QSGMII.
Enable full rate divider configuration support for J721E_WIZ_10G for
SGMII.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
This is merely a dummy driver that makes sure the DWC3 XHCI driver
finds its reset and PHY controllers. We rely on iBoot to set up
the PHY for us.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
USB2.0 Host and OTG controllers in RK3328 are using USB2PHY.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
[eugen.hristev@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Now that the Allwinner USB PHY driver supports the H616 quirk, let's
enable support for USB ports on that SoC.
We connect the compatible string to a new struct describing the SoCs USB
PHY properties, and unblock the PHY driver selection in Kconfig.
A later patch will enable USB support in the H616 boards' defconfigs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The H616 USB PHY is some kind of special snowflake: Only port2 works out
of the box, but all other ports need some help from this port2 to work
correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be
enabled, and the SIDDQ bit in the PMU PHY control register needs to be
cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be
ungated. Don't ask ....
Follow the respective Linux patch (b45c6d80325b) and add a quirk bit,
triggering the special sequence as outlined above, for PHYs other than
PHY2: ungate this one special clock, and clear the SIDDQ bit. We also
pick the clock and reset from PHY2 and enable them as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
So far we were assigning some crude "type" (SoC name, really) to each
Allwinner USB PHY model, then guarding certain quirks based on this.
This does not only look weird, but gets more or more cumbersome to
maintain.
Remove the bogus type names altogether, instead introduce flags for each
quirk, and explicitly check for them.
This improves readability, and simplifies future extensions.
Port of Linux patch 8dd256bae653.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
At the moment we use "select" in each Allwinner SoC's Kconfig section to
include the USB PHY driver in the build. This means it cannot be disabled
via Kconfig, although USB is not really a strictly required core
functionality, and a particular board might not even include USB ports.
Rework the Kconfig part by removing the "select" lines for each SoC's
section, and instead letting it default to "y" in the PHY driver section
itself. We use "depends on !" to exclude the few SoCs we don't support
(yet). The Allwinner V3s does not enable USB (PHY) support at the moment,
even though it should work: let the PHY default to "n" to keep the
current behaviour.
Also the MUSB USB driver directly calls some functions from the PHY
driver, so let the former depend on the PHY driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
The Allwinner F1C100s implements a single USB PHY, connected to its MUSB
OTG controller. The USB PHY is of the simpler, older type (like the A10),
the only real difference is that it's indeed only one PHY.
Add a struct describing those F1C100s USB PHY properties, and connect it
to the new compatible string.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
In its of_xlate() function, the Allwinner USB PHY driver compares the
args_count variable against the number of implemented USB PHYs, although
this is the *number of arguments* to the DT phandle property. Per the DT
binding for this PHY device, this number is always one, so this check
will always fail if the particular SoC implements exactly one USB PHY.
So far this affected only the V3s (which has USB support disabled), but
the F1C100s also sports one PHY only.
Fix that check to compare args_count against exactly 1, and the args[0]
content (requested PHY number) against the number of implemented PHYs.
This fixes USB operation on the Allwinner V3s and allows to enable USB
on the Allwinner F1C100s SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The support for #address-cells=2 has a loophole: if the reg is actually 0,
but the #address-cells is actually 1, like in such case below:
syscon {
#address-cells = <1>;
phy {
reg = <0 0x10>;
};
};
then the second u32 of the 'reg' is the size, not the address.
The code should check for the parent's #address-cells value, and not
assume that if the first u32 is 0, then the #address-cells is 2, and the
reg property is something like
reg = <0 0xff00 0x10>;
Fixed this by looking for the #address-cells value and retrieving the
reg address only if this is ==2.
To avoid breaking anything I also kept the check `if reg==0` as some DT's
may have a wrong #address-cells as parent and even if this commit is
correct, it might break the existing wrong device-trees.
Fixes: d538efb9ad ("phy: rockchip: inno-usb2: Add support #address_cells = 2")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
