Commit Graph

3412 Commits

Author SHA1 Message Date
Suman Anna
8a5fe04495 net: ti: am65-cpsw-nuss: Add logic to support MDIO reset
Enhance the AM65 CPSW NUSS driver to perform a MDIO reset using a GPIO
line. Logic is also added to perform a pre and post delay around reset
using the optional 'reset-delay-us' and 'reset-post-delay-us' properties.
This is similar to the reset being performed in the Linux kernel. The
reset is done once when the CPSW MDIO bus is being initialized.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15 17:46:39 -04:00
Siddharth Vadapalli
0131c90214 net: ti: am65-cpsw-nuss: Add support for SGMII mode
Add support for configuring the CPSW Ethernet Switch in SGMII mode.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15 17:46:39 -04:00
Weijie Gao
93eb707c28 net: mediatek: add support for MediaTek MT7988 SoC
This patch adds support for MediaTek MT7988.

MT7988 features MediaTek NETSYS v3, including three GMACs, and two
of them supports 10Gbps USXGMII.

MT7988 embeds a MT7531 switch (not MCM) which supports accessing
internal registers through MMIO instead of MDIO.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Weijie Gao
7628194d7a net: mediatek: add support for NETSYS v3
This patch adds support for NETSYS v3 hardware.
Comparing to NETSYS v2, NETSYS v3 has three GMACs.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Weijie Gao
ba026ebe46 net: mediatek: add USXGMII support
This patch adds support for USXGMII of SoC.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Weijie Gao
585a1a44ee net: mediatek: add support for GMAC/USB3 PHY mux mode for MT7981
MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
register must be set to connect the SGMII phy to GMAC2.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Weijie Gao
bd70f3cea3 net: mediatek: add support for SGMII 1Gbps auto-negotiation mode
Existing SGMII support of mtk-eth is actually a MediaTek-specific
2.5Gbps high-speed SGMII (HSGMII) which does not support
auto-negotiation mode.

This patch adds SGMII 1Gbps auto-negotiation mode and rename the
existing HSGMII to 2500basex.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Weijie Gao
159458d32c net: mediatek: add missing static qualifier
mt7531_mmd_ind_read and mt753x_switch_init are defined without static.
Since they're not used outside this file, we should add them back.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

fixup to add static qualifier
2023-08-03 09:40:50 -04:00
Weijie Gao
c94ad00917 net: mediatek: fix direct MDIO clause 45 access via SoC
The original direct MDIO clause 45 access via SoC is missing the
data output. This patch adds it back to ensure MDIO clause 45 can
work properly for external PHYs.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Weijie Gao
c41a058fb2 net: mediatek: optimize the switch reset delay wait time
Not all switches requires 1 second delay after deasserting reset.
MT7531 requires only maximum 200ms.

This patch defines dedicated reset wait time for each switch chip, and will
significantly improve the boot time for boards using MT7531.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Weijie Gao
c73d38719f net: mediatek: connect switch to PSE only when starting eth is requested
So far the switch is initialized in probe stage and is connected to PSE
unconditionally. This will cause all packets being flooded to PSE and may
cause PSE hang before entering linux.

This patch changes the connection between switch and PSE:
- Still initialize switch in probe stage, but disconnect it with PSE
- Connect switch with PSE on eth start
- Disconnect on eth stop

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00
Minda Chen
ff8590a225 net: rtl8169: Add one device ID 0x8161
Add rtl8169 NIC device ID and reorder the device ID.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02 11:02:32 +08:00
Minda Chen
3094845165 net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
For RISC-V architeture, hardware maintain the dcache coherency.
Software do not flush the cache. So even cache-line size larger
than descriptor size, driver can work.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02 11:02:32 +08:00
Minda Chen
a6a0d6a191 net: rtl8169: Fix compile warning in rtl8169
While compiling rtl8169.c, There are many "make pointer from
integer without a cast" compile warnings. fix them with
adding cast.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02 11:02:32 +08:00
Roger Quadros
7c9267e511 net: ti: am65-cpsw-nuss: Get port mode register from standard "phys" property
Approved DT binding has the port mode register in the
"phys" property. Get it from there instead of the custom
"cpsw-phy-sel" property.

This will allow us to keep DT in sync with Linux.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
2023-07-27 17:10:46 -04:00
Roger Quadros
fcb513e5f2 net: ti: am65-cpsw-nuss: Use approved property to get efuse address
The approved DT property for MAC efuse (ROM) address is
"ti,syscon-efuse".

Use that and drop custom property "mac_efuse".

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
2023-07-27 17:10:46 -04:00
Maxime Ripard
9b33be392b net: ti: am65-cpsw-nuss: Enforce pinctrl state on the MDIO child node
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.

The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.

However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node, like the SK-AM62 Device
Tree does.

Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.

Signed-off-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
2023-07-27 17:10:46 -04:00
Nate Drude
e8b4a8d7f0 phy: adin: add readext and writeext support for mdio cmd
The adin phy has extended registers that can be accessed using
adin_ext_read and adin_ext_write. These registers can be read directly
using the mdio command using readext and writext. For example:

     => mdio rx ethernet@428a0000 0xff23
     Reading from bus ethernet@428a0000
     PHY at address 0:
     65315 - 0xe01

Signed-off-by: Nate Drude <nate.d@variscite.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-07-27 14:32:12 -04:00
Karsten Wiese
3ca4955760 net: ksz9477: add support for KSZ9893 GbE switch
Copy and tweak the required code from the linux kernel.
Only the KSZ9893 has been tested.

Signed-off-by: Karsten Wiese <karsten.wiese@protechna.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-07-27 14:32:12 -04:00
Maksim Kiselev
3fb4ef7d39 net: axi_emac: Change return value to -EAGAIN if RX is not ready
If there is no incoming package than axiemac_recv will return -1 which
in turn leads to printing `eth_rx: recv() returned error -1` error
message in eth_rx function. But missing a package is not an fatal error,
so return -EAGAIN in that case would be more suitable.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20230719065337.69280-1-bigunclemax@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:39 +02:00
Michal Simek
174d728471 arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Venkatesh Yadav Abbarapu
22836f088d net: zynq_gem: Don't hardcode the MDC clock divisor
As per spec MDC must not exceed 2.5MHz, read the pclk clock
from the device tree and update the MDC clock divisor.
GEM devices support larger clock divisors and have a different
range of divisors.  Program the MDIO clock divisors based on
the clock rate of the pclk clock.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230619034922.24019-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Andreas Dannenberg
edacf6a44d net: ti: am65-cpsw-nuss: Use dedicated port mode control registers
The different CPSW sub-system Ethernet ports have different PHY mode
control registers. In order to allow the modes to get configured
independently only the register for the port in question must be
accessed, otherwise we would just be re-configuring the mode for port 1,
while leaving all others at their power-on defaults. Fix this issue by
adding a port-number based offset to the mode control base register
address based on the fact that the control registers for the different
ports are spaced exactly 0x4 bytes apart.

Fixes: 9d0dca1199 ("net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-07-14 15:21:07 -04:00
Yanhong Wang
736733b43a net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-07-12 13:21:40 +08:00
Yanhong Wang
e92ed065ba net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on StarFive VisionFive2 board.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-07-12 13:21:40 +08:00
Tom Rini
e80f4079b3 Prepare v2023.07-rc6
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Merge tag 'v2023.07-rc6' into next

Prepare v2023.07-rc6
2023-07-05 11:28:55 -04:00
Ioana Ciornei
5654ffa8f1 net: fsl-mc: sync remaining MC commands
This patch targets the last remaining commands left to sync to their
latest form - mainly the mc_get_version() API.

Besides this, remove any macro which is now of no help.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Ioana Ciornei
0aebee70bb net: fsl-mc: sync DPIO MC APIs
Sync the Data Path IO APIs to their latest form, this means the layout
of each command is created based on structures which clearly describe
the endianness of each field rather than some macros.

The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Ioana Ciornei
4797269e74 net: fsl-mc: sync DPSPARSER MC APIs
Sync the Data Path Soft Parser APIs to their latest form, this
means the layout of each command is created based on structures which
clearly describe the endianness of each field rather than some macros.

The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Ioana Ciornei
207c815770 net: fsl-mc: sync DPNI MC APIs
Sync the Data Path Network Interface APIs to their latest form, this
means the layout of each command is created based on structures which
clearly describe the endianness of each field rather than some macros.

The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Ioana Ciornei
95f309a4f8 net: fsl-mc: sync DPRC MC APIs
Sync the Data Resource Container APIs to their latest form, this means
the layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.

The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Ioana Ciornei
018bc358d3 net: fsl-mc: sync DPMAC MC APIs
Sync the Data Path MAC APIs to their latest form, this means the
layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.

The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Ioana Ciornei
694dc0dd79 net: fsl-mc: sync DPBP MC APIs
Sync the Data Path Buffer Pool APIs to their latest form, this means the
layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.

The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Ioana Ciornei
f21d326be4 net: fsl-mc: remove unused MC APIs
There are multiple MC APIs which were added years ago but they are not
used at all in the u-boot source code. Remove all these APIs.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Eugen Hristev
89d8c56f44 net: rtl8169: add depends on PCI
The rtl8169 driver uses calls to dm_pci_bus_to_phys,
which are compiled under CONFIG_PCI.

Without CONFIG_PCI, this happens:

drivers/net/rtl8169.o: in function `rtl_recv_common':
drivers/net/rtl8169.c:555: undefined reference to `dm_pci_bus_to_phys'

It is only natural that this driver depends on CONFIG_PCI then.
The device does not work connected in another way anyway, and the driver
does not assume anything else at this moment.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-14 12:56:10 -04:00
Ioana Ciornei
c6caaafe8d net: ldpaa_eth: export DPNI and DPMAC counters through 'net stats'
Export the already existing DPNI and DPMAC counters through the newly
added callbacks.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-14 18:40:16 +08:00
Ioana Ciornei
22df08d82e net: ldpaa_eth: extend debug capabilities with DPMAC statistics
The ldpaa_eth driver already had a DPMAC statistics dump, this patch
extends the list of stats and adds a bit more structure to the code.

For a bit more context, the DPAA2 u-boot software architecture uses a
default network interface object - a DPNI - which, at runtime, will get
connected to the currently used DPMAC object.
Each time the .stop() eth callback is called, the DPMAC is destroyed
thus any previous counters will get lost.

As a preparation for the next patches, we add a software kept set of
DPMAC counters which will get updated before each destroy operation
takes place.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-14 18:40:16 +08:00
Ioana Ciornei
308d67e77d net: ldpaa_eth: extend debug capabilities with DPNI statistics
The ldpaa_eth driver already had a DPNI statistics dump, this patch
extends the list of stats and adds a bit more structure to the code.

For a bit more context, the DPAA2 u-boot software architecture uses a
default network interface object - a DPNI - which, at runtime, will get
connected to the currently used DPMAC object.
Each time the .stop() eth callback is called, the DPNI is reset to its
original state, including its counters.

As a preparation for the next patches, we add a software kept set of
DPNI counters which will get updated before each reset operation takes
place.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-14 18:40:16 +08:00
Ioana Ciornei
13ca5c2f56 net: ldpaa_eth: transform dpni_statistics from a struct to a union
In order to simplify code, dpni_statistics can be written as a union.
Using the raw accessors we can just loop through all the statistics from
a page without trying to access each an every one independently.
Make this change to a union.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-14 18:40:16 +08:00
Tom Rini
7da82de916 Xilinx changes for v2023.10-rc1
global:
 - Use proper U-Boot project name
 
 Fix sparse warnings in zynqmp-clk, zynqmp handoff, board
 
 cmd:
 - Cover incorrect 0 length entries
 
 Versal NET:
 - Add bootmode logic
 - Support SPP production version
 - Add loadpdi command
 
 ZynqMP:
 - Clear pmufw node command ID handling
 - Change power domain behavior around zynqmp_pmufw_node()
 - Fix zynqmp cmd return values and pmufw command
 - Fix R5 tcm init and modes
 
 mmc:
 - Sync Versal NET emmc DT binding
 
 pcie:
 - Add support for ZynqMP PCIe root port
 
 video:
 - Add support for ZynqMP DP
 
 tools:
 - Fix debug message in relocate-rela
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Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.10-rc1

global:
- Use proper U-Boot project name

Fix sparse warnings in zynqmp-clk, zynqmp handoff, board

cmd:
- Cover incorrect 0 length entries

Versal NET:
- Add bootmode logic
- Support SPP production version
- Add loadpdi command

ZynqMP:
- Clear pmufw node command ID handling
- Change power domain behavior around zynqmp_pmufw_node()
- Fix zynqmp cmd return values and pmufw command
- Fix R5 tcm init and modes

mmc:
- Sync Versal NET emmc DT binding

pcie:
- Add support for ZynqMP PCIe root port

video:
- Add support for ZynqMP DP

tools:
- Fix debug message in relocate-rela
2023-06-12 16:42:37 -04:00
Tom Rini
260d4962e0 Merge tag v2023.07-rc4 into next
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-12 14:55:33 -04:00
Michal Simek
1be82afa80 global: Use proper project name U-Boot
Use proper project name in comments, Kconfig, readmes.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Qu Wenruo <wqu@suse.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-06-12 13:24:31 +02:00
Valentine Barshak
41a0cfd0c5 net: sh_eth: Fix RX error handling
In case RX error occurs, and the RD_RFE bit is set, the descriptor
is never returned back to the queue. Make sh_eth_recv_start return
zero length in this case so that the descriptor can be released
and pushed back to the list. Also return the more appropriate
-EAGAIN instead of -EINVAL if the descriptor is not ready yet.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Valentine Barshak
d49ba9c8d7 net: sh_eth: Workaround cache issues
U-Boot writes to RX packets when constructing replies.
This can cause stale cached data to be written to RX
buffer while we're receiving a packet. This causes RX
packet corruption because we invalidate the cache right
before processing the packet. Invalidate packet buffer
cache when preparing RX descriptor as well. This seems
to fix RX packet drops with high RX traffic.

While at it flush the descriptors right before enabling
RX/TX in sh_eth_tx_desc_init/sh_eth_rx_desc_init callbacks
when they are ready instead of flushing after allocation.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
92c312c734 net: sh_eth: Drop reset GPIO handling in favor of common code
The common code is now capable of handling reset GPIO associated
with PHY. Drop the local ad-hoc code in favor of common code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
5c80edb264 net: ravb: Drop reset GPIO handling in favor of common code
The common code is now capable of handling reset GPIO associated
with PHY. Drop the local ad-hoc code in favor of common code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
3015ae5feb net: phy: Handle reset-delay-us/reset-post-delay-us properties
These two properties are used by various DTs in place of
current reset-assert-us/reset-deassert-us , handle both .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
68a4d15061 net: phy: Bind ETH_PHY uclass driver to each new PHY
In case a new PHY is created and DM_ETH_PHY is enabled, bind a
generic PHY driver from ETH_PHY uclass to the PHY to have a
matching DM representation of that PHY.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
495fc04b6d net: phy: Unpublish phy_connect_dev()
The phy_connect_dev() is legacy API, now that there are no users,
make it internal to phy.c and unpublish it from headers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
83434e249f net: sunxi_emac: Switch to new U-Boot PHY API
Use new U-Boot phy_connect() API which also supports fixed PHYs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
b9b04f8c5f net: sh_eth: Switch to new U-Boot PHY API
Use new U-Boot phy_connect() API which also supports fixed PHYs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
8f5abff522 net: pch_gbe: Switch to new U-Boot PHY API
Use new U-Boot phy_connect() API which also supports fixed PHYs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
8869a8883b net: ethoc: Switch to new U-Boot PHY API
Use new U-Boot phy_connect() API which also supports fixed PHYs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
7ff881a69f net: ave: Switch to new U-Boot PHY API
Use new U-Boot phy_connect() API which also supports fixed PHYs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
fd5910288f net: altera_tsa: Switch to new U-Boot PHY API
Use new U-Boot phy_connect() API which also supports fixed PHYs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:05 +02:00
Marek Vasut
06173ef643 net: eth-phy: staticize eth_phy_reset()
The eth_phy_reset() is not used outside of this file, staticize it.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:04 +02:00
Tom Rini
41e289bb1f arm: Remove ti816x_evm board and ti816x SoC support
This platform is currently unmaintained and untested, so remove it.
Further, as it is the only TI816X SoC example, remove related files as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-31 10:11:46 -04:00
Tom Rini
0a9a4384c1 Merge tag 'u-boot-rockchip-20230509' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
2023-05-09 12:45:49 -04:00
Johan Jonker
320a1938b6 drivers: use devfdt_get_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
a12a73b664 drivers: use dev_read_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
e5822ecba2 drivers: use dev_read_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Stefan Herbrechtsmeier
1a3af267c0 net: phy: Request rgmii-id phy reset gpio as output
Request the reset gpio of the rgmii-id phy as output to be consistent
with the eth-phy-uclass driver.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
2023-05-05 18:03:18 -04:00
Eugen Hristev
bcbb64b199 net: rtl8169: add minimal support for 8125B variant
Add minimal support for 8125B version.
Changes are based on the Linux driver.
Tested on Radxa Rock 5B Rk3588 board.

Connection to a laptop worked fine in 100 Mbps mode.
1000 Mbps mode is not working at the moment.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-05-05 17:59:20 -04:00
Nishanth Menon
0207403eeb net: phy: dp83867: Explicitly check against sgmii
dp83867 driver only supports sgmii and not all the newer protocols.
Drop the usage of the generic phy_interface_is_sgmii function and just
matchup to the specific mode supported.

Reported-by: Tom Rini <trini@konsulko.com>
Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Suggested-by: Marek Behún <kabel@kernel.org>
Link: https://lore.kernel.org/all/b82ac325-4818-8e72-054b-640268dbf806@mailbox.org/
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-05-05 17:48:44 -04:00
Rasmus Villemoes
0b99afec9c phy: realtek: don't duplicate genphy_startup
rtl8211e_startup() is an exact copy of genphy_startup(). Use that
instead of duplicating it.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-05-05 17:48:44 -04:00
Rasmus Villemoes
8c0ed61390 phy: broadcom: don't duplicate genphy_startup
Functionally, bcm_cygnus_startup() is an exact copy of
genphy_startup().

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-05-05 17:48:44 -04:00
Stefan Herbrechtsmeier
2900342961 net: phy: gmii2rgmii: Support external rgmii-id phy
Read the phy mode of the external phy from the device tree if available
and check that it is a RGMII variant.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
2023-05-05 17:48:44 -04:00
Elmar Psilog
96d58ecac8 Let the EQoS in imx8mp handle fixed-phy too.
Without that patch it lost track to the node to scan
speed and duplex.
Patch was created by Marek Vasut, just tested by me.

Signed-off-by: Elmar Psilog <epsi@gmx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-05-05 17:48:37 -04:00
Ioana Ciornei
8491a7e4ed drivers: net: fsl-mc: fix MAC address fixup procedure
In the process of adopting CONFIG_DM_ETH on the DPAA2 based platforms,
interfaces which were previously defined as "xgmii" were transitioned to
be defined as "xfi" in the DTS.
See the commit below for reference:
commit 87274918f2 ("arm: dts: ls2088ardb: add DPMAC and PHY nodes")

Then Vladimir's commit replaced all occurrences of "xfi" with
"10gbase-r" in an effort to make U-Boot work with the same device tree
as Linux.
commit 77b11f7604 ("net: replace the "xfi" phy-mode with "10gbase-r"")

These changes to the phy_interface_t of an Ethernet port meant that the
mc_fixup_mac_addrs() function was no longer capable to properly fixup
the MAC addresses. The problem arises from the fact that the hardcoded
information about an interface (wriop_get_enet_if()) was no longer
matching any actual device.

For example, the function tried to search for "DPMAC1@xgmii1" by name
using eth_get_dev_by_name() when only "DPMAC1@10gbase-r" was available.

This function removes the need to rely on the hardcoded information by
iterating through all the UCLASS_ETH devices which are DPAA2 and request
a fixup for each of them.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-05-05 13:41:55 -04:00
Ioana Ciornei
3f1983d460 drivers: net: ldpaa: export driver name and API to get DPMAC id
Export the ldpaa_eth_get_dpmac_id() function so that it can be used from
other drivers, especially by fsl-mc which will need it the next patch.
Also, create a macro for the Ethernet ldpaa driver name and export it as
well.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2023-05-05 13:41:55 -04:00
Tim Harvey
1416b80de4 net: ksz9477: add port_probe function to config phy
Add a port_probe function to configure the phy. This leads to
earlier link negotiation so the port is more likely to be ready
when used.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-05-05 13:41:55 -04:00
Tim Harvey
2b7252953c net: ksz9477: remove unnecessary variable
We don't do anything useful with the master dev, so remove the variable.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-05-05 13:41:55 -04:00
Tim Harvey
38482d6596 net: ksz9477: remove unnecessary dsa_set_tagging call
packet tagging is not used for this driver so we do not need to
call dsa_set_tagging.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-05-05 13:41:55 -04:00
Phong Hoang
07679b1172 net: rswitch: Add Renesas Ethernet Switch
This patch adds Ethernet Switch support that found on R-Car S4
(r8a779f0) SoC. This is extracted from multiple patches from
downstream BSP, with additional rework of the network device
registration.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Marek: Rework the driver to support all ports via subdrivers.
        Split the driver up, add generic PHY framework support.
	Generic code clean ups.]
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-16 16:18:29 +02:00
Samuel Holland
93f93fe4cd net: sun8i-emac: Remove the SoC variant ID
Now that all differences in functionality are covered by individual
flags, remove the enumeration of SoC variants.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
3cfb1e6914 net: sun8i-emac: Use common syscon setup for R40
While R40 puts the EMAC syscon register at a different address from
other variants, the relevant portion of the register's layout is the
same. Factor out the register offset so the same code can be shared
by all variants. This matches what the Linux driver does.

This change provides two benefits beyond the simplification:
 - R40 boards now respect the RX delays from the devicetree
 - This resolves a warning on architectures where readl/writel
   expect the address to have a pointer type, not phys_addr_t.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
0e148342f7 net: sun8i-emac: Add a flag for the internal PHY switch
Describe this feature instead of using the SoC ID.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
c5ac4b160f net: sun8i-emac: Add a flag for RMII support
Describe this feature instead of using the SoC ID.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
c86d47328e net: sun8i-emac: Add a structure for variant data
Currently, EMAC variants are distinguished by their identity, but this
gets unwieldy as more overlapping variants are added. Add a structure so
we can describe the individual feature differences between the variants.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:20 +01:00
Tom Rini
965f74b5b3 Merge branch 'master_sh/gen4/initial' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Initial R-Car Generation 4 support
2023-04-07 15:55:50 -04:00
Hai Pham
c2fbaaf3dc net: ravb: Add R-Car Gen4 support
Add support for R-Car Gen4 SoCs and a matching DT compatible.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop SoC specific compatible, use RCAR_64 Kconfig symbol, update commit message]
2023-04-07 17:13:28 +02:00
Marek Vasut
b6fcab0728 net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux
Pull Marvell 10G PHY driver from Linux 6.1.y as of commit
d6d29292640d3 ("net: phy: marvell10g: select host interface configuration")
and heavily adapt to match U-Boot PHY framework. Support for
hwmon is removed as is much other functionality which could
not be tested, this results in much simpler driver which can
only bring the PHY up and set MAC type.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:21:37 +02:00
Marek Vasut
87b7502824 net: phy: Add phy_modify_mmd() and phy_modify_mmd_changed() from Linux
Add phy_modify_mmd()/phy_modify_mmd_changed() from Linux 5.1.y as of commit
b8554d4f7288f ("net: phy: add register modifying helpers returning 1 on change")
This is used by the upcoming Marvell 10G PHY driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:21:37 +02:00
Marek Vasut
bf3dabb7de net: phy: marvell: Import and use marvell_phy.h from Linux
Import marvell_phy.h from Linux 5.14.y as of commit
a5de4be0aaaa6 ("net: phy: marvell10g: fix differentiation of 88X3310 from 88X3340")
and use it in marvell PHY driver instead of current ad-hoc macros.
Two of the PHY IDs are unknown to Linux, 88E1149S and 88E1680, for
those two, only sync the length of the hexadecimal number to 8 digits.

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:21:37 +02:00
Marek Vasut
75d28899e3 net: phy: Synchronize PHY interface modes with Linux
Synchronize PHY interface modes with Linux next 6.2.y commit:
0194b64578e90 ("net: phy: improve phy_read_poll_timeout")

Retain LX2160A/LX2162A PHY modes as those are not yet supported
by the Linux kernel, but isolate those with ifdeffery.

Isolate NCSI which are also not supported by Linux kernel. Note
that the ifdeffery cannot be avoided with IS_ENABLED() here due
to compilation of the entire conditional, which would fail in
case NCSI symbols are not available.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:20:53 +02:00
Marek Vasut
166ea49750 net: mvpp2: Replace PHY_INTERFACE_MODE_SFI with 5GBASER/10GBASER/XAUI
Replace PHY_INTERFACE_MODE_SFI with PHY_INTERFACE_MODE_5GBASER,
PHY_INTERFACE_MODE_10GBASER and PHY_INTERFACE_MODE_XAUI to match
Linux PHY interface modes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:20:53 +02:00
Marek Vasut
6b1948d81a net: mvpp2: Drop PHY_INTERFACE_MODE_SGMII_2500 support
This mode does not seem to be well defined and used anywhere, remove support for it.
Based on discussion:
- 1000baseX does c37 AN of duplex+pause
- SGMII does AN of duplex+pause+speed, at lower speed bytes are repeated 10x/100x
- 2500baseX does not do AN, or does very different c73 AN
- SGMII 2500 behavior is unclear

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:20:53 +02:00
Marek Vasut
9461d73de9 net: phy: Only call phy_init() on systems needing manual relocation
The phy_init() is now used only to perform manual relocation of PHY
driver callbacks. Wrap it in ifdeffery and only call it on systems
which still require manual relocation, i.e. m68k .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:51 +02:00
Marek Vasut
c878e70beb net: phy: Re-inline phy_drv_reloc()
Wrap phy_drv_reloc() back into phy_init() to reduce ifdeffery,
since phy_drv_reloc() is now called only from one call site.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:51 +02:00
Marek Vasut
7da03bbc57 net: phy: Drop unused phy_register()
This function is no longer used, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:51 +02:00
Marek Vasut
8728d4c032 net: phy: Drop static phy_drivers list
The static phy_drivers list is superseded by linker list of struct phy_drivers
now that all drivers have been converted to the later. Drop the phy_drivers
list as well as list_head from struct phy_driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:51 +02:00
Marek Vasut
20bd8e4fcb net: phy: gen10g: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:51 +02:00
Marek Vasut
f7053296cb net: phy: genphy: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:51 +02:00
Marek Vasut
53ef8d79f2 net: phy: xilinx-gmii2rgmii: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
81a8728c83 net: phy: ncsi: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
7f4e6c2ae1 net: phy: fixed: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
5c359aa712 net: phy: mscc: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
330d64f5a0 net: phy: intel-xway: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
6620b9204d net: phy: xilinx: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
fb5cf1bb42 net: phy: vitesse: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
5b777fe527 net: phy: ti: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

This particular PHY driver is slightly more spread out across additional
source files. Since the phy_register() calls are no longer necessary, all
the registration calls across those source files is dropped. Furthermore,
the Makefile can now be updated to only compile generic TI PHY support if
matching Kconfig symbol is enabled and the ifdeffery in the generic TI PHY
driver can be dropped.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
787a67f471 net: phy: teranetics: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
2ea350c466 net: phy: smsc: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
f2e0be396e net: phy: realtek: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:50 +02:00
Marek Vasut
1965f2aa65 net: phy: nxp-tja11xx: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
d1296d44de net: phy: nxp-c45-tja11xx: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
390e3fcd4e net: phy: natsemi: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
3b96dc7513 net: phy: meson-gxl: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
6b5eea7508 net: phy: ksz90x1: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
f282e32d0a net: phy: ksz8xxx: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
9010be953e net: phy: marvell: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
f10c893815 net: phy: lxt: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
b20c53a93f net: phy: et1011c: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
abdbfad25c net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
7e9ce5adf6 net: phy: davicom: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:49 +02:00
Marek Vasut
579f359269 net: phy: cortina: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
227650f0e7 net: phy: ca_phy: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
c00f3f826f net: phy: broadcom: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
761e4060fe net: phy: b53: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
fba31ab92c net: phy: atheros: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
a5fbc10560 net: phy: aquantia: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
4de8644504 net: phy: adin: Convert to U_BOOT_PHY_DRIVER()
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.

Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
7940a93eb9 net: phy: Iterate over both registered PHYs and struct phy_driver linker list
Introduce U_BOOT_PHY_DRIVER() macro which is used to add struct phy_driver
into a new linker list section containing all compiled in struct phy_driver
drivers. This is so far empty until PHY drivers are converted over to this
macro.

Iterate over both drivers registered using soon to be legacy phy_register()
as well as drivers in the new linker list when looking up a suitable PHY
driver. This way, PHY drivers can be converted over to the new macro one
driver at a time.

The relocation of callbacks for linker list based drivers now happens in
phy_init() call as the drivers are available at that point in time, and
phy_register() is not called for those drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
9d5a38c214 net: phy: Factor manual relocation into separate function
Create separate function to implement manual relocation of PHY driver
functions and make use of that function. This is a preparatory patch
for introduction of PHY driver definition using linker lists.

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
d1569689c6 net: phy: teranetics: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
97c50ab8db net: phy: cortina: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:18:48 +02:00
Marek Vasut
3309c58a0e net: phy: ca_phy: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2023-04-07 14:17:24 +02:00
Marek Vasut
5914bec3f0 net: phy: aquantia: Staticize PHY driver entries
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07 14:15:07 +02:00
Marek Vasut
4bdc3524d7 net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
80a34e4008 net: fec_mxc: Add ref clock setup support for i.MX8M Mini/Nano/Plus
The FEC ref clock frequency on i.MX8M Mini/Nano/Plus was so far configured
via ad-hoc board code. Replace that with DM clock clk_set_rate() instead.
This way, the driver claims all its required clock and sets the ref clock
rate, without any need of architecture specific register fiddling.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
f9e950b9bf net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
2e9b3014df net: dwc_eth_qos: Add i.MX8M Plus RMII support
With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.

The board DT requires the following adjustments to EQoS node:
  phy-mode = "rmii";
  assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
  			<&clk IMX8MP_SYS_PLL2_100M>,
  			<&clk IMX8MP_SYS_PLL2_50M>;
  assigned-clock-rates = <0>, <100000000>, <50000000>;

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
158456089c net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.

The adjustment here is modeled after STM32MP15xx clock handling
in this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
a79de0808a net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC
The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
interface mode from RGMII to any other.

Since proper reset is desired in general to put the block into defined
state, always assert the DMA_MODE SWR bit before waiting for the bit
to clear itself.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
ac19125f72 net: dwc_eth_qos: Staticize eqos_inval_buffer_tegra186()
This function is only used within the driver, staticize it.

Fixes: 149e80f74b ("net: dwc_eth_qos: public some functions")
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
2e0bade785 net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32
The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
pointer is never valid. This is because only tegra186 ever claims the
phy_reset_gpio, all other platforms use the PHY framework to reset the
PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
895b05ce02 net: dwc_eth_qos: Drop bogus return after goto
The return is never triggered due to the goto just above it.
Drop it. No functional change.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Marek Vasut
6c7e559864 net: Pull board_interface_eth_init() into common code
Move the board_interface_eth_init() into common ethernet uclass code,
since this function could be shared by multiple drivers.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Mikhail Lappo
d797a8ccb2 net: ravb: Support fixed PHY in R-Car
Calling old U-Boot API doesn't allow to use fixed PHY.
Searching by mask is the part of new function, after
scanning FDT for a fixed PHY definition

Fixes: e821a7bdb1 ("net: ravb: Detect PHY correctly")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
[Hai Pham: Drop phy_connect_dev since it's called in phy_connect]
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use mask -1 instead of 0 to reinstate the search behavior
        over all PHY addresses. Add Fixes tag, sort the tag list.]
2023-03-18 12:02:38 +01:00
Algapally Santosh Sagar
6d87b1572f arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies
There are missing Kconfig dependencies in the code which is using
firmware interface.
The commit 71efd45a5f ("arm64: zynqmp: Change firmware dependency")
add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig
dependencies were properly described and also sdhci and gem drivers
didn't protect the code properly.
So, add the missing ZYNQMP_FIRMWARE dependencies.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:14:59 +01:00
Simon Glass
e6c5205d64 net: Add an SPL config for atheros
Add a new SPL_PHY_ATHEROS to avoid a build error on am335x_evm with split
config.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-03-03 09:49:02 -05:00
Simon Glass
b51b1a8442 Correct SPL uses of PHY_FIXED
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_PHY_FIXED defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:58 -05:00
Ulf Samuelsson
aa0a8a0be2 cpsw_mdio.c: Use correct reg in cpsw_mdio_get_alive
cpsw_mdio_get_alive reads the wrong register.
See page 2316 in SPRUH73Q AM335x TRM

Signed-off-by: Ulf Samuelsson <ulf@emagii.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-02-17 10:49:41 -05:00
Sergei Antonov
add396d667 net: ftmac100: add mii read and write callbacks
Register mii_bus with read and write callbacks to allow the 'mii'
command to work. Use a timeout of 10 ms to wait for the R/W
operations to complete.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
2023-02-10 13:41:07 -05:00
Sergei Antonov
9628c3e8b1 net: ftmac100: simplify priv->iobase casting
Replace 'phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in
struct ftmac100_data. It allows to remove casting in a number of places.

Since priv->iobase is phys_addr_t, use phys_to_virt() to make
a pointer from it.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-10 13:41:07 -05:00
Sergei Antonov
e9a1d8bfc9 net: ftmac100: change driver name from nds32_mac to ftmac100
So it will be named similarly to the related ftgmac100 driver.
The old name 'nds32_mac' is not referred to anywhere in U-Boot.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-10 13:41:07 -05:00
Sumit Garg
d382025dc5 net: dwc_eth_qos: Add Qcom ethernet driver glue layer
The Qualcom ETHQOS hardware supports an RGMII macro which needs to be
configured according to following link speeds:
- SPEED_1000
- SPEED_100
- SPEED_10

So add a corresponding glue driver to configure RGMII macro.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10 12:50:00 -05:00
Sumit Garg
a962b7cff4 net: dwc_eth_qos: Allow platform to override tx/rx_fifo_sz
The GMAC controller on QCS404 SoC (support added by upcoming patch) fails
to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So
allow platforms to override FIFO size using corresponding DT node
properties.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10 12:50:00 -05:00
Sumit Garg
9d53f335f6 net: dwc_eth_qos: Make eqos_get_tick_clk_rate callback optional
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10 12:50:00 -05:00
Simon Glass
24f95e141e Correct SPL uses of IMX_MODULE_FUSE
This converts 6 usages of this option to the non-SPL form, since there is
no SPL_IMX_MODULE_FUSE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00