Christian Marangi <ansuelsmth@gmail.com> says:
This series doesn't currently change anything and it does add all the
additional OPs to make support of OF_UPSTREAM.
While converting the mt7681/7686/7688/7623/7622 it was notice lots of
discrepancy between the downstream dtsi and the upstream one and the
clock ID between downstream clock ID and upstream clock ID.
Upstream reference clock by names and clock are handled by the
CCF (Common Clock Framework). The same can't be used here as we would
quickly reach the max space allocated before relocation.
The current mediatek clock driver reference all the parents and clocks
with offset from the clk ID related to the different tables.
Discrepancy between clock ID and the order in the clocks table cause
one clock referenced for another or even crash for trying to access
a clock at an offset that doesn't exist.
To handle this and permit use of OF_UPSTREAM, various measure and
changes are done to the mediatek clock driver to support it.
This series have all the generic clock changes. Once this is merged,
series for each SoC will came that will just change files in their
dedicated clock driver. This is to prevent massive patch and to
permit to split series, one for each SoC.
As said at the start, these changes doesn't cause regression and are
just expansion to the current API. Current behaviour is saved in every
possible way (aside from the first 2 patch that fixes latent bugs)
Add support for APMIXED parent in infra MUX. This is the case for mt7622
that reference APMIXED parents for the MUX1_SEL clock.
We assume the second level parent is always APMIXED.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support for GATEs for APMIXED OPs. It's possible that some APMIXED
have also gates on top of PLL. This is the case for mt7622. Add support
for this.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Upstream kernel linux might have a different clock ID order in their
<soc>-clk.h header. This is the case of some clock ID for mt7623 that
upstream use the shared header clk-mt7601.h
This header doesn't have a well distincted order and have factor or mux
in the middle of the CLK ID list. This is problematic with the mtk clock
driver that expect everything well organized in block and apply offset
to reference the clk in the different array.
To solve this problem, implement in the mtk_clk_tree an additional
option .id_offs_map, an array where each CLK ID can be remapped to what
the driver expect permitting to reorganize the clock following the
expected logic of fixed, factor, mux and gates.
Each clock function is updated to tranparently handle this by first
converting the clk ID to the remapped one.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Provide common clk init function for infrasys that defaults to topckgen
driver if clock-parent is not defined. This is the case for upstream
DTSI that doesn't provide this entry.
This is needed for infracfg driver that will make use of the unified
gates + muxes implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support for gate clock get_rate to reference topckgen clock for
infracfg-ao implementation.
In infracfg-ao implementation topckgen is on second level of parent with
infracfg in the middle.
To correctly detect this, check the driver of the dev parent and use the
second level parent if it's not mtk_clk_topckgen.
Due to all the dependency, parent tree must be filled before a gate is
used, hence is safe to assume it will be there.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As done for infracfg, also add support for parent mux from different
source for topckgen. This is needed as upstream linux doesn't use 1/1
factor and use directly the APMIXED clocks.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
There is a current limitation where parents for a mux can be all declared
as they are from a common source. This is not true as there are some MUX
that can have parent from both infracfg or from topckgen.
To handle this, implement a new flag for the mux, CLK_PARENT_MIXED, and
a new entry for the mux parent_flags.
To use this, CLK_PARENT_MIXED must be used and parent_flags will be used
instead of the parent variable.
Entry in parent_flags are just a struct of ID and flags where it will be
defined where that parent comes from with the usage of
CLK_PARENT_INFRASYS or CLK_PARENT_TOPCKGEN.
This permits to have MUX with parents from infracfg or topckgen.
Notice that with CLK_PARENT_MIXED applied the CLK_BYPASS_XTAL is
ignored.
With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the relevant parent
instead.
Also alias for the CLK_PARENT macro are provided to better clear their
usage. CLK_PARENT_MIXED require these alias that describe the clk type
to be defined in the clk_tree flags to prevent clk ID clash from
different subsystem that may have equal clk ID.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support to clk_gate ops to reference the clk ID at an offset by
using the just introduced gates_offs value from the unified muxes +
gates implementation.
Gate clock that doesn't have gates_offs set won't be affected as the
offset will simply be 0 and won't be offset of any value.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support for gates in clk_tree for infrasys ops.
Infracfg clks can have a sum of gates and muxes, and current solution
handle this by duplicating the driver and split clks for mux and clks
for gates. Upstream linux kernel handle this differently and doesn't
have this distinction.
To be closer to the upstream kernel clock definition, implement
additional logic to have gates defined in the clk_tree and implement
variant for the infrasys ops to handle gates defined in the tree.
Similar to how it's done with factor and mux, we introduce gates_offs.
Upstream kernel follow the similar logic with all the ID defined as
FDIVS, MUXES and finally GATES.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
We currently return 0 if XTAL rate is requested in get_mux_rate. This
deviates from what is done in get_factor_rate and is totally wrong as it
can cause unwanted results (division by 0 crash)
For infrasys that makes use of CLK_XTAL, assume xtal_rate to be defined
in clk_tree and return the rate when BYPASS_XTAL is not enabled with
clk ID 0 index parents.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
There is currently a massive bug that makes any gate clk that have
CLK_XTAL as parent to return the wrong clock.
Following the code, with CLK_XTAL defined as TOPCKGEN parent, the
topckgen get_rate is called. The clk ID (0) is parsed and only in some
corner case (scenario where fixed clock are not defined) the correct
XTAL rate will be returned as get_factor or get_mux is called (that have
correct handling for CLK_XTAL). With fixed clock defined, the rate that
will be returned will always be the FIRST ELEMENT of the fixed clock
table instead of the hardcoded XTAL rate.
To handle this, add additional logic and if the flag is set to
PARENT_XTAL for the gate, return the XTAL rate directly.
We assume the clk_tree to have xtal_rate defined with clk gates that
have XTAL as parents.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
This adds the CLK_XTAL macro/flag to allow modeling clocks which are
directly connected to the xtal clock.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds infrasys clock mux support for mediatek clock drivers.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds support for a clock node to configure its parent clock
where possible.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The mtk clock framework in u-boot uses array index for searching clock
parent (kernel uses strings for search), so we need to specify a special
clock with ID=0 for CLK_XTAL in u-boot.
In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
expected.
However for newer chips, they may have some clocks with ID=0 not
representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
called. Current logic will make entire clock driver not working.
This patch adds a flag to indicate that whether a clock driver needs clocks
with ID=0 to call mtk_topckgen_get_mux_rate.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
In the spirit of using the same base name for all of these related macros,
rename this to have the operation at the end. This is not widely used so
the impact is fairly small.
Signed-off-by: Simon Glass <sjg@chromium.org>
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.
This commit change the return type of mtk_clk_find_parent_rate to
ulong.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
