Observing the crash when we add the i2c-arbitrator node in the device
tree as per the DT bindings. The issue is with the child node of
i2c-arbitrator@72 i.e., i2c@f1950000->i2c-arbitrator@72->i2c-arb, as the
arbitrator uses the uclass of mux(UCLASS_I2C_MUX) and the mux uclass driver
checks for the "reg" property using the i2c_mux_child_post_bind() function,
if it won't find the "reg" property it will return -EINVAL which is leading
to the crash.
So, add the logic to check whether the child node has the "reg" property,
if the "reg" property exists then read the "reg" and update the channel.
https://www.kernel.org/doc/Documentation/devicetree/bindings/i2c/i2c-arb.txt
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Device bus address might not be valid for direct access when the bus
address and CPU address are not the same. Use dev_bus_to_phys() to
translate bus address back to CPU address.
Fixes: 3d98b8c504 ("net: designware: Invalidate RX buffer cache before freeing the DMA descriptor")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Remove duplicate .ops assignment that was overriding the correct
ti_musb_gadget_ops with musb_usb_ops (host ops) in the ti_musb_peripheral
driver. This was causing U-Boot crashes when trying to call the
handle_interrupts operation since the wrong ops structure was being used.
Fixes: 7d98dbcc3d ("usb: musb-new: Add support for DM_USB")
Fixes: 281eaf1ed8 ("usb: gadget: musb: Convert interrupt handling to usb_gadget_generic_ops")
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20250611171031.840277-1-kory.maincent@bootlin.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
The third_arg for a dfu alt is read as an integer and is overloaded for
different supported backends. For ext4 and fat, this third_arg
represents the partition and forms the dev part string, which should
have its partition in hex. This commit fixes dfu ext4/fat usage for
devices with ten or more partitions.
Signed-off-by: Ivan Pang <ipman@amazon.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Link: https://lore.kernel.org/r/20250611050127.38011-1-ipman@amazon.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
When doing the investigation for commit 53bb8fdea1 ("mmc: Kconfig:
Correct dependencies SDHCI ADMA options") I missed the implications of
MMC_SDHCI_ADMA_HELPERS. The problem is that FSL_ESDHC via the
FSL_ESDHC_SUPPORT_ADMA2 option will also enable these helper functions.
This in turn means the correct dependency here is
MMC_SDHCI_ADMA_HELPERS and not *MMC_SDHCI_ADMA.
Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This reverts commit 159b6f0e11.
Since commit 159b6f0e11 ("caam: Fix CAAM error on startup") the following
regression was reported by Tim Harvey:
"I've found that this patch causes a regression on an imx8mm board
(imx8mm_venice_defconfig) where the first call to caam_rng_read fails
here in jr_dequeue but if you call it again it works. With some
debugging added:
SEC0: RNG instantiated
...
Hit any key to stop autoboot: 0
u-boot=> rng list
RNG #0 - caam-rng
u-boot=> rng 0 10
caam_rng_read caam-rng len=16
run_descriptor_jr_idx idx=0
Error in SEC deq: -1
caam_rng_read_one run_descriptor_jr failed: -1
caam_rng_read caam-rng caam_rng_read_one failed: -5
Reading RNG failed
u-boot=> rng 0 10
caam_rng_read caam-rng len=16
run_descriptor_jr_idx idx=0
00000000: ad 2e ad c0 2a 12 27 c4 65 82 66 19 be ef f6 07 ....*.'.e.f.....
If I revert your patch caam_rng_read works initially and on subsequent
calls."
" I ran into this when I was testing
lwIP HTTPS as it causes anything that uses dm_rng to fail the first
time (such as HTTPS)."
Revert it for now to avoid the regression.
Reported-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
The val (the bits to set) is the second member of the reg_data structure
and mask the third one. We obviously want to clear bits 6 and 7 in order
to only set bit 7 in there instead of only clearing bit 7 in order to
write bits 6 and 7 (which makes no sense).
Fortunately, according to the datasheet, bit 6 value doesn't matter when
bit 7 is set so this is essentially just a cosmetic change, no intended
change in behavior.
Fixes: f172575d92 ("power: rk8xx: add support for RK806")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Allows use of the regulator functions of the RK8XX PMIC in SPL, which is
necessary to support the functionality of the Rockchip IO-domain driver
on relevant platforms.
Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Allows use of the Rockchip IO-domain driver in SPL to configure
the GPIO to match the voltage supplied by specific regulators
(e.g. "vcc_sdio").
Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Log the value of the regulators during initialization of the IO-domain
driver to aid in debugging GPIO voltage configuration problems.
Signed-off-by: Justin Klaassen <justin@tidylabs.net>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RAM_ROCKCHIP_DEBUG can be used only if DEBUG_UART is
available.
The next commit introduces changes in definition of debug
uart functions, so that DEBUG_UART is required to be defined
in order to initialize uart and use print functions.
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
This clears UHS_MODE_SELECT for timing modes <= MMC_HS_52.
When initializing to HS400 mode, the host controller downgrades to non-uhs
modes so clear UHS_MODE_SELECT at modes <= MMC_HS_52.
This fixes eMMC writes on j7200 EVM.
Fixes: 6067aa66b3 ("mmc: am654_sdhci: Add am654_sdhci_set_control_reg")
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
* Adjust fdtfile logic to support more boards
* Support linux,code variable in qcom-pmic button driver
* Minor CLK API adjustments and apq8096/msm8916 fixes
* vbus regulator register fixes
* dragonboard410c KASLR support and other fixes
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Merge tag 'qcom-more-for-2025.07' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
More Qualcomm fixes for 2025.07
* Adjust fdtfile logic to support more boards
* Support linux,code variable in qcom-pmic button driver
* Minor CLK API adjustments and apq8096/msm8916 fixes
* vbus regulator register fixes
* dragonboard410c KASLR support and other fixes
Most device vendors put "Volume Down" button onto PMIC RESIN.
But Sony is special: see
dts/upstream/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi or [1].
They put "Volume Down" on PMIC GPIO 7 where others usually put
"Volume Up", and KEY_VOLUMEUP is inside &pon_resin.
Currently if you boot U-Boot on such Sony device, you end up
with 2 "Volume Down" buttons, and no "Volume Up", which makes
navigating menu problematic.
Support reading devicetree "linux,code" property and override
statically defined button code & label based on that.
[1] https://elixir.bootlin.com/linux/v6.15-rc3/source/arch/
arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi#L263
Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Signed-off-by: Alexey Minnekhanov <alexeymin@minlexx.ru>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424014811.3809818-1-alexeymin@minlexx.ru
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
As of commit dc8754e8e4 ("clk/qcom: apq8016: improve clk_enable logging")
there are now warnings in the U-Boot console on DragonBoard 410c:
apq8016_clk_enable: unknown clk id 122
apq8016_clk_enable: unknown clk id 123
apq8016_clk_enable: unknown clk id 124
apq8016_clk_enable: unknown clk id 125
This is because we don't implement enable() properly for the SDCC clocks.
Currently they are being enabled as part of set_rate().
Fix this by moving the enable calls out of the apq8016_clk_init_sdc()
function and convert them to the equivalent GATE_CLK_POLLED() definitions.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Convert the usages of GATE_CLK() in clock-apq8016 to GATE_CLK_POLLED() to
make sure that we poll the status when enabling clocks:
- PRNG_AHB_CLK is a vote clock, so we poll a different register address.
- The USB clocks are simple branches, so enable/poll is the same register.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-5-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.
Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.
The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses:
- SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018
Should be 0x42018, this is an invalid register close to the USB clocks.
- SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018
Should be 0x43018, this is the SDCC1 clock.
When we try to enable SDCC2, we actually end up enabling SDCC1. When we try
to enable SDCC1, we just issue some broken register writes.
This hasn't caused any trouble so far, because the boot firmware is keeping
both SDCC clocks running. However, if these clocks are disabled when
entering U-Boot, MMC initialization is failing.
Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was
already correct, but change it the same way for consistency.
Fixes: 085921368b ("arm: Add support for Qualcomm Snapdragon family")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Change the return value for timeout errors in i2c-designware from 1 to
-ETIMEDOUT. Returning errors as negative values is standard practice in the
u-boot, which enhances error handling consistency across the codebase.
The current behavior can lead to silent errors when functions check for
negative return values to identify errors. For example, in
`dm_i2c_reg_read` from i2c-uclass.c, a timeout results in an uninitialized
value being returned, potentially causing unexpected behavior.
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wojciech Szamocki <wojciech.szamocki@nokia.com>
Signed-off-by: Wojciech Szamocki <wojciech.szamocki@nokia.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If the MII interface is used, the PHY is the clock master, thus don't
set the clock rate. On Zynq-7000, this will prevent the following
error:
zynq_gem ethernet@e000b000: failed to set tx clock rate 25000000
Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de>
Link: https://lore.kernel.org/r/20250415150400.136723-1-martin.kaistra@linutronix.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.
This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is
going to write to GEM0's registers wrong value, leaving GEM0 unusable)
Signed-off-by: Frantisek Bohacek <rutherther@ditigal.xyz>
Link: https://lore.kernel.org/r/20250522060703.4863-1-rutherther@ditigal.xyz
Signed-off-by: Michal Simek <michal.simek@amd.com>
FPGA configuration encounters failure when the cache is not flushed.
Add cache flushing to the memory region that holds the FPGA
configuration bitstream.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Link: https://lore.kernel.org/r/20250506012851.30039-1-nareshkumar.ravulapalli@altera.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The pcireg base is not assigned to any address, reading the
pcireg base with PS_LINKUP_OFFSET which is incorrect and
giving random values. So update the pcireg base from
devicetree so that we can read the valid PCIE link status
and PHY ready status.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/20250516092314.939424-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The way we enable ULPI support today isn't something that should work.
The "optional" keyword in a choice statement is not a documented
feature. To make this work in a supported way, make USB_ULPI something
we ask about if USB_HOST is set. Next, we move the choice of what
viewer to use to be after the framework portion and to depend on that.
We then borrow a few words from the top-level README to make the help
text here clearer. Finally we make the Qualcomm driver select ULPI as
it's required and we make the tegra driver not duplicate a check that
Kconfig now handles for us.
Signed-off-by: Tom Rini <trini@konsulko.com>
The last platform to enable this driver was removed in 2019. Remove this
unused code and documentation now.
Signed-off-by: Tom Rini <trini@konsulko.com>
dwc3_core_init loops 'timeout' times to check if the IP block is out
of reset using 'while (timeout--)'. If there is some issue and
the block doesn't come out of reset, the loop will run till
'timeout' becomes zero and the post decrement operator would set
timeout to 0xffffffff. Though the IP block is not out reset, the
subsequent if check 'if !timeout' would fail as timeout is not
equal to zero and the function proceeds with the initialization.
Use poll API instead to resolve this.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
In rare cases U-Boot returns an error message when intantiating the RNG
of the CAAM device:
“SEC0: RNG4 SH0 instantiation failed with error 0xffffffff”
This means, that even when the CAAM device reports a finished
descriptor, none is found in the output ring.
This might be caused by a missing cache invalidation before
reading the memory of the output ring
This patch moves the cache invalidation of the output ring from start of
the job to immediately after the notification from hardware where the
output ring will be read.
Signed-off-by: Olaf Baehring <olaf.baehring@draeger.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
The driver is adapted from Linux kernel's version of clk-th1520-ap.c,
with only output clocks for external sensors, which are barely useful in
bootloaders, removed.
Same as the mainline driver, it currently lacks of ability to enable and
reconfigure PLLs, which could be implemented later.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This patch cleans the vendor code of DDR initialization up, converts the
driver to fit in DM framework and use a firmware[1] packaged by binman to
ship PHY configuration.
Currently the driver is only capable of initializing the controller to
work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
That's how it looks like without CONFIG_MMC_SUPPORTS_TUNING before the
patch:
aarch64-buildroot-linux-gnu-ld.bfd: drivers/mmc/cv1800b_sdhci.o: in function `cv1800b_execute_tuning':
drivers/mmc/cv1800b_sdhci.c:47:(.text.cv1800b_execute_tuning+0x50): undefined reference to `mmc_send_tuning'
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
With commit cc4e8af2c5, fsl_enetc register accessors have been split to
handle different register offsets on different SoCs. However, for
internal MDIO register calculation, only ENETC_PM_IMDIO_BASE was fixed
without adding the SoC specific MAC register offset.
As a result, the network support for the Kontron SMARC-sAL28 and
probably other boards based on the LS1028A CPU is broken.
Add the SoC specific MAC register offset to calculation of imdio.priv to
fix this.
Fixes: cc4e8af2c5 ("net: fsl_enetc: Split register accessors")
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # LS1028A
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx95_19x19_evk
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
On 32-bit systems, e.g. i.mxrt-1170 fdt_addr_t may only be 32-bit.
Cast to a "long long" for garbage avoidance.
Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
The flexspi on different SoCs may have different number of LUTs.
So involve lut_num in nxp_fspi_devtype_data to make distinguish.
This patch prepare for the adding of imx8ulp.
Fixes: ef89fd56bdfc ("arm64: dts: imx8ulp: add flexspi node")
Cc: stable@kernel.org
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20240905094338.1986871-3-haibo.chen@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(Picked from linux 190b7e2efb1ed8435fc7431d9c7a2447d05d5066)
Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
The commit ac30d90f33 ("clk: Ensure the parent clocks are enabled
while reparenting") add a call to clk_enable() for the parent clock.
For clock drivers that do not implement the enable() ops, like most
Rockchip clock drivers, this now cause the set_parent() ops to never
be called when CLK_CCF=n (default for Rockchip).
clk_enable() typically return -ENOSYS when the enable() ops is not
implemented by the clock driver, with CLK_CCF=y clk_enable() instead
return 0 when the enable() ops is unimplemented.
Change to ignore -ENOSYS from the newly introduced clk_enable() call to
fix this regression and restore the old behavior of set_parent() ops
being called regardless of if enable() ops is implemented or not.
Fixes: ac30d90f33 ("clk: Ensure the parent clocks are enabled while reparenting")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Dang Huynh <danct12@riseup.net>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Currently, Synopsis xgmac driver only works if DMA region is under 4GB.
This change enables the DMA buffers allocations above 4GB memory
regions.
Signed-off-by: Nikunj Kela <nikunj.kela@sima.ai>
This file was using IS_ENABLED() to test for CONFIG flags but omitted
the CONFIG_ prefix and so did not work as expected.
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for Skyworks AAT2870 LED Backlight Driver and Multiple LDO
Lighting Management Unit. Only backlight is supported as for now. Supported
backlight level range is from 2 to 255 with step of 1.
Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
LG LH400WV3-SD04 is a color active matrix TFT (Thin Film Transistor)
liquid crystal display (LCD). The resolution of a 4" contains 480 x 800
pixels.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Hitachi TX10D07VM0BAA is a color active matrix TFT (Thin Film Transistor)
liquid crystal display (LCD). The resolution of a 4" contains 480 x 800
pixels.
Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add support for 8-bit CPU driven (primary and secondary) display signal
interface found in Tegra 2 and Tegra 3 SoC.
Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
MAX8907 PMIC has embedded poweroff function used by some device to initiane
device power off. Implement it as optional sysreset driver guarded by
kconfig option and system-power-controller device tree property.
Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Added a new regulator driver for the MAXIM MAX8907 PMIC, providing
essential regulator functionalities and incorporated the necessary binding
framework within the core PMIC driver.
Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
