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Merge tag 'v2025.04-rc4' into next
This uses Heinrich's merge of lib/efi_loader/efi_net.c which results in
no changes.
When an error is detected in the TSEC receive path, the driver currently
prints an error message, but leaves the corresponding packet descriptor
in its old state (i.e. owned by the CPU side). As a result, the packet
queue can be starved of available buffers if enough errors happen.
To recover from errors, re-arm the packet buffer descriptor after an
error has been detected.
Errors can be provoked by changing a PHY with phy-mode = "rgmii-id" to
phy-mode = "rgmii".
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This is necessary for the following patch. No functional change.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Neither bb_miiphy_buses nor bb_miiphy_buses_num are used anymore.
Drop both of them.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Instead of doing another lookup, trivially access the struct mii_dev
embedded in struct bb_miiphy_bus . No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Instead of doing another lookup, trivially access the struct mii_dev
embedded in struct bb_miiphy_bus . No functional change.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The struct bb_miiphy_bus embeds struct struct mii_dev, which
already contains one copy of name field. Drop the duplicate
top level copy of name field.
The a38x code does static assignment of disparate names, use
snprintf(...) to fill in matching name in probe to avoid any
breakage.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Replace the name based look up in bb_miiphy_getbus() with trivial
container_of() call. This works because the struct bb_miiphy_bus
always embeds the matching struct mii_dev . This also makes the
code much simpler and more efficient.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks
currently listed in bb_miiphy_buses[] array. This is a temporary
duplication of assignment to avoid breakage, which will be removed
in follow up patches. At this point, the bb_miiphy callbacks can
reach these accessors by doing container_of() on struct mii_dev.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks
currently listed in bb_miiphy_buses[] array. This is a temporary
duplication of assignment to avoid breakage, which will be removed
in follow up patches. At this point, the bb_miiphy callbacks can
reach these accessors by doing container_of() on struct mii_dev.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks
currently listed in bb_miiphy_buses[] array. This is a temporary
duplication of assignment to avoid breakage, which will be removed
in follow up patches. At this point, the bb_miiphy callbacks can
reach these accessors by doing container_of() on struct mii_dev.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Introduce bb_miiphy_alloc()/bb_miiphy_free() wrappers to allocate and free
struct bb_miiphy_bus. Make struct bb_miiphy_bus wrap struct mii_dev, which
will become useful later in bb_miiphy_bus accessors, which would be able
to access struct bb_miiphy_bus using container_of, even if the PHY stack
only passes in the inner struct mii_dev .
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Pull the bbmiiphy initialization code from designware_eth_probe() into
dedicated function, dw_bb_mdio_init(), just like all the other MDIO
initialization functions.
Keep check for "snps,bitbang-mii" in the designware_eth_probe(), so the
driver can initialize this MDIO only in case the property is present,
and initialize regular DW MDIO in case it is not present.
The dw_bb_mdio_init() allocates its own MDIO instance, because thus far
code gated behind "snps,bitbang-mii" did depend on allocation of MDIO bus
by the other two MDIO bus options and then rewrote the newly allocated
MDIO bus callbacks, which is wrong, instead allocate proper MDIO bus with
the correct callbacks outright.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
There is literally one single bbmiiphy bus in this driver,
remove the bus index handling.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
The .init callback is not called by any function, drop it.
There are no more users of the init callback, drop the entire
mechanism.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Move the bb_miiphy functions before MDIO registration. This is a
preparatory patch, the functions will be referenced around the MDIO
registration in the follow up patches. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Move the bb_miiphy functions before MDIO registration. This is a
preparatory patch, the functions will be referenced around the MDIO
registration in the follow up patches. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Move the bb_miiphy functions before MDIO registration. This is a
preparatory patch, the functions will be referenced around the MDIO
registration in the follow up patches. No functional change.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This is unnecessary, the unset structure member is initialized to
NULL by default, drop the assignment.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The init function does nothing, the bb_miiphy_init() already checks
whether the .init callback is assigned, and if not, skips calling it.
Remove the empty init function. The entire init callback will be
removed in follow up patches.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The init function does nothing, the bb_miiphy_init() already checks
whether the .init callback is assigned, and if not, skips calling it.
Remove the empty init function. The entire init callback will be
removed in follow up patches.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The PCS exists only in GMAC1 and relates to SGMII interface and
is used to control the SGMII PHY.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
[trini: Adjust slightly for white space and to move 'start' to within if
block]
Update the debug() print, use __func__ to always print matching
function name, and also print bus name in case there are multiple
busses.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Replace ifdeffery with plain debug() function call. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The TI DP83822 does have support for configurable RGMII RX/TX clock
shift, add support for parsing DT properties which describe the RX/TX
clock shift configuration and configuration of the matching bits in
RCSR register.
The shift is only configurable on DP83822, the other PHYs supported
by this PHY driver, namely DP83825/DP83826 variants, do not implement
this functionality and the RCSR bits used to configure the clock shift
are missing from those PHYs.
The shift is configurable separately for RX and TX path. Each path can
either enable the shift or disable the shift using single bit. In case
the shift is disabled, a delay of 0ns is added to the path, otherwise
a delay of 3.5ns is added to the path.
Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12
enables RX internal shift when SET, while RCSR bit 11 enables TX shift
when UNSET.
Signed-off-by: Marek Vasut <marex@denx.de>
These functions can be static as they are referenced only in this file.
Make them static. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
It seems that every remaining system which enables BITBANGMII also
enables BITBANGMII_MULTI . Remove the BITBANGMII_MULTI symbol and
assume it is always enabled. This allows removal of a bit of legacy
code. No functional change intended.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
The ENETCv4 port DT nodes on i.MX95 may contain optional clock phandle
to IMX95_CLK_ENETREF "ref" clock. These "ref" clock must be enabled for
the ethernet to work. These "ref" clock are enabled after cold boot, but
when the system booted Linux and rebooted, those "ref" clock might have
been disabled in the process, which would make ethernet inoperable after
reboot. Make sure those "ref" clock are always correctly enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
1. Bug fixed for doorbell in secure device manager mailbox driver
2. Enhancement on SoCFPGA dwc_eth_xgmac driver
3. Enhancement on DW MAC driver
4. Improved the error message and status for SoC64 device FPGA
configuration driver
5. Updated existing watchdog in system manager to support new SM device
This patch adds support for configuring the ethernet MAC mode independently
from the PHY mode on our SoC FPGA board. Specifically, this is necessary
for a scenario where the ethernet controller MAC is connected to the
FPGA HVIO with a different GMII interface, and the FPGA output is routed
to the PHY using a RGMII interface.
To support this configuration, a mechanism is introduced to handle
separate MAC mode settings, ensuring that the MAC controller and PHY
can operate correctly with their respective interface modes.
If mac-mode is not defined, the MAC mode will default to the PHY mode,
ensuring compatibility and proper operation between the MAC and PHY.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Agilex5 having several ethernet instance, adding the device
name at the error message to differentiate between which
instance is having issue.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
An issue was identified where selecting the phy-mode as
rgmii-id in the device tree source (DTS) would cause the
`dwc_eth_xgmac_socfpga` driver to raise an unsupported phy mode error.
From the MAC controller's perspective, the rgmii and rgmii-id
phy modes are effectively identical. To address this, both
modes will now be configured to rgmii in the MAC controller.
This change ensures that the rgmii-id phy mode is properly
supported without error.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
This patch adds support for the "rgmii-id", "rgmii-rxid", and
"rgmii-txid" modes for the dwmac_socfpga driver.
Signed-off-by: Rufus Segar <rhs@riseup.net>
Michael Chang <zhang971090220@gmail.com> says:
I am resubmitting the patch titled "Add bitbang feature for npcm8xx
and driver" for review and inclusion in the upstream project.
Driver didn't support bitbang feature.
Add bb_miiphy_bus function for driver and open feature for npcm8xx
the log is as below:
-------------------------------------------------
U-Boot 2024.10-g30b9cdaf2df5-dirty (Jan 09 2025 - 00:57:37 +0000)
CPU-0: NPCM845 A1 @ Model: Nuvoton npcm845 Development Board (Device Tree)
DRAM: 1 GiB
RNG: NPCM RNG module bind OK
OTP: NPCM OTP module bind OK
AES: NPCM AES module bind OK
SHA: NPCM SHA module bind OK
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
Core: 649 devices, 28 uclasses, devicetree: separate
WDT: Not starting watchdog@901c
MMC: sdhci@f0842000: 0
Loading Environment from SPIFlash... SF:
Detected w25q512jvq with page size 256 Bytes, erase size 64 KiB,
total 64 MiB
OK
In: serial@0
Out: serial@0
Err: serial@0
Net: eth0: eth@f0802000, eth1: eth@f0804000, eth3: eth@f0808000
Hit any key to stop autoboot: 0
U-Boot>
U-Boot>
U-Boot>setenv ipaddr 192.168.16.3
U-Boot>ping 192.168.16.12
eth@f0802000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0802000
eth@f0804000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0804000
Speed: 100, full duplex
Using eth@f0808000 device
host 192.168.16.12 is alive
Link: https://lore.kernel.org/r/20250117104540.1580343-1-zhang971090220@gmail.com
Add bb_miiphy_bus function for designware bitbang feature.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Michael Chang <zhang971090220@gmail.com>
This patch adds support for MediaTek MT7987.
MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs
which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be
connected to a dedicated GMAC.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also
some ethernet switch initialization code. As we may add more switch
support in the future, it's better to move them out of mtk_eth.c to
avoid increasing the code complexity.
Since not all switches are supported for a particular board, Kconfig
options are added to allow user to select which switch should be
built into u-boot. If multiple switches are selected, auto-detecting
can also be enabled.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
i.MX95 uses enetc version 4.1 controller. Update the enetc for i.MX95.
Add ARM-specific cache handling and i.MX95 specific register layout
handling.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Clean up
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
The verdor ID and device ID of i.MX95 EMDIO are different from LS1028A
EMDIO, so add new vendor ID and device ID to pci_device_id table to
support i.MX95 EMDIO.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Clean up
Signed-off-by: Ye Li <ye.li@nxp.com>
The netc-blk-ctrl driver is used to configure Integrated Endpoint
Register Block (IERB) and Privileged Register Block (PRB) of NETC.
For i.MX platforms, it is also used to configure the NETCMIX block.
The IERB contains registers that are used for pre-boot initialization,
debug, and non-customer configuration. The PRB controls global reset
and global error handling for NETC. The NETCMIX block is mainly used
to set MII protocol and PCS protocol of the links, it also contains
settings for some other functions.
Note the IERB configuration registers can only be written after being
unlocked by PRB, otherwise, all write operations are inhibited. A warm
reset is performed when the IERB is unlocked, and it results in an FLR
to all NETC devices. Therefore, all NETC device drivers must be probed
or initialized after the warm reset is finished.
Ported from Linux 6.13-rc as of commit
fe5ba6bf91b3 ("net: enetc: add initial netc-blk-ctrl driver support")
Signed-off-by: Marek Vasut <marex@denx.de>
Pass struct udevice * into the register accessors, so the accessors can reach
driver data, which contain device specific register offsets.
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce driver data for each PCI device. The driver data carry
offsets of registers which differ between different SoCs.
Signed-off-by: Marek Vasut <marex@denx.de>
Split register accessors to the port base/station interface/port/mac
registers as those are at different offsets on different SoCs. This
is a preparatory patch which will allow addition of adjusted offsets
for new SoCs easily.
Signed-off-by: Marek Vasut <marex@denx.de>
