Use dev_phys_to_bus() to convert CPU addresses of DMA descriptors
into bus addresses of DMA descriptors. This is necessary on hardware
which does not have 1:1 mapping between CPU and memory addressed by
the DMA. This has no impact on other hardware which does not need
this conversion.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
After a warm reboot, the PHY is left in power-down state
(BMCR_PDOWN set) causing auto-negotiation to timeout when
running the dhcp command.
Fix this by calling phy_reset() in dp83867_config() which
brings the PHY to a known clean state. The existing
DP83867_SW_RESTART is removed as it is redundant after phy_reset().
Fixes: 721aed79126b ("net: phy: Add support for Texas Instruments DP83867")
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
At the very early stage when PHY ID is being auto-detected, the
PHY device is not yet instantiated and rswitch_etha .phydev is
still NULL. Add missing check for this condition and perform C22
fallback access in this PHY ID auto-detection case.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The HIFEMAC_ETH functionality can only work with both DM_ETH_PHY and
DM_MDIO enabled (it calls one of the functions that requires both), so
express this dependency in Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds support for RTL8125d. Its chip version is 0x6a.
Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
[jf: add missing comma]
Signed-off-by: Jerome Forissier <jerome.forissier@arm.com>
Functionally, both networking stacks require DM_ETH. This is because
they both also require some networking devices to be enabled. Express
this more correctly by having both NET and NET_LWIP select NETDEVICES.
In turn NETDEVICES no longer depends on NET or NET_LWIP as it's not
prompted anymore.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
- Add a call to phy_reset() in ksz9031_config() to ensure the PHY is
properly reset during initialization.
- This clears the power-down bit and ensures the PHY recovers correctly
after Linux reboot.
Tested on Agilex5 hardware with KSZ90X1 PHY.
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
- Move DMA software reset and pad calibration in xgmac_start() to occur
after the PHY is initialized and connected.
- This ensures the PHY is ready before performing these operations,
which is necessary for proper recovery after reboot.
This change fixes issues where the PHY did not recover from power-down
state after a Linux reboot, for the board using Micrel KSZ90x1 PHY.
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
As exposed by "make randconfig", we have a few dependency issues with
some network drivers:
- Both HIFEMAC_ETH and HIGMACV300_ETH functionally require both DM and
OF_CONTROL. Further, HIFEMAC_ETH needs DM_CLK not just CLK to be
selected.
- BNXT_ETH deals with it's PCI requirement in a backwards way. The
symbol PCI_INIT_R is board specific, PCI alone is required to build.
Signed-off-by: Tom Rini <trini@konsulko.com>
Airoha PCS driver depends on ARCH_AIROHA, so it should not be built
by allyesconfig configuration.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Airoha switch mdio maybe used not only by GDM1, but also by other GDM
ports (ex: as21xxx phy connected to GDM2 port). So it's better probe
airoha switch mdio a bit early in the airoha_eth_probe() code.
Also remove useless eth_phy_set_mdio_bus() call and related code.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
The implementation of FW_LOADER requires CMDLINE to be enabled, and
expressses this. In order to not have to have every users also depends
on CMDLINE introduce SUPPORTS_FW_LOADER. This depends on CMDLINE and
ENV_SUPPORT and then we have all users depends on SUPPORTS_FW_LOADER.
Signed-off-by: Tom Rini <trini@konsulko.com>
The Zynq GEM TX status register retains the transfer‑complete bit
until it is explicitly cleared. The current flow waits for
transfer‑complete but never clears it, so on the next send the wait
loop returns immediately because transfer‑complete is already high.
This causes the driver to report TX completion before the new DMA
transfer has actually finished, which breaks back‑to‑back
transmissions. This issue causes timeouts during LWIP TFTP transfers
when cache coherency is enabled.
Fix this by explicitly clearing transfer‑complete (write‑to‑clear)
after the wait completes, so each transmit starts with a clean TXSR.
Co-developed-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Co-developed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f354680d43fba0f590a6fae693848e5bf7114ba5.1772437409.git.michal.simek@amd.com
Pull request net-20260312.
net:
- Move network PHY under NETDEVICES
- s/DM_CLK/CLK/ in HIFEMAC_{ETH,MDIO}
- Add support for Airoha AN8811HB PHY
- airoha: PCS and MDIO support for Airoha AN7581 SoC
net-lwip:
- Fix issue when TFTP blocksize is >8192
- Adjust PBUF_POOL_SIZE/IP_REASS_MAX_PBUFS for better performance and
resource usage.
- Enable mii command for NET_LWIP
A number of network PHY drivers have Kconfig dependencies on various
network drivers under NETDEVICES. This is in addition to logical
dependencies of network PHYs needing network drivers. Resolve the
Kconfig problems by moving the network PHY lines to be after the network
devices, within the overall NETDEVICES guard.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
For enabling the clock driver we use symbol CONFIG_CLK.
Select this symbol for the HiSilicon Fast Ethernet Controller driver.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Current code just bind mt7531 mdio with it's driver, so mdio device may
not be probed and hense not usable.
This patch:
* Forces probing of mt7531 mdio for GDM1 port
* Renames the mt7531 mdio bus interface to 'mt7531-mdio'. We may have
multiple available MDIO, so the name 'mdio' isn't descriptive enough.
* Sets mdio bus for the GDM port device
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
It's not possible to disable PCS support just now, an7581 u-boot will not
compile. This patch fixes an issue.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add required changes to call PCS function to configure the Serdes Port.
The Ethernet driver is adapted following Upstream Kernel node structure.
Function calling order is the same of Phylink upstream kernel.
With the PCS support, also add support for attaching PHY. With
"in-band-status" set in DT for the managed property, a rudimental
support for SFP module is present.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
pcs-airoha-common.o should not build unconditionally,
also make building rules looks better.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add support for Airoha PCS driver present on AN7581 SoC.
This is needed to configure the Serdes port for the different PHY mode.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Call airoha_switch_init() before creating GDM instances, so if
allocation of GDM port fails, early created GDM instances will work
normally.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
We should not call airoha_fe_init() from GDM port independent code,
because it do a GDM specific things.
Makes airoha_fe_maccr_init() and airoha_fe_init() port dependent
and call them from airoha_eth_port_probe()
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Declare airoha_eth_port as U_BOOT_DRIVER(), fix airoha_alloc_gdm_port()
to lookup a driver instead of direct airoha_eth_port usage.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
In the case of an7581 possible GDM port id are: 1, 2 and 4.
Initialization of port GDM4 will lead to out of boundary writing
to gdm_port_str[] array.
Let's increase the array size by 1 to avoid it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Rework the driver to support multiple GDM port. The driver is split to
main driver as a MISC driver with forced probe (by using the
DM_FLAG_PROBE_AFTER_BIND) and each GDM port register a ETH driver.
This permit a 1:1 implementation with the linux kernel driver and permit
to use the same exact DT nodes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Instead of having duplicate priv struct for mdio-mt7531-mmio driver in
both driver and header, use the one exposed by the header directly.
This make sure we have consistent priv struct if the driver will be
updated in the future.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Rockchip RK3506 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.
Add initial support for the RK3506 GMAC variant.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
Christian Marangi <ansuelsmth@gmail.com> says:
This small series consolidate header usage of mdio-mt7531-mmio driver
and improve usage in preparation for support of OF PHY autoprobe.
This driver is still not used (as it will be used by AN7581/AN7583)
in the OF mode (it's used by MT7988 for the MDIO functions)
For OF PHY to be correctly autoprobed, the MDIO driver needs to attached
to the MDIO node (the parent of the PHY nodes)
With such change the MDIO driver can be binded with the MDIO node instead
of the switch node as previously required.
Link: https://lore.kernel.org/r/20260209114515.1916-1-ansuelsmth@gmail.com
The MDIO node is ALWAYS a parent of the MT7531 switch node and the MDIO
registers are in the MT7531 register space (in the context of MT7988
it's all memory-mapped)
With these assumption, we can simplify and permit better usage of PHY OF
automatic probing by binding the mt7531-mdio-mmio driver with the MDIO
node instead of the switch node.
For OF PHY to be correctly autoprobed, the MDIO driver needs to attached
to the MDIO node (the parent of the PHY nodes).
The driver will reach the parent node (the switch node) and will parse
the register address from there.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Instead of having duplicate priv struct for mdio-mt7531-mmio driver in
both driver and header, use the one exposed by the header directly.
This make sure we have consistent priv struct if the driver will be
updated in the future.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:
This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR
instances.
Many files declare DECLARE_GLOBAL_DATA_PTR and include
asm/global_data.h even though gd is never used. In these cases,
asm/global_data.h is effectively treated as a proxy header, which is
not a good practice.
Following the Include What You Use principle, files should include
only the headers they actually depend on, rather than relying on
global_data.h indirectly. This approach is also adopted in Linux kernel
[1].
The first few patches are prepartion to avoid building break after
remove the including of global_data.h.
A script is for filtering the files:
list=`find . -name "*.[ch]"`
for source in ${list}
do
result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}`
if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then
echo "Found in ${source}"
result=`sed -n '/\<gd\>/p' ${source}`
result2=`sed -n '/\<gd_/p' ${source}`
result3=`sed -n '/\<gd->/p' ${source}`
if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then
echo "Cleanup ${source}"
sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source}
sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source}
sed -i '/global_data.h/d' ${source}
git add ${source}
fi
fi
done
[1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf
CI: https://github.com/u-boot/u-boot/pull/865
Link: https://lore.kernel.org/r/20260209-cleanup-v2-0-73a3a84ddbdb@nxp.com
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.
Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <anshuld@ti.com> #TI boards
Acked-by: Yao Zi <me@ziyao.cc> #TH1520
Signed-off-by: Peng Fan <peng.fan@nxp.com>
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
# Conflicts:
# drivers/ddr/altera/Makefile
Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.
Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.
This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129081054.1703479-1-pranav.vinaytilak@amd.com
Pull request net-20260209.
net:
- airoha: mdio support for the switch
- phy: mscc: allow RGMII with internal delay for the VSC8541
- dwc_eth_qos: Update tail pointer handling
net-legacy:
- Stop conflating return value with file size in net_loop()
net-lwip:
- wget: rework the '#' printing
- tftp: add support of tsize option to client
The i.MX91 SoC reuses the ENET FEC from i.MX93. Add all required driver
checks to make it work also on the i.MX91 based platforms.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
uses "airoha,en7581-switch" dts node for finding MDIO childs. This is wrong
for EN7523 SoC. The correct node name should be used instead.
Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add the missing RGMII modes with internal delay for the VSC8541.
Fixes: a5fd13ad1913 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541")
Signed-off-by: Charles Perry <charles.perry@microchip.com>
Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
refers to non-present CONFIG_MDIO_MT7531 and non-present "mt7531-mdio"
driver. It should use CONFIG_MDIO_MT7531_MMIO and "mt7531-mdio-mmio"
instead.
Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
