270 Commits

Author SHA1 Message Date
Varadarajan Narayanan
32825eaddc sysreset: Implement PSCI based reset to EDL mode for QCOM SoCs
Implement request_arg() sysreset_op for QCOM SoCs that use
PSCI to reset to EDL (Emergency Download) mode.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260121063920.1500293-4-varadarajan.narayanan@oss.qualcomm.com
[casey: add missing ARM_SMCCC depends to kconfig to fix CI allyesconfig]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-04-27 12:38:44 +02:00
Dan Carpenter
3a29dfc92e firmware: scmi: Fix setting the function
Set BIT(10) when the function needs to be set, otherwise the setting is
ignored.

Fixes: 0cb160f1b629 ("scmi: pinctrl: add pinctrl driver for SCMI")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-04-09 12:16:58 -06:00
Dan Carpenter
0cb160f1b6 scmi: pinctrl: add pinctrl driver for SCMI
This driver adds the base support of pinctrl over SCMI.  The driver
does two main things.  First, it allows you to configure the initial
pin states.  Secondly, it's used a base to build a GPIO driver on
top of it.

To configure the states then add a pinmux config to the scmi_pinctrl
section:

        scmi_pinctrl: protocol@19 {
                reg = <0x19>;
                pinmux1: pinmux_test {
                        pinmux = <0 1 0xFFFFFFFF 18 1
                                  0 2 0xFFFFFFFF 18 1
                                  0 3 0xFFFFFFFF 18 1>;
                        function = "f_gpio1";
                        groups = "grp_1", "grp_3";
                };
        };

Under linux the pinctrl subsystem will parse the function and group
properties and use that to handle muxing.  However, under u-boot the
pin muxing is done using the "pinmux" property, which feeds raw SCMI
pinctrl PINCTRL_SETTINGS_CONFIGURE commands to the server.  The
numbers are: selector, identifier, function_id, config_type, and
config_value.  In the example above, it sets pins 1, 2, and 3 to 1.
The linux-kernel ignores this pinmux property.

Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-03-23 10:58:20 +08:00
Tom Rini
80bdc86db5 scmi: Rework SCMI_FIRMWARE implementation
As exposed by "make randconfig", how we have SCMI_FIRMWARE today is
incomplete, and in one case, used incorrectly. First, SCMI_FIRMWARE has
a build-time dependency on OF_CONTROL being enabled, so add that.
Second, RESET_SCMI depends on SCMI_FIRMWARE being enabled, it should not
select that symbol. In turn, a number of platforms need to now enable
SCMI_FIRMWARE explicitly and not rely on RESET_SCMI to enable it for
them.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Anshul Dalal <anshuld@ti.com>
Acked-by: Michal Simek <michal.simek@amd.com> # Versal Gen 2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-03-23 10:55:01 +08:00
Tom Rini
1e240f7206 Prepare v2026.04-rc4
-----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQTzzqh0PWDgGS+bTHor4qD1Cr/kCgUCaa8k+wAKCRAr4qD1Cr/k
 Cu3PAP9NGUYzCBO5BOYYJ8nQNIyr2S/mKB25HQ54n+MiILxbTwD+MpTLhNw7Yz3M
 A9aXrmEMzMYeKPFfeP/Zjh4+7VDC7AI=
 =sEOP
 -----END PGP SIGNATURE-----

Merge tag 'v2026.04-rc4' into next

Prepare v2026.04-rc4
2026-03-09 15:26:34 -06:00
Peng Fan
3ee1408eeb firmware: scmi: Validate device tree node before setup channel
SCMI base protocol device does not have a device tree, it should use and
need to use the agent base channel.

For scmi_base.[x], there is no real device tree node for it. ofnode_null() is
assigned as the device tree node for scmi base protocol device:
commit 7eb4eb541c14 ("firmware: scmi: install base protocol to SCMI agent")

However with recent update in commit 0535e46d55d7
("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c"),
SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1
and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF.

So add a check in x_get_channel() to validate the protocol devices'
ofnode.

Reported-by: Ye Li <ye.li@nxp.com>
Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-26 09:04:46 -06:00
Tom Rini
9ddccb5144 Merge patch series "treewide: Clean up usage of DECLARE_GLOBAL_DATA_PTR"
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:

This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR
instances.

Many files declare DECLARE_GLOBAL_DATA_PTR and include
asm/global_data.h even though gd is never used. In these cases,
asm/global_data.h is effectively treated as a proxy header, which is
not a good practice.

Following the Include What You Use principle, files should include
only the headers they actually depend on, rather than relying on
global_data.h indirectly. This approach is also adopted in Linux kernel
[1].

The first few patches are prepartion to avoid building break after
remove the including of global_data.h.

A script is for filtering the files:
list=`find . -name "*.[ch]"`
for source in ${list}
do
        result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}`
        if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then
                echo "Found in ${source}"

                result=`sed -n '/\<gd\>/p' ${source}`
                result2=`sed -n '/\<gd_/p' ${source}`
                result3=`sed -n '/\<gd->/p' ${source}`
                if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then
                        echo "Cleanup ${source}"
                        sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source}
                        sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source}
                        sed -i '/global_data.h/d' ${source}
                        git add ${source}
                fi
        fi
done

[1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf

CI: https://github.com/u-boot/u-boot/pull/865

Link: https://lore.kernel.org/r/20260209-cleanup-v2-0-73a3a84ddbdb@nxp.com
2026-02-17 13:51:26 -06:00
Peng Fan
0f90b1e715 treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <anshuld@ti.com> #TI boards
Acked-by: Yao Zi <me@ziyao.cc> #TH1520
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-17 13:50:22 -06:00
Sean Anderson
df1875ea31 pinctrl: zynqmp: Add SPL support
Although the pinctrl pm requests are implemented in the PMU firmware,
PM_QUERY_DATA is actually implemented in ATF. In SPL (or when running in
EL3), ATF is not yet running, so we need to implement this API
ourselves. Do the bare minimum, allowing SPL to enumerate functions, but
don't bother with groups. Groups take up a lot of space, and can be
emulated with pins. For example, a node like

	display-port {
		mux {
			groups = "dpaux0_1";
			function = "dpaux0";
		};
	};

can be replaced by

	display-port {
		mux {
			pins = "MIO34", "MIO35", "MIO36", "MIO37";
			function = "dpaux0";
		};
	};

While this isn't backwards-compatible with existing devicetrees, it's
more than enough for SPL where we may only need to mux one or two pins.

Add SPL_PINCTRL_ZYNQMP to ensure there's no SPL size growth when pinctrl
is enabled in U-Boot but isn't necessary for SPL. The only config this
would affect is Kria, but SPL_PINCTRL_GENERIC is disabled so
SPL_PINCTRL_ZYNQMP is not selected.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129184011.3932790-1-sean.anderson@linux.dev
2026-02-13 08:16:25 +01:00
Peng Fan
8e918cbe7a firmware: scmi: sandbox: Use scmi_clk_state_in_v2
The sandbox scmi clock protocol use version 3.0, so need to use
scmi_clk_state_in_v2.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-01-28 14:28:01 +08:00
Tom Rini
217cf656e2 dm: core: Default to using DEVRES outside of xPL
The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).

This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-01-09 09:08:14 -06:00
Michal Simek
29427fdf71 arm64: versal2: Read and show multiboot value
SOC can boot from different boot medias and also different offsets that's
why by default show multiboot value to be aware which image system is
booting out of. It is especially useful for systems with A/B update
enabled.
Also limit zynqmp_pm_get_pmc_multi_boot_reg() usage only for Versal and
Versal Gen 2.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fd7564ce2f51d965c273e939e98de01beb92e6f5.1764232124.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
a078ebb86f firmware: xilinx: Add support for enhancement SMC format
Versal Gen 2 is using different SMC format that's why firmware and clock
drivers needs to be align with it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/16bdee56fd75113c6d531bae7a8a34900b10280d.1762788250.git.michal.simek@amd.com
2025-12-19 08:25:26 +01:00
Francois Berder
00e1fed93c firmware: ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource
- Fix temp memory leak
- Free memory during error handling

Signed-off-by: Francois Berder <fberder@outlook.fr>
2025-12-05 16:23:49 -06:00
Vinh Nguyen
0619cb3203 firmware: scmi: Add clock v3.2 CONFIG_SET support
SCMI v3.2 introduces a new clock CONFIG_SET message format that can
optionally carry also OEM specific configuration values beside the usual
clock enable/disable requests. Add support to use such new format when
talking to a v3.2 compliant SCMI platform.

Support existing enable/disable operations across different clock protocol
versions: this patch still does not add protocol operations to support the
new OEM specific optional configuration capabilities.

No functional change for the SCMI drivers users of the related enable and
disable clock operations.

[Marek: Remodel after Linux e49e314a2cf7 ("firmware: arm_scmi: Add clock v3.2 CONFIG_SET support")
        Support both old < 2.1 and new >= 2.1 protocol versions.
	Update commit message based on Linux one]

Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:42 +08:00
Marek Vasut
a5a0134570 firmware: scmi: Drop mmu_set_region_dcache_behaviour() misuse
MMU region cache behavior configuration for SCMI/SMT mailboxes is
platform specific. Even on ARM systems, the mailbox memory may not
even be located in any cacheable MMU region and may instead reside
in some SRAM. Remove this non-generic cache behavior configuration
code from generic code path.

It is unlikely that any platform is affected by this change if it
did configure its MMU regions correctly on start up. Platforms
which might be affected are i.MX94/95 and STM32MP.

Fixes: 240720e9052f ("firmware: scmi: mailbox/smt agent device")
Fixes: 2a3f161c8b16 ("scmi: correctly configure MMU for SCMI buffer")
Fixes: b2ae10970d40 ("firmware: scmi: use PAGE_SIZE alignment for ARM64")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Alice Guo <alice.guo@nxp.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:42 +08:00
Peng Fan
ac9b02dd10 firmware: scmi: Add i.MX95 SCMI CPU Protocol
This protocol allows an agent to start, stop a CPU or set reset vector.
It is used to manage auxiliary CPUs in an LM (e.g. additional cores in an
AP cluster).

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Peng Fan
3f20ea3675 firmware: scmi: Add i.MX95 SCMI LMM protocol driver
Add Logical Machine Management(LMM) protocol which is intended for boot,
shutdown, and reset of other logical machines (LM). It is usually used to
allow one LM to manager another used as an offload or accelerator engine.

Following Linux Kernel, created a separate folder for holding vendor
protocol drivers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Peng Fan
7830ccc77a firmware: scmi: Support probe vendor ID 0x80 and 0x82
Preparing to add i.MX LMM and CPU protocol driver, support probe SCMI
vendor ID 0x80(i.MX SCMI LMM ID) and 0x82(i.MX SCMI CPU ID). And use
Kconfig option to support conditional compilation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Peng Fan
251dd6bf0e firmware: scmi: Conditionally compile protocol support
Add conditional compilation for SCMI protocol support in scmi_get_protocol()
and scmi_add_protocol() based on corresponding Kconfig options. This ensures
that only the enabled protocols are compiled and accessed, and reducing binary
size.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Andrew Goodbody
5b9125746d ti_sci: Pointer is never assigned to valid value
The pointer resp is declared but never assigned a value but is then
dereferenced. Fix this by assigning the pointer to the message buffer.

This issue was found by Smatch.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-10-16 15:02:14 -06:00
Andrew Goodbody
4602fa9220 ti_sci: Provide error code on error exit
In ti_sci_get_response the check for message sequence will return ret
on a fail but ret will be 0 at that point. Instead return -EINVAL.
Also change dev_dbg call to dev_err to be consistent with other error
detection code in the same function.

This issue was found by Smatch.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-10-16 15:02:14 -06:00
Andrew Goodbody
4b8bc5af80 ti_sci: Prevent memory leak
temp is assigned the pointer returned by malloc which is used without a
NULL check and then never freed. Add a NULL check and ensure temp is
freed on all return paths.

This issue was found by Smatch.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-10-16 15:02:14 -06:00
Tom Rini
b1cc9a53d7 AMD/Xilinx/FPGA changes for v2026.01-rc1 v2
zynqmp:
 - DT updates
 - Enable new commands
 
 mbv:
 - Simplify defconfigs
 
 clk:
 - Separate legacy handler and use SMC handler
 
 misc:
 - Tighten TTC Kconfig dependency
 
 net:
 - Add 10GBE support to Gem
 
 pwm:
 - cadence-ttc: Fix array sizes
 
 fwu:
 - Add platform hook support
 
 spi:
 - Remove undocumented cdns,is-dma property
 
 video:
 - Fix DPSUB RGB handling
 -----BEGIN PGP SIGNATURE-----
 
 iHQEABYIAB0WIQSXAixArPbWpRanWW+rB/7wTvUR9QUCaO5Y1wAKCRCrB/7wTvUR
 9TOOAQD21dxtXKgMCRumd391bWvtXTIoUPZ4AVKstviJBolAKAD4p3Nmp0RBFR6L
 4LH+4e5bARtOFDGL5ExCxK57xU5lCg==
 =1Hkr
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2026.01-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx/FPGA changes for v2026.01-rc1 v2

zynqmp:
- DT updates
- Enable new commands

mbv:
- Simplify defconfigs

clk:
- Separate legacy handler and use SMC handler

misc:
- Tighten TTC Kconfig dependency

net:
- Add 10GBE support to Gem

pwm:
- cadence-ttc: Fix array sizes

fwu:
- Add platform hook support

spi:
- Remove undocumented cdns,is-dma property

video:
- Fix DPSUB RGB handling
2025-10-14 09:48:02 -06:00
Peng Fan
5e9fb0e583 firmware: scmi: mailbox: Support arm,max_rx_timeout_ms
Per devicetree bindings:
arm,max-rx-timeout-ms indicates an optional time value, expressed in
milliseconds, representing the transport maximum timeout value for the
receive channel. The value should be a non-zero value if set.

Support this property if platform set it to a non-default value. This
property is a per SCMI property, so all channels share same value.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-10-09 14:16:11 -06:00
Peng Fan
f116ec5b91 firmware: scmi: mailbox: Update timeout to 30ms
Following Linux Kernel drivers/firmware/arm_scmi/transports/mailbox.c to
set the default timeout to 30ms.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
b2ae10970d firmware: scmi: use PAGE_SIZE alignment for ARM64
For ARMv7, the alignment could be SECTION size. But for ARM64, use
PAGE_SIZE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
eb7469eb1a firmware: scmi: Add error code IN_USE
In SCMI spec 3.2, there is an update:
Add IN_USE error code for usage with Pin control protocol

So add the error decoding for IN_USE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
23e2b76922 firmware: scmi: smt: Dump more info
"Buffer too small" is too vague, dump more info to make it easier to
debug issues.
Change dev_dbg to dev_err when buffer is too small.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
8c48bae4f5 firmware: scmi: smt: Use io helpers
It is not good practice to directly use "hdr->x" to read/write the hdr,
because the SCMI buffer may not mapped as normal memory. Following Linux
Kernel, using ioread32/iowrite32/memcpy_[from,to]io for smt header read,
write.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
92fe41caad firmware: scmi: Typo fix
Typo: 'to' -> 'too'

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Naman Trivedi
4146a31dce drivers: firmware: update xilinx_pm_request to support max payload
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Michal Simek
27fa1e2c17 firmware: zynqmp: Simplify power-domain driver bind
CONFIG_IS_ENABLED macro is covering CONFIG_POWER_DOMAIN or
CONFIG_SPL_POWER_DOMAIN Kconfig symbols based on build target which
simplify logic around binding power domain driver.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c75627e92eeaffedf0f7e682edd4f6f39f0b5706.1752826352.git.michal.simek@amd.com
2025-07-24 09:06:52 +02:00
Michal Simek
1b267fe182 firmware: xilinx: Prepare code for new SMC firmware format
Separate code to own function to be able to add new enhancement format.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf99fe1af82bc004de3e313d4018464f4504f380.1750858165.git.michal.simek@amd.com
2025-07-08 14:58:43 +02:00
Tom Rini
237574c181 firmware: xilinx: Tighten dependencies for ZYNQMP_FIRMWARE
The ZYNQMP_FIRMWARE code  cannot build without platform specific headers
being available. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/20250702010410.18828-1-trini@konsulko.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Moteen Shah
60ee945855 firmware: ti_sci.c: Add a function to request DM metadata using ti_sci* calls
Add a function to retrieve information of the DM firmware's ABI versions,
RM/PM HAL, firmware version, etc using TI_SCI protocol.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
e1252194b6 firmware: ti_sci.c: Add a function to query DM firmware's capability
Add a new function to query the capabilities of the DM firmware, using
TI SCI protocol to retrieve a 64-bit firmware capability, where each bit
represents a specific capability supported by the firmware.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
33fc7751b9 ti_sci_* : Add capability to access DM firmware's metadata
Introduce response and request structs to receive and request
information regarding DM version, etc from TI SCI.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
3bc174031d ti_sci_*: Add utility to access tisci firmware and SOC capability
Introduce response and request structs for receiving information
regarding FW/SOC capability from DM. The received capability can
further be used to call certain API's based on the feature supoorted
by the DM firmware.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Udit Kumar
1c26f91a22 firmware: ti_sci: Add Initialization of dev_info head node
On K3 devices two drivers ti_sci and ti_sci_dm are supporting firmware
functions. At run time one of driver is used.

Driver ti_sci already initializing head for dev_list in its probe
function, but it was missed in ti_sci_dm driver.

So add head list init support for ti_sci_dm driver.
While at this, move init of list before usages in both functions.

Fixes: 5d5a699855a7("firmware: ti_sci: Add support for Resoure Management at R5 SPL stage")
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2025-05-05 14:18:59 -06:00
Ye Li
a881951c63 scmi_protocols: update struct scmi_base_discover_list_protocols_out
@protocols is an array of protocol identifiers that are implemented,
excluding the Base protocol. Four protocol identifiers are packed into
each array element. The number of elements of @protocols is specified by
callee-side.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-05-03 16:55:32 -03:00
Alice Guo
ced74d88b2 sandbox: add SCMI clock control permissions to sandbox
This patch is used to add SCMI clock control permissions to sandbox for
testing.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-05-03 16:55:32 -03:00
Alice Guo
bf2ea4fde7 firmware: scmi_agent: add SCMI pin control protocol support
This patch adds SCMI pin control protocol support to make the pin
controller driver based on SCMI, such as
drivers/pinctrl/nxp/pinctrl-imx-scmi.c, can be bound to the SCMI agent
device whose protocol id is 0x19.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-05-03 16:55:32 -03:00
Alice Guo
adff089cd4 firmware: scmi: use scmi_proto_driver_get() function to get SCMI protocol driver
If there is a SoC specific SCMI protocol driver, using
scmi_proto_driver_get() function can avoid to add SoC specific code to
scmi_agent-uclass.c.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-05-03 16:55:32 -03:00
Alice Guo
b4f3fab643 firmware: scmi: support to manage SCMI protocol drivers with a linker-genetated array
U_BOOT_SCMI_PROTO_DRIVER macro is used to add a SCMI protocol driver to
scmi_proto_driver list. scmi_proto_driver_get() function can be used to
match a SCMI protocol id and its driver.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-05-03 16:55:32 -03:00
Miquel Raynal
9086b64ca0 power-domain: Add support for refcounting (again)
It is very surprising that such an uclass, specifically designed to
handle resources that may be shared by different devices, is not keeping
the count of the number of times a power domain has been
enabled/disabled to avoid shutting it down unexpectedly or disabling it
several times.

Doing this causes troubles on eg. i.MX8MP because disabling power
domains can be done in recursive loops were the same power domain
disabled up to 4 times in a row. PGCs seem to have tight FSM internal
timings to respect and it is easy to produce a race condition that puts
the power domains in an unstable state, leading to ADB400 errors and
later crashes in Linux.

Some drivers implement their own mechanism for that, but it is probably
best to add this feature in the uclass and share the common code across
drivers. In order to avoid breaking existing drivers, refcounting is
only enabled if the number of subdomains a device node supports is
explicitly set in the probe function. ->xlate() callbacks will return
the power domain ID which is then being used as the array index to reach
the correct refcounter.

As we do not want to break existing users while stile getting
interesting error codes, the implementation is split between:
- a low-level helper reporting error codes if the requested transition
  could not be operated,
- a higher-level helper ignoring the "non error" codes, like EALREADY and
  EBUSY.

CI tests using power domains are slightly updated to make sure the count
of on/off calls is even and the results match what we *now* expect. They
are also extended to test the low-level functions.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-04-28 10:41:19 -03:00
Marek Vasut
2a8e7ea4f9 power: regulator: scmi: Move regulator subnode hack to scmi_regulator
The current code attempts to bind scmi_voltage_domain to regulator subnode
of the SCMI protocol node, so scmi_voltage_domain can then bind regulators
directly to subnodes of its node. This kind of behavior should not be in
core code, move it into scmi_voltage_domain driver code. Let the driver
descend into regulator node and bind regulators to its subnodes.

Fixes: 1f213ee4dbf2 ("firmware: scmi: voltage regulator")
Signed-off-by: Marek Vasut <marex@denx.de>
[Alice Guo: Fix scmi_regulator_bind]
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-23 11:28:12 +08:00
Wadim Egorov
71f497a6d3 Revert "power-domain: Add refcounting"
Unfortunately this change breaks boot on K3 platform.
U-Boot will hang after:

  U-Boot SPL 2025.04-01050-ga40fc5afaec0 (Apr 14 2025 - 07:31:32 +0000)
  SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.7--v09.02.07 (Kool Koala)')

This reverts commit 197376fbf300e92afa0a1583815d9c9eb52d613a as
suggested in [1].

[1] https://lists.denx.de/pipermail/u-boot/2025-April/587032.html

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-04-18 09:35:39 -06:00
Venkatesh Yadav Abbarapu
5b8d6dcf7c ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers
Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com
2025-04-16 13:42:06 +02:00
Prasad Kummari
5ffab6ee12 xilinx: versal: add firmware access to PMC multi Boot mode register
Added extended support for retrieving the PMC muti boot mode
register via the firmware interface, which is preferred when
U-Boot runs in EL2 and cannot directly access PMC registers
via raw reads. Ideally, all secure registers should be accessed
via xilinx_pm_request(). Introduced the secure
zynqmp_pm_get_pmc_multi_boot_reg() call, which uses
xilinx_pm_request() to read the PMC multi boot mode register.

BootROM increments the MultiBoot register (PMC_MULTI_BOOT) read
address offset by 32 KB and retries. For SD and eMMC boot modes,
it can search up to 8191 FAT files for the identification string.
A 13-bit mask (0x1FFF) is applied to PMC_MULTI_BOOT_MASK to obtain
the correct values in BootROM.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20250305134845.3182193-1-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-04-16 13:42:06 +02:00