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riscv: andesv5: Set default cache line size to 64-bytes

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The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Yu Chien Peter Lin 2024-04-11 17:29:45 +08:00 committed by Leo Yu-Chi Liang
parent ff0de1f055
commit fd55792e14
1 changed files with 1 additions and 0 deletions
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arch/riscv/cpu/andesv5/Kconfig
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@ -1,6 +1,7 @@
config RISCV_NDS config RISCV_NDS
bool bool
select ARCH_EARLY_INIT_R select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
imply CPU imply CPU
imply CPU_RISCV imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)