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Prepare v2025.10-rc3

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Merge tag 'v2025.10-rc3' into next

Prepare v2025.10-rc3
This commit is contained in:
Tom Rini 2025-08-25 13:28:49 -06:00
commit fceb37d802
195 changed files with 1967 additions and 6326 deletions
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2
Makefile
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@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*

5
arch/arm/dts/Makefile
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@ -648,11 +648,6 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-oka40i-c.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-pinecube.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN8I_R528) += \
sun8i-t113s-mangopi-mq-r-t113.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \

16
arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi
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@ -7,6 +7,13 @@
#include "r8a779g0-u-boot.dtsi"
&avb0_pins {
pins-vddq18-25-avb {
pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0";
power-source = <1800>;
};
};
/* Page 31 / FAN */
&gpio1 {
pwm-fan-hog {
@ -44,7 +51,16 @@
&rpc {
flash@0 {
/*
* EVTA1 is populated with Spansion S25FS512S
* EVTB1 is populated with Winbond W77Q51NW
*/
compatible = "jedec,spi-nor";
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&vcc_sdhi {
states = <1800000 0>, <3300000 1>;
};

44
arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
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@ -1,44 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
*/
/dts-v1/;
#include "sun8i-v3.dtsi"
#include "sunxi-common-regulators.dtsi"
/ {
model = "Elimo Impetus SoM";
compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&mmc0 {
broken-cd;
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};

29
arch/arm/dts/sun8i-s3-elimo-initium.dts
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@ -1,29 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
*/
/dts-v1/;
#include "sun8i-s3-elimo-impetus.dtsi"
/ {
model = "Elimo Initium";
compatible = "elimo,initium", "elimo,impetus", "sochip,s3",
"allwinner,sun8i-v3";
aliases {
serial1 = &uart1;
};
};
&uart1 {
pinctrl-0 = <&uart1_pg_pins>;
pinctrl-names = "default";
status = "okay";
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
status = "okay";
};

53
arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
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@ -1,53 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
*/
/dts-v1/;
#include "sun8i-v3.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Sipeed Lichee Zero Plus";
compatible = "sipeed,lichee-zero-plus", "sochip,s3",
"allwinner,sun8i-v3";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
broken-cd;
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};

228
arch/arm/dts/sun8i-s3-pinecube.dts
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@ -1,228 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright 2019 Icenowy Zheng <icenowy@aosc.io>
*/
/dts-v1/;
#include "sun8i-v3.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "PineCube IP Camera";
compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
aliases {
serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led1 {
label = "pine64:ir:led1";
gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
};
led2 {
label = "pine64:ir:led2";
gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */
};
};
reg_vcc5v0: vcc5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_vcc_wifi: vcc-wifi {
compatible = "regulator-fixed";
regulator-name = "vcc-wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */
vin-supply = <&reg_dcdc3>;
startup-delay-us = <200000>;
};
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */
post-power-on-delay-ms = <200>;
};
};
&csi1 {
pinctrl-names = "default";
pinctrl-0 = <&csi1_8bit_pins>;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
bus-width = <8>;
hsync-active = <1>; /* Active high */
vsync-active = <0>; /* Active low */
data-active = <1>; /* Active high */
pclk-sample = <1>; /* Rising */
};
};
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pe_pins>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&csi1_mclk_pin>;
clocks = <&ccu CLK_CSI1_MCLK>;
clock-names = "xclk";
AVDD-supply = <&reg_ldo3>;
DOVDD-supply = <&reg_ldo3>;
DVDD-supply = <&reg_ldo4>;
reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */
powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi1_ep>;
bus-width = <8>;
hsync-active = <1>; /* Active high */
vsync-active = <0>; /* Active low */
data-active = <1>; /* Active high */
pclk-sample = <1>; /* Rising */
};
};
};
};
&lradc {
vref-supply = <&reg_ldo2>;
status = "okay";
button-200 {
label = "Setup";
linux,code = <KEY_SETUP>;
channel = <0>;
voltage = <190000>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdc3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_vcc_wifi>;
vqmmc-supply = <&reg_dcdc3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&pio {
vcc-pd-supply = <&reg_dcdc3>;
vcc-pe-supply = <&reg_ldo3>;
};
#include "axp209.dtsi"
&ac_power_supply {
status = "okay";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd-sys-cpu-ephy";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_ldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "avdd-dovdd-2v8-csi";
regulator-soft-start;
regulator-ramp-delay = <1600>;
};
&reg_ldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-1v8-csi";
};
&spi0 {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart2 {
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usbphy {
usb0_vbus-supply = <&reg_vcc5v0>;
status = "okay";
};

12
arch/arm/dts/sun8i-v3-sl631-imx179.dts
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@ -1,12 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
*/
#include "sun8i-v3-sl631.dtsi"
/ {
model = "SL631 Action Camera with IMX179";
compatible = "allwinner,sl631-imx179", "allwinner,sl631",
"allwinner,sun8i-v3";
};

138
arch/arm/dts/sun8i-v3-sl631.dtsi
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@ -1,138 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
*/
/dts-v1/;
#include "sun8i-v3.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "SL631 Action Camera";
compatible = "allwinner,sl631", "allwinner,sun8i-v3";
aliases {
serial0 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&i2c0 {
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pb_pins>;
status = "okay";
};
&lradc {
vref-supply = <&reg_ldo2>;
status = "okay";
button-174 {
label = "Down";
linux,code = <KEY_DOWN>;
channel = <0>;
voltage = <174603>;
};
button-384 {
label = "Up";
linux,code = <KEY_UP>;
channel = <0>;
voltage = <384126>;
};
button-593 {
label = "OK";
linux,code = <KEY_OK>;
channel = <0>;
voltage = <593650>;
};
};
&mmc0 {
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
vmmc-supply = <&reg_dcdc3>;
status = "okay";
};
&pio {
vcc-pd-supply = <&reg_dcdc3>;
vcc-pe-supply = <&reg_dcdc3>;
};
#include "axp209.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd-sys-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vdd-3v3";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&spi0 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
};
};
&uart1 {
pinctrl-0 = <&uart1_pg_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
status = "okay";
};

63
arch/arm/dts/sun8i-v3.dtsi
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@ -1,63 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
* Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*/
#include "sun8i-v3s.dtsi"
/ {
soc {
i2s0: i2s@1c22000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-v3-i2s",
"allwinner,sun8i-h3-i2s";
reg = <0x01c22000 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
clock-names = "apb", "mod";
dmas = <&dma 3>, <&dma 3>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_pins>;
resets = <&ccu RST_BUS_I2S0>;
status = "disabled";
};
};
};
&ccu {
compatible = "allwinner,sun8i-v3-ccu";
};
&codec_analog {
compatible = "allwinner,sun8i-v3-codec-analog",
"allwinner,sun8i-h3-codec-analog";
};
&emac {
/delete-property/ phy-handle;
/delete-property/ phy-mode;
};
&mdio_mux {
external_mdio: mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
};
&pio {
compatible = "allwinner,sun8i-v3-pinctrl";
i2s0_pins: i2s0-pins {
pins = "PG10", "PG11", "PG12", "PG13";
function = "i2s";
};
uart1_pg_pins: uart1-pg-pins {
pins = "PG6", "PG7";
function = "uart1";
};
};

276
arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts
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@ -1,276 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include "sun8i-v3s.dtsi"
#include "sunxi-common-regulators.dtsi"
/ {
model = "Anbernic RG Nano";
compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s";
aliases {
rtc0 = &pcf8563;
rtc1 = &rtc;
serial0 = &uart0;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>;
default-brightness-level = <11>;
power-supply = <&reg_vcc5v0>;
pwms = <&pwm 0 40000 1>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
button-a {
gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-A";
linux,code = <BTN_EAST>;
};
button-b {
gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-B";
linux,code = <BTN_SOUTH>;
};
button-down {
gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-DOWN";
linux,code = <BTN_DPAD_DOWN>;
};
button-left {
gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-LEFT";
linux,code = <BTN_DPAD_LEFT>;
};
button-right {
gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-RIGHT";
linux,code = <BTN_DPAD_RIGHT>;
};
button-se {
gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-SELECT";
linux,code = <BTN_SELECT>;
};
button-st {
gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-START";
linux,code = <BTN_START>;
};
button-tl {
gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-L";
linux,code = <BTN_TL>;
};
button-tr {
gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-R";
linux,code = <BTN_TR>;
};
button-up {
gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-UP";
linux,code = <BTN_DPAD_UP>;
};
button-x {
gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-X";
linux,code = <BTN_NORTH>;
};
button-y {
gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-Y";
linux,code = <BTN_WEST>;
};
};
};
&codec {
allwinner,audio-routing = "Speaker", "HP",
"MIC1", "Mic",
"Mic", "HBIAS";
allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */
status = "okay";
};
&ehci {
status = "okay";
};
&i2c0 {
status = "okay";
gpio_expander: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */
vcc-supply = <&reg_vcc3v3>;
};
axp209: pmic@34 {
reg = <0x34>;
interrupt-parent = <&pio>;
interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */
};
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
#include "axp209.dtsi"
&battery_power_supply {
status = "okay";
};
&mmc0 {
broken-cd;
bus-width = <4>;
disable-wp;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&ohci {
status = "okay";
};
&pio {
vcc-pb-supply = <&reg_vcc3v3>;
vcc-pc-supply = <&reg_vcc3v3>;
vcc-pf-supply = <&reg_vcc3v3>;
vcc-pg-supply = <&reg_vcc3v3>;
spi0_no_miso_pins: spi0-no-miso-pins {
pins = "PC1", "PC2", "PC3";
function = "spi0";
};
};
&pwm {
pinctrl-0 = <&pwm0_pin>;
pinctrl-names = "default";
status = "okay";
};
/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */
&reg_dcdc2 {
regulator-always-on;
regulator-max-microvolt = <1250000>;
regulator-min-microvolt = <1250000>;
regulator-name = "vdd-cpu";
};
/* DCDC3 wired into every 3.3v input that isn't the RTC. */
&reg_dcdc3 {
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "vcc-io";
};
/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */
&reg_ldo1 {
regulator-always-on;
regulator-name = "vcc-rtc";
};
/* LDO2 wired into VCC-PLL and audio codec. */
&reg_ldo2 {
regulator-always-on;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <3000000>;
regulator-name = "vcc-pll";
};
/* LDO3, LDO4, and LDO5 unused. */
&reg_ldo3 {
status = "disabled";
};
&reg_ldo4 {
status = "disabled";
};
/* RTC uses internal oscillator */
&rtc {
/delete-property/ clocks;
};
&spi0 {
pinctrl-0 = <&spi0_no_miso_pins>;
pinctrl-names = "default";
status = "okay";
display@0 {
compatible = "saef,sftc154b", "panel-mipi-dbi-spi";
reg = <0>;
backlight = <&backlight>;
dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */
reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
spi-max-frequency = <100000000>;
height-mm = <39>;
width-mm = <39>;
/* Set hb-porch to compensate for non-visible area */
panel-timing {
hactive = <240>;
vactive = <240>;
hback-porch = <80>;
vback-porch = <0>;
clock-frequency = <0>;
hfront-porch = <0>;
hsync-len = <0>;
vfront-porch = <0>;
vsync-len = <0>;
};
};
};
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usb_power_supply {
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */
status = "okay";
};

105
arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
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@ -1,105 +0,0 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sun8i-v3s-licheepi-zero.dts"
#include <dt-bindings/input/input.h>
/ {
model = "Lichee Pi Zero with Dock";
compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
"allwinner,sun8i-v3s";
aliases {
ethernet0 = &emac;
};
leds {
/* The LEDs use PG0~2 pins, which conflict with MMC1 */
status = "disabled";
};
};
&emac {
allwinner,leds-active-low;
status = "okay";
};
&lradc {
vref-supply = <&reg_vcc3v0>;
status = "okay";
button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <400000>;
};
button-600 {
label = "Select";
linux,code = <KEY_SELECT>;
channel = <0>;
voltage = <600000>;
};
button-800 {
label = "Start";
linux,code = <KEY_OK>;
channel = <0>;
voltage = <800000>;
};
};
&mmc1 {
broken-cd;
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};

101
arch/arm/dts/sun8i-v3s-licheepi-zero.dts
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@ -1,101 +0,0 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-v3s.dtsi"
#include "sunxi-common-regulators.dtsi"
/ {
model = "Lichee Pi Zero";
compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
blue_led {
label = "licheepi:blue:usr";
gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
};
green_led {
label = "licheepi:green:usr";
gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
default-state = "on";
};
red_led {
label = "licheepi:red:usr";
gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
};
};
};
&mmc0 {
broken-cd;
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};

656
arch/arm/dts/sun8i-v3s.dtsi
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@ -1,656 +0,0 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
* Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
framebuffer-lcd {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "mixer0-lcd0";
clocks = <&display_clocks CLK_MIXER0>,
<&ccu CLK_TCON0>;
status = "disabled";
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clocks = <&ccu CLK_CPU>;
};
};
de: display-engine {
compatible = "allwinner,sun8i-v3s-display-engine";
allwinner,pipelines = <&mixer0>;
status = "disabled";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc24M: osc24M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-accuracy = <50000>;
clock-output-names = "osc24M";
};
osc32k: osc32k-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-accuracy = <50000>;
clock-output-names = "ext-osc32k";
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-v3s-de2-clk";
reg = <0x01000000 0x10000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@1100000 {
compatible = "allwinner,sun8i-v3s-de2-mixer";
reg = <0x01100000 0x100000>;
clocks = <&display_clocks 0>,
<&display_clocks 6>;
clock-names = "bus",
"mod";
resets = <&display_clocks 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_mixer0>;
};
};
};
};
syscon: system-control@1c00000 {
compatible = "allwinner,sun8i-v3s-system-control",
"allwinner,sun8i-h3-system-control";
reg = <0x01c00000 0xd0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
nmi_intc: interrupt-controller@1c000d0 {
compatible = "allwinner,sun8i-v3s-nmi",
"allwinner,sun9i-a80-nmi";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x01c000d0 0x0c>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-v3s-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <1>;
};
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-v3s-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>,
<&ccu CLK_TCON0>;
clock-names = "ahb",
"tcon-ch0";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
reg = <0>;
tcon0_in_mixer0: endpoint {
remote-endpoint = <&mixer0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>,
<&ccu CLK_MMC0>,
<&ccu CLK_MMC0_OUTPUT>,
<&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@1c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>,
<&ccu CLK_MMC1>,
<&ccu CLK_MMC1_OUTPUT>,
<&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@1c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>,
<&ccu CLK_MMC2>,
<&ccu CLK_MMC2_OUTPUT>,
<&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
crypto@1c15000 {
compatible = "allwinner,sun8i-v3s-crypto",
"allwinner,sun8i-a33-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
clock-names = "ahb", "mod";
dmas = <&dma 16>, <&dma 16>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_CE>;
reset-names = "ahb";
};
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@1c19400 {
compatible = "allwinner,sun8i-v3s-usb-phy";
reg = <0x01c19400 0x2c>,
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu0";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci: usb@1c1a000 {
compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ohci: usb@1c1a400 {
compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@1c20400 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-v3-rtc";
reg = <0x01c20400 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc32k>;
clock-output-names = "osc32k", "osc32k-out";
};
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-v3s-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
/omit-if-no-ref/
csi0_mclk_pin: csi0-mclk-pin {
pins = "PE20";
function = "csi_mipi";
};
/omit-if-no-ref/
csi1_8bit_pins: csi1-8bit-pins {
pins = "PE0", "PE2", "PE3", "PE8", "PE9",
"PE10", "PE11", "PE12", "PE13", "PE14",
"PE15";
function = "csi";
};
/omit-if-no-ref/
csi1_mclk_pin: csi1-mclk-pin {
pins = "PE1";
function = "csi";
};
i2c0_pins: i2c0-pins {
pins = "PB6", "PB7";
function = "i2c0";
};
/omit-if-no-ref/
i2c1_pb_pins: i2c1-pb-pins {
pins = "PB8", "PB9";
function = "i2c1";
};
/omit-if-no-ref/
i2c1_pe_pins: i2c1-pe-pins {
pins = "PE21", "PE22";
function = "i2c1";
};
uart0_pb_pins: uart0-pb-pins {
pins = "PB8", "PB9";
function = "uart0";
};
uart2_pins: uart2-pins {
pins = "PB0", "PB1";
function = "uart2";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
bias-pull-up;
};
/omit-if-no-ref/
pwm0_pin: pwm0-pin {
pins = "PB4";
function = "pwm0";
};
/omit-if-no-ref/
pwm1_pin: pwm1-pin {
pins = "PB5";
function = "pwm1";
};
spi0_pins: spi0-pins {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
};
};
timer@1c20c00 {
compatible = "allwinner,sun8i-v3s-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
pwm: pwm@1c21400 {
compatible = "allwinner,sun8i-v3s-pwm",
"allwinner,sun7i-a20-pwm";
reg = <0x01c21400 0xc>;
clocks = <&osc24M>;
#pwm-cells = <3>;
status = "disabled";
};
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x400>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-v3s-codec";
reg = <0x01c22c00 0x400>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
clock-names = "apb", "codec";
resets = <&ccu RST_BUS_CODEC>;
dmas = <&dma 15>, <&dma 15>;
dma-names = "rx", "tx";
allwinner,codec-analog-controls = <&codec_analog>;
status = "disabled";
};
codec_analog: codec-analog@1c23000 {
compatible = "allwinner,sun8i-v3s-codec-analog";
reg = <0x01c23000 0x4>;
};
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART2>;
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "disabled";
};
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-v3s-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
mdio_mux: mdio-mux {
compatible = "allwinner,sun8i-h3-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
/* Only one MDIO is usable at the time */
internal_mdio: mdio@1 {
compatible = "allwinner,sun8i-h3-mdio-internal";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
};
};
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI_SCLK>,
<&ccu CLK_DRAM_CSI>;
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
};
};
};

5
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
View File

@ -20,6 +20,11 @@
"xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
model = "ZynqMP KR260 revB";
aliases {
ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */
ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;

13
arch/arm/mach-imx/imx9/scmi/soc.c
View File

@ -635,7 +635,8 @@ enum env_location env_get_location(enum env_operation op, int prio)
switch (dev) {
case QSPI_BOOT:
env_loc = ENVL_SPI_FLASH;
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
env_loc = ENVL_SPI_FLASH;
break;
case SD1_BOOT:
case SD2_BOOT:
@ -643,10 +644,16 @@ enum env_location env_get_location(enum env_operation op, int prio)
case MMC1_BOOT:
case MMC2_BOOT:
case MMC3_BOOT:
env_loc = ENVL_MMC;
if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
env_loc = ENVL_MMC;
break;
default:
env_loc = ENVL_NOWHERE;
if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
env_loc = ENVL_NOWHERE;
else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
env_loc = ENVL_SPI_FLASH;
else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
env_loc = ENVL_MMC;
break;
}

8
arch/arm/mach-imx/imx9/soc.c
View File

@ -809,7 +809,13 @@ enum env_location env_get_location(enum env_operation op, int prio)
return ENVL_FAT;
return ENVL_NOWHERE;
default:
return ENVL_NOWHERE;
if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
return ENVL_NOWHERE;
else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
return ENVL_MMC;
return ENVL_UNKNOWN;
}
}

13
arch/arm/mach-snapdragon/board.c
View File

@ -534,8 +534,7 @@ int board_late_init(void)
env_set_hex("ramdisk_addr_r", addr) : 1;
status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ?
env_set_hex("kernel_comp_addr_r", addr) : 1;
status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ?
env_set_hex("kernel_comp_size", addr) : 1;
status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
status |= !lmb_alloc(SZ_4M, &addr) ?
env_set_hex("scriptaddr", addr) : 1;
status |= !lmb_alloc(SZ_4M, &addr) ?
@ -544,9 +543,13 @@ int board_late_init(void)
if (IS_ENABLED(CONFIG_FASTBOOT)) {
status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ?
env_set_hex("fastboot_addr_r", addr) : 1;
/* override loadaddr for memory rich soc */
status |= !lmb_alloc(SZ_128M, &addr) ?
env_set_hex("loadaddr", addr) : 1;
/*
* Override loadaddr for memory rich soc since ${loadaddr} and
* ${kernel_addr_r} need to be different for the Android boot image
* flow. It's typically safe for ${loadaddr} to be the same address
* as the fastboot buffer.
*/
status |= env_set_hex("loadaddr", addr);
}
fdt_status |= !lmb_alloc(SZ_2M, &addr) ?

3
arch/arm/mach-sunxi/Kconfig
View File

@ -487,6 +487,7 @@ config MACH_SUN8I_V3S
select SUNXI_DRAM_DW_16BIT
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply OF_UPSTREAM
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
@ -718,9 +719,9 @@ config DRAM_CLK
int "sunxi dram clock speed"
default 792 if MACH_SUN9I
default 648 if MACH_SUN8I_R40
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
MACH_SUN8I_V3S
default 312 if MACH_SUN6I || MACH_SUN8I
default 672 if MACH_SUN50I
default 744 if MACH_SUN50I_H6
default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133

2
arch/arm/mach-sunxi/board.c
View File

@ -476,8 +476,8 @@ void board_init_f(ulong dummy)
/* Enable non-secure access to some peripherals */
tzpc_init();
clock_init();
timer_init();
clock_init();
gpio_init();
spl_init();

2
arch/arm/mach-sunxi/dram_sun50i_a133.c
View File

@ -416,7 +416,7 @@ static void mctl_com_init(const struct dram_para *para,
static void mctl_drive_odt_config(const struct dram_para *para)
{
u32 val;
u64 base;
ulong base;
u32 i;
/* DX drive */

12
arch/arm/mach-sunxi/dram_sun50i_h616.c
View File

@ -1078,18 +1078,18 @@ static bool mctl_phy_init(const struct dram_para *para,
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
break;
case SUNXI_DRAM_TYPE_LPDDR3:
writel(mr0, &mctl_ctl->mrctrl1);
/* MR0 is read-only */
/* MR1: nWR=14, BL8 */
writel(0x183, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(4, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(mr2, &mctl_ctl->mrctrl1);
/* MR2: no WR leveling, WL set A, use nWR>9, nRL=14/nWL=8 */
writel(0x21c, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
/* MR3: 34.3 Ohm pull-up/pull-down resistor */
writel(0x301, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);

4
arch/riscv/Kconfig
View File

@ -11,6 +11,9 @@ choice
config TARGET_ANDES_AE350
bool "Support Andes ae350"
config TARGET_ANDES_VOYAGER
bool "Support Andes Voyager Board"
config TARGET_BANANAPI_F3
bool "Support BananaPi F3 Board"
@ -101,6 +104,7 @@ config SPL_ZERO_MEM_BEFORE_USE
# board-specific options below
source "board/andestech/ae350/Kconfig"
source "board/andestech/voyager/Kconfig"
source "board/aspeed/ibex_ast2700/Kconfig"
source "board/canaan/k230_canmv/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"

14
arch/riscv/cpu/cpu.c
View File

@ -608,14 +608,14 @@ static inline bool supports_extension(char ext)
static int riscv_cpu_probe(void)
{
#ifdef CONFIG_CPU
int ret;
if (CONFIG_IS_ENABLED(CPU)) {
int ret;
/* probe cpus so that RISC-V timer can be bound */
ret = cpu_probe_all();
if (ret)
return log_msg_ret("RISC-V cpus probe failed\n", ret);
#endif
/* probe cpus so that RISC-V timer can be bound */
ret = cpu_probe_all();
if (ret)
return log_msg_ret("RISC-V cpus probe failed\n", ret);
}
return 0;
}

2
arch/riscv/dts/Makefile
View File

@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb
dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb
dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
@ -14,6 +15,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
include $(srctree)/scripts/Makefile.dts

227
arch/riscv/dts/qilai-voyager.dts Normal file
View File

@ -0,0 +1,227 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "binman.dtsi"
#include "voyager-u-boot.dtsi"
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "andestech,voyager", "andestech,qilai";
model = "Voyager";
aliases {
uart0 = &serial0;
spi0 = &spi;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlycon=sbi debug loglevel=7";
stdout-path = "uart0:115200n8";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
timebase-frequency = <0x3938700>;
CPU0: cpu@0 {
device_type = "cpu";
reg = <0x0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdc";
riscv,priv-major = <0x1>;
riscv,priv-minor = <0xa>;
mmu-type = "riscv,sv39";
clock-frequency = <0x3938700>;
i-cache-size = <0x8000>;
i-cache-line-size = <0x20>;
d-cache-size = <0x8000>;
d-cache-line-size = <0x20>;
next-level-cache = <&L2>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <0x1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU1: cpu@1 {
device_type = "cpu";
reg = <0x1>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdc";
riscv,priv-major = <0x1>;
riscv,priv-minor = <0xa>;
mmu-type = "riscv,sv39";
clock-frequency = <0x3938700>;
i-cache-size = <0x8000>;
i-cache-line-size = <0x20>;
d-cache-size = <0x8000>;
d-cache-line-size = <0x20>;
next-level-cache = <&L2>;
CPU1_intc: interrupt-controller {
#interrupt-cells = <0x1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU2: cpu@2 {
device_type = "cpu";
reg = <0x2>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdc";
riscv,priv-major = <0x1>;
riscv,priv-minor = <0xa>;
mmu-type = "riscv,sv39";
clock-frequency = <0x3938700>;
i-cache-size = <0x8000>;
i-cache-line-size = <0x20>;
d-cache-size = <0x8000>;
d-cache-line-size = <0x20>;
next-level-cache = <&L2>;
CPU2_intc: interrupt-controller {
#interrupt-cells = <0x1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU3: cpu@3 {
device_type = "cpu";
reg = <0x3>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdc";
riscv,priv-major = <0x1>;
riscv,priv-minor = <0xa>;
mmu-type = "riscv,sv39";
clock-frequency = <0x3938700>;
i-cache-size = <0x8000>;
i-cache-line-size = <0x20>;
d-cache-size = <0x8000>;
d-cache-line-size = <0x20>;
next-level-cache = <&L2>;
CPU3_intc: interrupt-controller {
#interrupt-cells = <0x1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
L2: l2-cache@200000 {
compatible = "cache";
cache-level = <0x2>;
cache-size = <0x40000>;
reg = <0x0 0x00200000 0x0 0x100000>;
andes,inst-prefetch = <0x3>;
andes,data-prefetch = <0x3>;
andes,tag-ram-ctl = <0x0 0x0>;
andes,data-ram-ctl = <0x0 0x0>;
};
memory@400000000 {
device_type = "memory";
reg = <0x04 0x00000000 0x0 0x40000000>;
};
soc {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "simple-bus";
ranges;
plic0: interrupt-controller@2000000 {
compatible = "riscv,plic0";
#address-cells = <0x2>;
#interrupt-cells = <0x2>;
interrupt-controller;
reg = <0x0 0x02000000 0x0 0x2000000>;
riscv,ndev = <0x47>;
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
&CPU1_intc 11 &CPU1_intc 9
&CPU2_intc 11 &CPU2_intc 9
&CPU3_intc 11 &CPU3_intc 9>;
};
plic1: interrupt-controller@400000 {
compatible = "andestech,plicsw";
#address-cells = <0x2>;
#interrupt-cells = <0x2>;
interrupt-controller;
reg = <0x0 0x00400000 0x0 0x400000>;
riscv,ndev = <0x1>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
};
plmt0@100000 {
compatible = "andestech,plmt0";
reg = <0x0 0x00100000 0x0 0x100000>;
interrupts-extended = <&CPU0_intc 7
&CPU1_intc 7
&CPU2_intc 7
&CPU3_intc 7>;
};
};
spiclk: virt_100mhz {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x5f5e100>;
};
serial0: serial@30300000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x0 0x30300000 0x0 0x1000>;
interrupts = <0x9 0x4>;
clock-frequency = <0x12c0000>;
reg-shift = <0x2>;
reg-offset = <0x20>;
no-loopback-test = <0x1>;
interrupt-parent = <&plic0>;
};
mmc0: mmc@30c00000 {
compatible = "andestech,atfsdc010";
max-frequency = <0x5f5e100>;
clock-freq-min-max = <0x61a80 0x5f5e100>;
fifo-depth = <0x10>;
reg = <0x0 0x30c00000 0x0 0x1000>;
interrupts = <0x12 0x4>;
cap-sd-highspeed;
interrupt-parent = <&plic0>;
dma-coherent;
};
spi: spi@30900000 {
compatible = "andestech,atcspi200";
reg = <0x0 0x30900000 0x0 0x100000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
num-cs = <0x1>;
clocks = <&spiclk>;
interrupts = <0x4 0x4>;
interrupt-parent = <&plic0>;
flash@0 {
compatible = "mx25u1635e", "jedec,spi-nor";
spi-max-frequency = <0x2faf080>;
reg = <0x0>;
spi-cpol;
spi-cpha;
};
};
};

52
arch/riscv/dts/voyager-u-boot.dtsi Normal file
View File

@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/ {
cpus {
bootph-pre-ram;
CPU0: cpu@0 {
bootph-pre-ram;
CPU0_intc: interrupt-controller {
bootph-pre-ram;
};
};
CPU1: cpu@1 {
bootph-pre-ram;
CPU1_intc: interrupt-controller {
bootph-pre-ram;
};
};
CPU2: cpu@2 {
bootph-pre-ram;
CPU2_intc: interrupt-controller {
bootph-pre-ram;
};
};
CPU3: cpu@3 {
bootph-pre-ram;
CPU3_intc: interrupt-controller {
bootph-pre-ram;
};
};
};
memory@0 {
bootph-pre-ram;
};
soc {
bootph-pre-ram;
plic1: interrupt-controller@400000 {
bootph-pre-ram;
};
plmt0@100000 {
bootph-pre-ram;
};
};
serial0: serial@30300000 {
bootph-pre-ram;
};
};

12
arch/riscv/dts/xilinx-binman.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* binman file for AMD MicroBlaze V
*
* (C) Copyright 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "binman.dtsi"

8
arch/riscv/dts/xilinx-mbv32.dts
View File

@ -2,15 +2,13 @@
/*
* dts file for AMD MicroBlaze V
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "binman.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
@ -26,6 +24,7 @@
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imafdc";
mmu-type = "riscv,sv39";
i-cache-size = <32768>;
d-cache-size = <32768>;
clock-frequency = <100000000>;
@ -70,7 +69,8 @@
interrupt-controller;
interrupt-parent = <&cpu0_intc>;
#interrupt-cells = <2>;
kind-of-intr = <0>;
xlnx,num-intr-inputs = <2>;
xlnx,kind-of-intr = <0>;
};
xlnx_timer0: timer@41c00000 {

8
arch/riscv/dts/xilinx-mbv64.dts
View File

@ -2,15 +2,13 @@
/*
* dts file for AMD MicroBlaze V
*
* (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
* (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "binman.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
@ -26,6 +24,7 @@
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
i-cache-size = <32768>;
d-cache-size = <32768>;
clock-frequency = <100000000>;
@ -70,7 +69,8 @@
interrupt-controller;
interrupt-parent = <&cpu0_intc>;
#interrupt-cells = <2>;
kind-of-intr = <0>;
xlnx,num-intr-inputs = <2>;
xlnx,kind-of-intr = <0>;
};
xlnx_timer0: timer@41c00000 {

12
arch/riscv/lib/memcpy.S
View File

@ -125,6 +125,14 @@ WEAK(memcpy)
.copy_end:
ret
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define M_SLL sll
#define M_SRL srl
#else
#define M_SLL srl
#define M_SRL sll
#endif
.Lmisaligned_word_copy:
/*
* Misaligned word-wise copy.
@ -144,10 +152,10 @@ WEAK(memcpy)
addi t0, t0, -(SZREG-1)
/* At least one iteration will be executed here, no check */
1:
srl a4, a5, t3
M_SRL a4, a5, t3
REG_L a5, SZREG(a1)
addi a1, a1, SZREG
sll a2, a5, t4
M_SLL a2, a5, t4
or a2, a2, a4
REG_S a2, 0(a0)
addi a0, a0, SZREG

12
arch/riscv/lib/memmove.S
View File

@ -91,6 +91,14 @@ WEAK(memmove)
mv a0, t0
ret
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define M_SLL sll
#define M_SRL srl
#else
#define M_SLL srl
#define M_SRL sll
#endif
.Lmisaligned_word_copy:
/*
* Misaligned word-wise copy.
@ -110,10 +118,10 @@ WEAK(memmove)
addi t0, t0, SZREG-1
/* At least one iteration will be executed here, no check */
1:
sll a4, a5, t4
M_SLL a4, a5, t4
addi a1, a1, -SZREG
REG_L a5, 0(a1)
srl a2, a5, t3
M_SRL a2, a5, t3
or a2, a2, a4
addi a0, a0, -SZREG
REG_S a2, 0(a0)

44
board/andestech/voyager/Kconfig Normal file
View File

@ -0,0 +1,44 @@
if TARGET_ANDES_VOYAGER
config SYS_CPU
default "andes"
config SYS_BOARD
default "voyager"
config SYS_VENDOR
default "andestech"
config SYS_SOC
default "qilai"
config SYS_CONFIG_NAME
default "voyager"
config ENV_SIZE
default 0x2000 if ENV_IS_IN_SPI_FLASH
config ENV_OFFSET
default 0x1F0000 if ENV_IS_IN_SPI_FLASH
config SPL_TEXT_BASE
default 0x400800000
config SPL_OPENSBI_LOAD_ADDR
default 0x400000000
config SYS_FDT_BASE
hex
default 0x81E0000 if OF_SEPARATE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_ANDES
select SUPPORT_SPL
select BINMAN if SPL
imply SMP
imply SPL_RAM_SUPPORT
imply SPL_RAM_DEVICE
imply OF_HAS_PRIOR_STAGE
endif

8
board/andestech/voyager/MAINTAINERS Normal file
View File

@ -0,0 +1,8 @@
Andestech Voyager BOARD
M: Randolph <randolph@andestech.com>
S: Maintained
F: board/andestech/voyager/
F: configs/voyager_spl_defconfig
F: doc/board/andestech/voyager.rst
F: include/configs/qilai.h

6
board/andestech/voyager/Makefile Normal file
View File

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2025 Andes Technology Corporation.
# Randolph Lin, Andes Technology Corporation <randolph@andestech.com>
obj-y := voyager.o

70
board/andestech/voyager/voyager.c Normal file
View File

@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2025 Andes Technology Corporation
* Randolph Lin, Andes Technology Corporation <randolph@andestech.com>
*/
#include <asm/csr.h>
#include <asm/global_data.h>
#include <asm/sbi.h>
#include <config.h>
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
#include <fdtdec.h>
#include <flash.h>
#include <image.h>
#include <init.h>
#include <linux/io.h>
#include <net.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
/* enable andes-l2 cache */
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
enable_caches();
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r(void)
{
/* enable andes-l2 cache */
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
enable_caches();
return 0;
}
#endif
#ifdef CONFIG_SPL
void board_boot_order(u32 *spl_boot_list)
{
u8 i;
u32 boot_devices[] = {
#ifdef CONFIG_SPL_RAM_SUPPORT
BOOT_DEVICE_RAM,
#endif
#ifdef CONFIG_SPL_MMC
BOOT_DEVICE_MMC1,
#endif
};
for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
spl_boot_list[i] = boot_devices[i];
}
#endif

4
board/microchip/mpfs_icicle/Kconfig
View File

@ -59,5 +59,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply MTD_SPI_NAND
imply CMD_MTD
imply CMD_MTDPARTS
imply DM_MAILBOX
imply MPFS_MBOX
imply MISC
imply MPFS_SYSCONTROLLER
endif

123
board/microchip/mpfs_icicle/mpfs_icicle.c
View File

@ -4,52 +4,21 @@
* Padmarao Begari <padmarao.begari@microchip.com>
*/
#include <dm.h>
#include <env.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/sections.h>
#include <dm.h>
#include <dm/devres.h>
#include <env.h>
#include <linux/compat.h>
#include <mpfs-mailbox.h>
DECLARE_GLOBAL_DATA_PTR;
#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
#define MPFS_SYS_SERVICE_CR ((unsigned int *)0x37020050)
#define MPFS_SYS_SERVICE_SR ((unsigned int *)0x37020054)
#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
#define PERIPH_RESET_VALUE 0x1e8u
#define SERVICE_CR_REQ 0x1u
#define SERVICE_SR_BUSY 0x2u
static void read_device_serial_number(u8 *response, u8 response_size)
{
u8 idx;
u8 *response_buf;
unsigned int val;
response_buf = (u8 *)response;
writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
/*
* REQ bit will remain set till the system controller starts
* processing.
*/
do {
val = readl(MPFS_SYS_SERVICE_CR);
} while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
/*
* Once system controller starts processing the busy bit will
* go high and service is completed when busy bit is gone low
*/
do {
val = readl(MPFS_SYS_SERVICE_SR);
} while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
for (idx = 0; idx < response_size; idx++)
response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
}
static unsigned char mac_addr[6];
#if defined(CONFIG_MULTI_DTB_FIT)
int board_fit_config_name_match(const char *name)
@ -145,13 +114,35 @@ int board_late_init(void)
{
u32 ret;
int node;
u8 idx;
u8 device_serial_number[16] = { 0 };
unsigned char mac_addr[6];
char icicle_mac_addr[20];
u8 device_serial_number[16] = {0};
void *blob = (void *)gd->fdt_blob;
struct udevice *dev;
struct mpfs_sys_serv *sys_serv_priv;
read_device_serial_number(device_serial_number, 16);
ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev);
if (ret) {
debug("%s: system controller setup failed\n", __func__);
return ret;
}
sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL);
if (!sys_serv_priv)
return -ENOMEM;
sys_serv_priv->dev = dev;
sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev);
ret = IS_ERR(sys_serv_priv->sys_controller);
if (ret) {
debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret);
return -ENODEV;
}
ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number);
if (ret) {
printf("Cannot read device serial number\n");
return -EINVAL;
}
/* Update MAC address with device serial number */
mac_addr[0] = 0x00;
@ -170,19 +161,6 @@ int board_late_init(void)
}
}
icicle_mac_addr[0] = '[';
sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
icicle_mac_addr[18] = ']';
icicle_mac_addr[19] = '\0';
for (idx = 0; idx < 20; idx++) {
if (icicle_mac_addr[idx] == ':')
icicle_mac_addr[idx] = ' ';
}
env_set("icicle_mac_addr0", icicle_mac_addr);
mac_addr[5] = device_serial_number[0] + 1;
node = fdt_path_offset(blob, "/soc/ethernet@20110000");
@ -194,18 +172,33 @@ int board_late_init(void)
}
}
icicle_mac_addr[0] = '[';
return 0;
}
sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
int ft_board_setup(void *blob, struct bd_info *bd)
{
u32 ret;
int node;
icicle_mac_addr[18] = ']';
icicle_mac_addr[19] = '\0';
for (idx = 0; idx < 20; idx++) {
if (icicle_mac_addr[idx] == ':')
icicle_mac_addr[idx] = ' ';
node = fdt_path_offset(blob, "/soc/ethernet@20110000");
if (node >= 0) {
ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
printf("Error setting local-mac-address property for ethernet@20110000\n");
return -ENODEV;
}
}
mac_addr[5] -= 1;
node = fdt_path_offset(blob, "/soc/ethernet@20112000");
if (node >= 0) {
ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
printf("Error setting local-mac-address property for ethernet@20112000\n");
return -ENODEV;
}
}
env_set("icicle_mac_addr1", icicle_mac_addr);
return 0;
}

4
board/phytec/phycore_am62ax/phycore_am62ax.env
View File

@ -26,7 +26,11 @@ spi_fdt_addr=0x700000
spi_image_addr=0x800000
spi_ramdisk_addr=0x2200000
#ifdef CONFIG_BOOTMETH_RAUC
bootmeths=rauc script efi extlinux pxe
#else
bootmeths=script efi extlinux pxe
#endif
boot_targets=mmc1 mmc0 spi_flash dhcp
watchdog=watchdog@e000000

4
board/phytec/phycore_am62x/phycore_am62x.env
View File

@ -26,7 +26,11 @@ spi_fdt_addr=0x700000
spi_image_addr=0x800000
spi_ramdisk_addr=0x2200000
#ifdef CONFIG_BOOTMETH_RAUC
bootmeths=rauc script efi extlinux pxe
#else
bootmeths=script efi extlinux pxe
#endif
boot_targets=mmc1 mmc0 spi_flash dhcp
watchdog=watchdog@e000000

4
board/phytec/phycore_am64x/phycore_am64x.env
View File

@ -25,7 +25,11 @@ spi_fdt_addr=0x700000
spi_image_addr=0x800000
spi_ramdisk_addr=0x2200000
#ifdef CONFIG_BOOTMETH_RAUC
bootmeths=rauc script efi extlinux pxe
#else
bootmeths=script efi extlinux pxe
#endif
boot_targets=mmc1 mmc0 spi_flash dhcp
watchdog=watchdog@e000000

3
board/phytec/phycore_imx93/spl.c
View File

@ -52,8 +52,7 @@ void spl_dram_init(void)
int ret;
enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
/* NOTE: In SPL lpi2c3 is mapped to bus 0 */
ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
goto out;

130
board/renesas/sparrowhawk/sparrowhawk.c
View File

@ -6,8 +6,12 @@
#include <asm/io.h>
#include <compiler.h>
#include <dbsc5.h>
#include <spi.h>
#include <spi_flash.h>
#include <spl.h>
#include "../../../drivers/mtd/spi/sf_internal.h"
#if defined(CONFIG_XPL_BUILD)
static const struct renesas_dbsc5_board_config
@ -112,12 +116,134 @@ dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
* Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk
* board variants from each other automatically.
*/
if (modemr0 & BIT(19))
if ((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19)))
return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config;
else
return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config;
}
static bool renesas_v4h_sparrowhawk_is_evta1 = false;
unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
{
const u8 sf_ids_evta1[6] = { 0x01, 0x02, 0x20, 0x4d, 0x00, 0x81 };
renesas_v4h_sparrowhawk_is_evta1 = !memcmp(sf_ids_evta1, flash->info->id,
sizeof(sf_ids_evta1));
return CONFIG_SYS_SPI_U_BOOT_OFFS;
}
void spl_perform_fixups(struct spl_image_info *spl_image)
{
void *blob = spl_image_fdt_addr(spl_image);
int err, offs;
u32 size;
if (!renesas_v4h_sparrowhawk_is_evta1)
return;
printf("EVTA1 board detected\n");
/*
* MicroSD voltage switch is not populated on Sparrow Hawk EVTA1,
* rewrite MicroSD slot regulator to only support 3V3 and disable
* UHS modes in MicroSD slot node.
*/
if (!blob)
return;
err = fdt_check_header(blob);
if (err < 0) {
printf("Invalid FDT header: %s\n", fdt_strerror(err));
return;
}
size = fdt_totalsize(blob);
err = fdt_open_into(blob, blob, size + 64);
if (err < 0) {
printf("Failed to expand DT\n");
return;
}
offs = fdt_path_offset(blob, "/regulator-vcc-sdhi");
if (offs < 0) {
printf("Failed to locate MicroSD regulator node: %d\n", offs);
return;
}
err = fdt_setprop_string(blob, offs, "compatible", "regulator-fixed");
if (err < 0) {
printf("Failed to set fixed MicroSD regulator: %d\n", err);
return;
}
err = fdt_setprop_u32(blob, offs, "regulator-min-microvolt", 3300000);
if (err < 0) {
printf("Failed to set MicroSD regulator minimum voltage: %d\n", err);
return;
}
err = fdt_nop_property(blob, offs, "gpios");
if (err < 0) {
printf("Failed to remove MicroSD regulator gpios: %d\n", err);
return;
}
err = fdt_nop_property(blob, offs, "gpios-states");
if (err < 0) {
printf("Failed to remove MicroSD regulator gpio states: %d\n", err);
return;
}
err = fdt_nop_property(blob, offs, "states");
if (err < 0) {
printf("Failed to remove MicroSD regulator states: %d\n", err);
return;
}
offs = fdt_path_offset(blob, "/soc/mmc@ee140000");
if (offs < 0) {
printf("Failed to locate MicroSD device node: %d\n", offs);
return;
}
err = fdt_nop_property(blob, offs, "sd-uhs-sdr50");
if (err < 0) {
printf("Failed to disable SDR50 mode in MicroSD node: %d\n", err);
return;
}
err = fdt_nop_property(blob, offs, "sd-uhs-sdr104");
if (err < 0) {
printf("Failed to disable SDR104 mode in MicroSD node: %d\n", err);
return;
}
err = fdt_setprop_string(blob, offs, "pinctrl-names", "default");
if (err < 0) {
printf("Failed to set fixed MicroSD pin names: %d\n", err);
return;
}
err = fdt_nop_property(blob, offs, "pinctrl-1");
if (err < 0) {
printf("Failed to disable UHS pins in MicroSD node: %d\n", err);
return;
}
offs = fdt_path_offset(blob, "/soc/pinctrl@e6050000/avb0/pins-vddq18-25-avb");
if (offs < 0) {
printf("Failed to locate AVB pinctrl node: %d\n", offs);
return;
}
err = fdt_setprop_u32(blob, offs, "power-source", 2500);
if (err < 0) {
printf("Failed to set AVB IO voltage: %d\n", err);
return;
}
}
#endif
#define RST_MODEMR0 0xe6160000
@ -130,7 +256,7 @@ void renesas_dram_init_banksize(void)
int bank;
/* 8 GiB device, do nothing. */
if (!(modemr0 & BIT(19)))
if (!((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19))))
return;
/* 16 GiB device, adjust memory map. */

8
board/starfive/visionfive2/visionfive2-i2c-eeprom.c
View File

@ -275,7 +275,7 @@ static int prog_eeprom(unsigned int size)
if (is_match_magic()) {
printf("MAGIC ERROR, Please check the data@%p.\n", pbuf.buf);
return -1;
return CMD_RET_FAILURE;
}
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
@ -285,7 +285,7 @@ static int prog_eeprom(unsigned int size)
if (ret) {
printf("Get i2c bus:%d addr:%d fail.\n", CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR);
return ret;
return CMD_RET_FAILURE;
}
for (i = 0, p = (u8 *)pbuf.buf; i < size; ) {
@ -314,11 +314,11 @@ static int prog_eeprom(unsigned int size)
if (ret) {
has_been_read = -1;
printf("Programming failed.\n");
return -1;
return CMD_RET_FAILURE;
}
printf("Programming passed.\n");
return 0;
return CMD_RET_SUCCESS;
}
/**

1
board/xilinx/mbv/Kconfig
View File

@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS
imply SPL_RAM_DEVICE
imply CMD_SBI
imply CMD_PING
imply OF_HAS_PRIOR_STAGE
source "board/xilinx/Kconfig"

3
boot/Kconfig
View File

@ -869,7 +869,6 @@ config EXPO
config BOOTMETH_RAUC
bool "Bootdev support for RAUC A/B systems"
depends on CMDLINE
select BOOTMETH_GLOBAL
select HUSH_PARSER
help
Enables support for booting RAUC A/B systems from MMC devices. This
@ -1057,7 +1056,7 @@ config SYS_BOOTM_LEN
hex "Maximum size of a decompresed OS image"
depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \
LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT
default 0x4000000 if PPC || ARM64
default 0x4000000 if PPC || ARM64 || RISCV
default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
default 0x800000
help

23
boot/bootmeth_rauc.c
View File

@ -52,6 +52,18 @@ struct distro_rauc_priv {
struct distro_rauc_slot **slots;
};
static void distro_rauc_priv_free(struct distro_rauc_priv *priv)
{
int i;
for (i = 0; priv->slots[i]; i++) {
free(priv->slots[i]->name);
free(priv->slots[i]);
}
free(priv->slots);
free(priv);
}
static struct distro_rauc_slot *get_slot(struct distro_rauc_priv *priv,
const char *slot_name)
{
@ -187,13 +199,8 @@ static int distro_rauc_read_bootflow(struct udevice *dev, struct bootflow *bflow
ret = distro_rauc_scan_parts(bflow);
if (ret < 0) {
for (i = 0; priv->slots[i]->name; i++) {
free(priv->slots[i]->name);
free(priv->slots[i]);
}
free(priv);
distro_rauc_priv_free(priv);
free(boot_order_copy);
bflow->bootmeth_priv = NULL;
return ret;
}
@ -402,6 +409,8 @@ static int distro_rauc_boot(struct udevice *dev, struct bootflow *bflow)
if (ret)
return log_msg_ret("boot", ret);
distro_rauc_priv_free(priv);
return 0;
}
@ -410,7 +419,7 @@ static int distro_rauc_bootmeth_bind(struct udevice *dev)
struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev);
plat->desc = "RAUC distro boot from MMC";
plat->flags = BOOTMETHF_GLOBAL;
plat->flags = BOOTMETHF_ANY_PART;
return 0;
}

2
cmd/Kconfig
View File

@ -2117,7 +2117,7 @@ config CMD_DHCP
config CMD_DNS
bool "dns"
select PROT_DNS_LWIP if NET_LWIP
select DNS
help
Lookup the IP of a hostname

108
cmd/lwip/dns.c
View File

@ -2,115 +2,7 @@
/* Copyright (C) 2024 Linaro Ltd. */
#include <command.h>
#include <console.h>
#include <env.h>
#include <lwip/dns.h>
#include <lwip/timeouts.h>
#include <net.h>
#include <time.h>
U_BOOT_CMD(dns, 3, 1, do_dns, "lookup the IP of a hostname",
"hostname [envvar]");
#define DNS_RESEND_MS 1000
#define DNS_TIMEOUT_MS 10000
struct dns_cb_arg {
ip_addr_t host_ipaddr;
const char *var;
bool done;
};
static void do_dns_tmr(void *arg)
{
dns_tmr();
}
static void dns_cb(const char *name, const ip_addr_t *ipaddr, void *arg)
{
struct dns_cb_arg *dns_cb_arg = arg;
char *ipstr = ip4addr_ntoa(ipaddr);
dns_cb_arg->done = true;
if (!ipaddr) {
printf("DNS: host not found\n");
dns_cb_arg->host_ipaddr.addr = 0;
return;
}
dns_cb_arg->host_ipaddr.addr = ipaddr->addr;
if (dns_cb_arg->var)
env_set(dns_cb_arg->var, ipstr);
}
static int dns_loop(struct udevice *udev, const char *name, const char *var)
{
struct dns_cb_arg dns_cb_arg = { };
struct netif *netif;
ip_addr_t ipaddr;
ulong start;
int ret;
dns_cb_arg.var = var;
netif = net_lwip_new_netif(udev);
if (!netif)
return CMD_RET_FAILURE;
if (net_lwip_dns_init()) {
net_lwip_remove_netif(netif);
return CMD_RET_FAILURE;
}
dns_cb_arg.done = false;
ret = dns_gethostbyname(name, &ipaddr, dns_cb, &dns_cb_arg);
if (ret == ERR_OK) {
dns_cb(name, &ipaddr, &dns_cb_arg);
} else if (ret == ERR_INPROGRESS) {
start = get_timer(0);
sys_timeout(DNS_RESEND_MS, do_dns_tmr, NULL);
do {
net_lwip_rx(udev, netif);
if (dns_cb_arg.done)
break;
if (ctrlc()) {
printf("\nAbort\n");
break;
}
} while (get_timer(start) < DNS_TIMEOUT_MS);
sys_untimeout(do_dns_tmr, NULL);
}
net_lwip_remove_netif(netif);
if (dns_cb_arg.done && dns_cb_arg.host_ipaddr.addr != 0) {
if (!var)
printf("%s\n", ipaddr_ntoa(&ipaddr));
return CMD_RET_SUCCESS;
}
return CMD_RET_FAILURE;
}
int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
char *name;
char *var = NULL;
if (argc == 1 || argc > 3)
return CMD_RET_USAGE;
name = argv[1];
if (argc == 3)
var = argv[2];
if (net_lwip_eth_start() < 0)
return CMD_RET_FAILURE;
return dns_loop(eth_get_dev(), name, var);
}

1
cmd/lwip/ping.c
View File

@ -170,6 +170,7 @@ int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
if (net_lwip_dns_resolve(argv[1], &addr))
return CMD_RET_USAGE;
net_try_count = 1;
restart:
if (net_lwip_eth_start() < 0 || ping_loop(eth_get_dev(), &addr) < 0) {
if (net_start_again() == 0)

1
cmd/lwip/sntp.c
View File

@ -79,7 +79,6 @@ static int sntp_loop(struct udevice *udev, ip_addr_t *srvip)
sys_timeout(SNTP_TIMEOUT, no_response, NULL);
while (sntp_state == NOT_DONE) {
net_lwip_rx(udev, netif);
sys_check_timeouts();
if (ctrlc()) {
printf("\nAbort\n");
sntp_state = ABORTED;

15
cmd/mtd.c
View File

@ -17,6 +17,7 @@
#include <malloc.h>
#include <mapmem.h>
#include <mtd.h>
#include <time.h>
#include <dm/devres.h>
#include <linux/err.h>
@ -466,8 +467,9 @@ static int mtd_special_write_oob(struct mtd_info *mtd, u64 off,
static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
bool dump, read, raw, woob, write_empty_pages, has_pages = false;
bool dump, read, raw, woob, benchmark, write_empty_pages, has_pages = false;
u64 start_off, off, len, remaining, default_len;
unsigned long bench_start, bench_end;
struct mtd_oob_ops io_op = {};
uint user_addr = 0, npages;
const char *cmd = argv[0];
@ -490,6 +492,7 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc,
read = dump || !strncmp(cmd, "read", 4);
raw = strstr(cmd, ".raw");
woob = strstr(cmd, ".oob");
benchmark = strstr(cmd, ".benchmark");
write_empty_pages = !has_pages || strstr(cmd, ".dontskipff");
argc -= 2;
@ -559,6 +562,9 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc,
led_activity_blink();
if (benchmark)
bench_start = timer_get_us();
/* Loop over the pages to do the actual read/write */
while (remaining) {
/* Skip the block if it is bad */
@ -586,6 +592,13 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc,
io_op.oobbuf += io_op.oobretlen;
}
if (benchmark && bench_start) {
bench_end = timer_get_us();
printf("%s speed: %lukiB/s\n",
read ? "Read" : "Write",
((io_op.len * 1000000) / (bench_end - bench_start)) / 1024);
}
led_activity_off();
if (!ret && dump)

56
cmd/nand.c
View File

@ -37,6 +37,7 @@
#include <asm/byteorder.h>
#include <jffs2/jffs2.h>
#include <nand.h>
#include <display_options.h>
#include "legacy-mtd-utils.h"
@ -159,7 +160,7 @@ free_memory:
}
static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob,
int repeat)
int ecc, int repeat)
{
int i;
u_char *datbuf, *oobbuf, *p;
@ -191,39 +192,30 @@ static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob,
ops.oobbuf = oobbuf;
ops.len = mtd->writesize;
ops.ooblen = mtd->oobsize;
ops.mode = MTD_OPS_RAW;
if (ecc)
ops.mode = MTD_OPS_PLACE_OOB;
else
ops.mode = MTD_OPS_RAW;
i = mtd_read_oob(mtd, addr, &ops);
if (i < 0) {
printf("Error (%d) reading page %08lx\n", i, off);
printf("Error reading page at offset %08lx, %d %s\n",
off, i, i == -EUCLEAN ? "correctable" :
"uncorrectable, dumping raw data");
ret = 1;
goto free_all;
}
printf("Page %08lx dump:\n", off);
printf("\nPage at offset %08lx dump:\n", off);
if (!only_oob) {
i = mtd->writesize >> 4;
i = mtd->writesize;
p = datbuf;
while (i--) {
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
p[8], p[9], p[10], p[11], p[12], p[13], p[14],
p[15]);
p += 16;
}
print_buffer(off, p, 1, i, 16);
}
puts("OOB:\n");
i = mtd->oobsize >> 3;
puts("\nOOB:\n");
i = mtd->oobsize;
p = oobbuf;
while (i--) {
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
p += 8;
}
print_buffer(0, p, 1, i, 8);
free_all:
free(oobbuf);
free_dat:
free(datbuf);
@ -412,7 +404,7 @@ int do_nand_env_oob(struct cmd_tbl *cmdtp, int argc, char *const argv[])
}
ops.datbuf = NULL;
ops.mode = MTD_OOB_AUTO;
ops.mode = MTD_OPS_AUTO_OOB;
ops.ooboffs = 0;
ops.ooblen = ENV_OFFSET_SIZE;
ops.oobbuf = (void *) oob_buf;
@ -708,11 +700,19 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc,
}
if (strncmp(cmd, "dump", 4) == 0) {
int only_oob, ecc;
if (argc < 3)
goto usage;
only_oob = !strcmp(&cmd[4], ".oob") || !strcmp(&cmd[4], ".ecc.oob") ||
!strcmp(&cmd[4], ".oob.ecc");
ecc = !strcmp(&cmd[4], ".ecc") || !strcmp(&cmd[4], ".ecc.oob") ||
!strcmp(&cmd[4], ".oob.ecc");
off = (int)hextoul(argv[2], NULL);
ret = nand_dump(mtd, off, !strcmp(&cmd[4], ".oob"), repeat);
ret = nand_dump(mtd, off, only_oob, ecc, repeat);
return ret == 0 ? 1 : 0;
}
@ -1026,8 +1026,8 @@ U_BOOT_LONGHELP(nand,
"nand write - addr off|partition size\n"
" read/write 'size' bytes starting at offset 'off'\n"
" to/from memory address 'addr', skipping bad blocks.\n"
"nand read.raw - addr off|partition [count]\n"
"nand write.raw[.noverify] - addr off|partition [count]\n"
"nand read.raw - addr off|partition [pages]\n"
"nand write.raw[.noverify] - addr off|partition [pages]\n"
" Use read.raw/write.raw to avoid ECC and access the flash as-is.\n"
#ifdef CONFIG_CMD_NAND_TRIMFFS
"nand write.trimffs - addr off|partition size\n"
@ -1042,7 +1042,7 @@ U_BOOT_LONGHELP(nand,
"nand erase.part [clean] partition - erase entire mtd partition'\n"
"nand erase.chip [clean] - erase entire chip'\n"
"nand bad - show bad blocks\n"
"nand dump[.oob] off - dump page\n"
"nand dump[.oob][.ecc] off - dump raw (default) or ecc corrected page at offset\n"
#ifdef CONFIG_CMD_NAND_WATCH
"nand watch <off> <size> - check an area for bitflips\n"
"nand watch.part <part> - check a partition for bitflips\n"

1
configs/A20-OLinuXino-Lime2_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_I2C1_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

3
configs/LicheePi_Zero_defconfig
View File

@ -1,8 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun8i-v3s-licheepi-zero"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_NO_NET=y

1
configs/ae350_rv32_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_ANDES_AE350=y
CONFIG_SYS_MONITOR_BASE=0x88000000

1
configs/ae350_rv32_falcon_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv32_falcon_xip_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv32_spl_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv32_spl_xip_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv32_xip_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_ANDES_AE350=y
CONFIG_XIP=y

1
configs/ae350_rv64_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y

1
configs/ae350_rv64_falcon_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv64_falcon_xip_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv64_spl_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv64_spl_xip_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_AE350=y

1
configs/ae350_rv64_xip_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y

2
configs/avaota-a1_defconfig
View File

@ -22,6 +22,8 @@ CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_REGULATOR_AXP=y
CONFIG_AXP717_POWER=y
CONFIG_AXP_I2C_ADDRESS=0x35

1
configs/hihope_rzg2_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m-ex"

1
configs/ibex-ast2700_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_DM_RESET=y
CONFIG_SPL_TEXT_BASE=0x14bc0080
CONFIG_SPL_BSS_START_ADDR=0x14bd7800
CONFIG_SPL_BSS_MAX_SIZE=0x800
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x83000000
CONFIG_SPL_SIZE_LIMIT=0x16000
CONFIG_SPL=y

1
configs/imx93-phycore_defconfig
View File

@ -92,6 +92,7 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK_IMX93=y
CONFIG_CLK_IMX93=y
CONFIG_DFU_MMC=y

1
configs/k230_canmv_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80400000
CONFIG_DEFAULT_DEVICE_TREE="k230-canmv"
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0xc000000
CONFIG_TARGET_K230_CANMV=y
CONFIG_ARCH_RV64I=y

3
configs/microchip_mpfs_icicle_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_MEM_TOP_HIDE=0x400000
# CONFIG_DEBUG_UART is not set
@ -13,6 +14,7 @@ CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
@ -20,6 +22,7 @@ CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM_MTD=y

1
configs/milkv_duo_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000
CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_IDENT_STRING="milkv_duo"
CONFIG_TARGET_MILKV_DUO=y

4
configs/pinecube_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun8i-s3-pinecube"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_SUNXI_DRAM_DDR3_1333=y
@ -9,13 +9,13 @@ CONFIG_DRAM_ODT_EN=y
CONFIG_I2C0_ENABLE=y
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_SPL_I2C=y
CONFIG_NO_NET=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_MTD=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP209_POWER=y
CONFIG_AXP_DCDC2_VOLT=1250
CONFIG_AXP_DCDC3_VOLT=3300

1
configs/qemu-riscv32_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_FIT=y

1
configs/qemu-riscv32_smode_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y

1
configs/qemu-riscv32_spl_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y

1
configs/qemu-riscv64_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y

1
configs/qemu-riscv64_smode_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y

1
configs/qemu-riscv64_spl_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y

1
configs/r8a77970_eagle_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000

1
configs/r8a77970_v3msk_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000

1
configs/r8a77990_ebisu_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000

1
configs/r8a77995_draak_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000

1
configs/r8a779a0_falcon_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_ARM=y
CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN4=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_TEXT_BASE=0x50000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC00000
CONFIG_ENV_SECT_SIZE=0x40000

9
configs/r8a779g3_sparrowhawk_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_GPIO_HOG=y
CONFIG_REMOTEPROC_RENESAS_APMU=y
CONFIG_BITBANGMII=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NVME_PCI=y
CONFIG_PCI=y
@ -34,6 +35,14 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_RENESAS_RAVB=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_USB=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_GENERIC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_RCAR is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y

2
configs/radxa-cubie-a5e_defconfig
View File

@ -22,6 +22,8 @@ CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_REGULATOR_AXP=y
CONFIG_AXP717_POWER=y
CONFIG_AXP_DCDC2_VOLT=920

1
configs/renesas_rzg2l_smarc_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_SYS_INIT_SP_BSS_OFFSET=1048576
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_ENV_SIZE=0x20000

1
configs/rzg2_beacon_defconfig
View File

@ -3,7 +3,6 @@
CONFIG_ARM=y
CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN3=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000

2
configs/sandbox_defconfig
View File

@ -207,9 +207,7 @@ CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_STRATIX_II=y
CONFIG_FPGA_STRATIX_V=y
CONFIG_FPGA_ACEX1K=y
CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_LATTICE=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN2=y
CONFIG_FPGA_SPARTAN3=y

1
configs/sifive_unleashed_defconfig
View File

@ -11,7 +11,6 @@ CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x81cfe70
CONFIG_SPL_BSS_START_ADDR=0x85000000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y

1
configs/sifive_unmatched_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x81cfe60
CONFIG_SPL_BSS_START_ADDR=0x85000000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y

1
configs/silinux_ek874_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3F0000

1
configs/sipeed_licheerv_nano_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000
CONFIG_DEFAULT_DEVICE_TREE="sg2002-licheerv-nano-b"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_IDENT_STRING="licheerv_nano"
CONFIG_TARGET_LICHEERV_NANO=y

1
configs/sipeed_maix_bitm_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_SF_DEFAULT_BUS=3
CONFIG_TARGET_SIPEED_MAIX=y

1
configs/sipeed_maix_smode_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_SF_DEFAULT_BUS=3
CONFIG_TARGET_SIPEED_MAIX=y

1
configs/starfive_visionfive2_defconfig
View File

@ -18,7 +18,6 @@ CONFIG_SPL_STACK=0x8180000
CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_SPL_BSS_START_ADDR=0x8040000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y

1
configs/th1520_lpi4a_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
CONFIG_SPL_STACK=0xffe0170000
CONFIG_SPL_BSS_START_ADDR=0xffe0160000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL=y
CONFIG_TARGET_TH1520_LPI4A=y

65
configs/voyager_spl_defconfig Normal file
View File

@ -0,0 +1,65 @@
CONFIG_RISCV=y
CONFIG_TEXT_BASE=0x401800000
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x410000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="qilai-voyager"
CONFIG_SPL_BSS_START_ADDR=0x400400000
CONFIG_SYS_LOAD_ADDR=0x400100000
CONFIG_SPL=y
CONFIG_TARGET_ANDES_VOYAGER=y
CONFIG_NR_CPUS=4
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x410000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE_F=0x2000
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_CYCLIC is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_BOARD_INIT is not set
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RETRY_COUNT=50
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC=y
CONFIG_FTSDC010=y
CONFIG_FTSDC010_SDIO=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ATCSPI200_SPI=y
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
CONFIG_WDT_ATCWDT200=y
# CONFIG_BINMAN_FDT is not set

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