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x86: ivybridge: Move sandybridge init to the lpc probe() method

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The watchdog can be reset later when probing the LPC after relocation.
Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-01-17 16:11:21 -07:00 committed by Bin Meng
parent 17e0a9ab08
commit fcd30cdfa8
2 changed files with 18 additions and 17 deletions
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16
arch/x86/cpu/ivybridge/early_init.c
View File

@ -14,20 +14,6 @@
#include <asm/arch/pch.h> #include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h> #include <asm/arch/sandybridge.h>
static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev)
{
/* Setting up Southbridge. In the northbridge code. */
debug("Setting up static southbridge registers\n");
x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
debug("Disabling watchdog reboot\n");
setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
}
static void sandybridge_setup_northbridge_bars(struct udevice *dev) static void sandybridge_setup_northbridge_bars(struct udevice *dev)
{ {
/* Set up all hardcoded northbridge BARs */ /* Set up all hardcoded northbridge BARs */
@ -74,8 +60,6 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
dm_pci_write_config8(dev, 0xf3, reg8); dm_pci_write_config8(dev, 0xf3, reg8);
} }
sandybridge_setup_lpc_bars(PCH_LPC_DEV);
sandybridge_setup_northbridge_bars(dev); sandybridge_setup_northbridge_bars(dev);
/* Device Enable */ /* Device Enable */

19
arch/x86/cpu/ivybridge/lpc.c
View File

@ -609,6 +609,23 @@ void lpc_enable(pci_dev_t dev)
setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
} }
static int bd82x6x_lpc_early_init(struct udevice *dev)
{
/* Setting up Southbridge. In the northbridge code. */
debug("Setting up static southbridge registers\n");
dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80);
debug("Disabling watchdog reboot\n");
setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
return 0;
}
static int bd82x6x_lpc_probe(struct udevice *dev) static int bd82x6x_lpc_probe(struct udevice *dev)
{ {
int ret; int ret;
@ -622,7 +639,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev)
return ret; return ret;
} }
return 0; return bd82x6x_lpc_early_init(dev);
} }
static const struct udevice_id bd82x6x_lpc_ids[] = { static const struct udevice_id bd82x6x_lpc_ids[] = {