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net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_USE_PORT

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The CFG_SH_ETHER_USE_PORT configuration option is a remnant from
before U-Boot DM existed and SH Ethernet made full use of it, and
is no longer used, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2025-06-30 20:51:11 +02:00
parent 45e0a55ff6
commit fc85e55205
12 changed files with 0 additions and 16 deletions
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3
README
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@ -379,9 +379,6 @@ The following options need to be configured:
CONFIG_SH_ETHER CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller Support for Renesas on-chip Ethernet controller
CFG_SH_ETHER_USE_PORT
Define the number of ports to be used
CFG_SH_ETHER_PHY_ADDR CFG_SH_ETHER_PHY_ADDR
Define the ETH PHY's address Define the ETH PHY's address

3
drivers/net/sh_eth.c
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@ -29,9 +29,6 @@
#include "sh_eth.h" #include "sh_eth.h"
#ifndef CFG_SH_ETHER_USE_PORT
# error "Please define CFG_SH_ETHER_USE_PORT"
#endif
#ifndef CFG_SH_ETHER_PHY_ADDR #ifndef CFG_SH_ETHER_PHY_ADDR
# error "Please define CFG_SH_ETHER_PHY_ADDR" # error "Please define CFG_SH_ETHER_PHY_ADDR"
#endif #endif

1
include/configs/alt.h
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@ -21,7 +21,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/condor.h
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@ -14,7 +14,6 @@
/* Environment compatibility */ /* Environment compatibility */
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/gose.h
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@ -20,7 +20,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/grpeach.h
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@ -17,7 +17,6 @@
#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
/* Network interface */ /* Network interface */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0 #define CFG_SH_ETHER_PHY_ADDR 0
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/koelsch.h
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@ -20,7 +20,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/lager.h
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@ -21,7 +21,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/porter.h
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@ -22,7 +22,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/silk.h
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@ -22,7 +22,6 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/stout.h
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@ -26,7 +26,6 @@
#define CFG_SCIF_A #define CFG_SCIF_A
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK

1
include/configs/v3hsk.h
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@ -15,7 +15,6 @@
/* Environment compatibility */ /* Environment compatibility */
/* SH Ether */ /* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x0 #define CFG_SH_ETHER_PHY_ADDR 0x0
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_WRITEBACK