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global: Migrate CONFIG_SAR2_REG to CFG

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Perform a simple rename of CONFIG_SAR2_REG to CFG_SAR2_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-04 10:13:41 -05:00
parent 3db78c830f
commit f9932d38a3
2 changed files with 5 additions and 5 deletions
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4
arch/arm/mach-mvebu/cpu.c
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@ -195,7 +195,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
int i; int i;
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS) #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */
#else #else
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
#endif #endif
@ -205,7 +205,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
* Shift CPU0 clock frequency select bit from SAR2 register * Shift CPU0 clock frequency select bit from SAR2 register
* into correct position * into correct position
*/ */
freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
>> SAR2_CPU_FREQ_OFFS) << 3; >> SAR2_CPU_FREQ_OFFS) << 3;
#endif #endif
for (i = 0; sar_freq_tab[i].val != 0xff; i++) { for (i = 0; sar_freq_tab[i].val != 0xff; i++) {

6
arch/arm/mach-mvebu/include/mach/soc.h
View File

@ -135,7 +135,7 @@
#if defined(CONFIG_ARMADA_375) #if defined(CONFIG_ARMADA_375)
/* SAR values for Armada 375 */ /* SAR values for Armada 375 */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) #define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204)) #define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204))
#define SAR_CPU_FREQ_OFFS 17 #define SAR_CPU_FREQ_OFFS 17
#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
@ -174,7 +174,7 @@
#elif defined(CONFIG_ARMADA_MSYS) #elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */ /* SAR values for MSYS */
#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) #define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
#define SAR_CPU_FREQ_OFFS 18 #define SAR_CPU_FREQ_OFFS 18
#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
@ -192,7 +192,7 @@
#elif defined(CONFIG_ARMADA_XP) #elif defined(CONFIG_ARMADA_XP)
/* SAR values for Armada XP */ /* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) #define CFG_SAR2_REG (MVEBU_REGISTER(0x18234))
#define SAR_CPU_FREQ_OFFS 21 #define SAR_CPU_FREQ_OFFS 21
#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)