From f4cf8710a16c0fe1c98e8265b50ac2826869becf Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 28 Jan 2023 16:55:31 +0100 Subject: [PATCH 1/7] video: ti: am335x: restore driver-model code The commit 82f7b869f5d7a ("video: Drop CONFIG_AM335X_LCD") removed not only the LCD legacy implementation but also the code with driver model support. The patch restores the code with driver model support. Fixes: 82f7b869f5d7a ("video: Drop CONFIG_AM335X_LCD") Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- drivers/video/Kconfig | 2 + drivers/video/Makefile | 1 + drivers/video/ti/Kconfig | 8 + drivers/video/ti/Makefile | 6 + drivers/video/ti/tilcdc-panel.c | 172 +++++++++++++ drivers/video/ti/tilcdc-panel.h | 14 ++ drivers/video/ti/tilcdc.c | 425 ++++++++++++++++++++++++++++++++ drivers/video/ti/tilcdc.h | 38 +++ 8 files changed, 666 insertions(+) create mode 100644 drivers/video/ti/Kconfig create mode 100644 drivers/video/ti/Makefile create mode 100644 drivers/video/ti/tilcdc-panel.c create mode 100644 drivers/video/ti/tilcdc-panel.h create mode 100644 drivers/video/ti/tilcdc.c create mode 100644 drivers/video/ti/tilcdc.h diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 440b161b842..e08b7a77dd2 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -576,6 +576,8 @@ config ATMEL_HLCD help HLCDC supports video output to an attached LCD panel. +source "drivers/video/ti/Kconfig" + source "drivers/video/exynos/Kconfig" config LOGICORE_DP_TX diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 40a871d638e..b359b078405 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -26,6 +26,7 @@ obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ +obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig new file mode 100644 index 00000000000..3081e9e8c09 --- /dev/null +++ b/drivers/video/ti/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Dario Binacchi +# +config AM335X_LCD + bool "Enable AM335x video support" + help + Supports video output to an attached LCD panel. diff --git a/drivers/video/ti/Makefile b/drivers/video/ti/Makefile new file mode 100644 index 00000000000..1f551c84f34 --- /dev/null +++ b/drivers/video/ti/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Dario Binacchi +# + +obj-$(CONFIG_AM335X_LCD) += tilcdc.o tilcdc-panel.o diff --git a/drivers/video/ti/tilcdc-panel.c b/drivers/video/ti/tilcdc-panel.c new file mode 100644 index 00000000000..df95086a515 --- /dev/null +++ b/drivers/video/ti/tilcdc-panel.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OMAP panel support + * + * Copyright (C) 2020 Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tilcdc.h" + +struct tilcdc_panel_priv { + struct tilcdc_panel_info info; + struct display_timing timing; + struct udevice *backlight; + struct gpio_desc enable; +}; + +static int tilcdc_panel_enable_backlight(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + if (dm_gpio_is_valid(&priv->enable)) + dm_gpio_set_value(&priv->enable, 1); + + if (priv->backlight) + return backlight_enable(priv->backlight); + + return 0; +} + +static int tilcdc_panel_set_backlight(struct udevice *dev, int percent) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + if (dm_gpio_is_valid(&priv->enable)) + dm_gpio_set_value(&priv->enable, 1); + + if (priv->backlight) + return backlight_set_brightness(priv->backlight, percent); + + return 0; +} + +int tilcdc_panel_get_display_info(struct udevice *dev, + struct tilcdc_panel_info *info) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + memcpy(info, &priv->info, sizeof(*info)); + return 0; +} + +static int tilcdc_panel_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->timing, sizeof(*timing)); + return 0; +} + +static int tilcdc_panel_remove(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + if (dm_gpio_is_valid(&priv->enable)) + dm_gpio_free(dev, &priv->enable); + + return 0; +} + +static int tilcdc_panel_probe(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + int err; + + err = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (err) + dev_warn(dev, "failed to get backlight\n"); + + err = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, + GPIOD_IS_OUT); + if (err) { + dev_warn(dev, "failed to get enable GPIO\n"); + if (err != -ENOENT) + return err; + } + + return 0; +} + +static int tilcdc_panel_of_to_plat(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + ofnode node; + int err; + + err = ofnode_decode_display_timing(dev_ofnode(dev), 0, &priv->timing); + if (err) { + dev_err(dev, "failed to get display timing\n"); + return err; + } + + node = dev_read_subnode(dev, "panel-info"); + if (!ofnode_valid(node)) { + dev_err(dev, "missing 'panel-info' node\n"); + return -ENXIO; + } + + err |= ofnode_read_u32(node, "ac-bias", &priv->info.ac_bias); + err |= ofnode_read_u32(node, "ac-bias-intrpt", + &priv->info.ac_bias_intrpt); + err |= ofnode_read_u32(node, "dma-burst-sz", &priv->info.dma_burst_sz); + err |= ofnode_read_u32(node, "bpp", &priv->info.bpp); + err |= ofnode_read_u32(node, "fdd", &priv->info.fdd); + err |= ofnode_read_u32(node, "sync-edge", &priv->info.sync_edge); + err |= ofnode_read_u32(node, "sync-ctrl", &priv->info.sync_ctrl); + err |= ofnode_read_u32(node, "raster-order", &priv->info.raster_order); + err |= ofnode_read_u32(node, "fifo-th", &priv->info.fifo_th); + if (err) { + dev_err(dev, "failed to get panel info\n"); + return err; + } + + /* optional */ + priv->info.tft_alt_mode = ofnode_read_bool(node, "tft-alt-mode"); + priv->info.invert_pxl_clk = ofnode_read_bool(node, "invert-pxl-clk"); + + dev_dbg(dev, "LCD: %dx%d, bpp=%d, clk=%d Hz\n", + priv->timing.hactive.typ, priv->timing.vactive.typ, + priv->info.bpp, priv->timing.pixelclock.typ); + dev_dbg(dev, " hbp=%d, hfp=%d, hsw=%d\n", + priv->timing.hback_porch.typ, priv->timing.hfront_porch.typ, + priv->timing.hsync_len.typ); + dev_dbg(dev, " vbp=%d, vfp=%d, vsw=%d\n", + priv->timing.vback_porch.typ, priv->timing.vfront_porch.typ, + priv->timing.vsync_len.typ); + + return 0; +} + +static const struct panel_ops tilcdc_panel_ops = { + .enable_backlight = tilcdc_panel_enable_backlight, + .set_backlight = tilcdc_panel_set_backlight, + .get_display_timing = tilcdc_panel_get_display_timing, +}; + +static const struct udevice_id tilcdc_panel_ids[] = { + {.compatible = "ti,tilcdc,panel"}, + {} +}; + +U_BOOT_DRIVER(tilcdc_panel) = { + .name = "tilcdc_panel", + .id = UCLASS_PANEL, + .of_match = tilcdc_panel_ids, + .ops = &tilcdc_panel_ops, + .of_to_plat = tilcdc_panel_of_to_plat, + .probe = tilcdc_panel_probe, + .remove = tilcdc_panel_remove, + .priv_auto = sizeof(struct tilcdc_panel_priv), +}; diff --git a/drivers/video/ti/tilcdc-panel.h b/drivers/video/ti/tilcdc-panel.h new file mode 100644 index 00000000000..6bcfbf8a8b4 --- /dev/null +++ b/drivers/video/ti/tilcdc-panel.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Dario Binacchi + */ + +#ifndef _TILCDC_PANEL_H +#define _TILCDC_PANEL_H + +#include "tilcdc.h" + +int tilcdc_panel_get_display_info(struct udevice *dev, + struct tilcdc_panel_info *info); + +#endif /* _TILCDC_PANEL_H */ diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c new file mode 100644 index 00000000000..88043fc18c5 --- /dev/null +++ b/drivers/video/ti/tilcdc.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tilcdc.h" +#include "tilcdc-panel.h" + +#define LCDC_FMAX 200000000 + +/* LCD Control Register */ +#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8) +#define LCDC_CTRL_RASTER_MODE BIT(0) +#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8) +/* LCD Clock Enable Register */ +#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0) +#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1) +#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2) +/* LCD DMA Control Register */ +#define LCDC_DMA_CTRL_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4) +#define LCDC_DMA_CTRL_BURST_1 0x0 +#define LCDC_DMA_CTRL_BURST_2 0x1 +#define LCDC_DMA_CTRL_BURST_4 0x2 +#define LCDC_DMA_CTRL_BURST_8 0x3 +#define LCDC_DMA_CTRL_BURST_16 0x4 +#define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8) +/* LCD Timing_0 Register */ +#define LCDC_RASTER_TIMING_0_HORMSB(x) ((((x) - 1) & BIT(10)) >> 7) +#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4) +#define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10) +#define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16) +#define LCDC_RASTER_TIMING_0_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24) +/* LCD Timing_1 Register */ +#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0)) +#define LCDC_RASTER_TIMING_1_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10) +#define LCDC_RASTER_TIMING_1_VFP(x) (((x) & GENMASK(7, 0)) << 16) +#define LCDC_RASTER_TIMING_1_VBP(x) (((x) & GENMASK(7, 0)) << 24) +/* LCD Timing_2 Register */ +#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8) +#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4) +#define LCDC_RASTER_TIMING_2_ACB(x) (((x) & GENMASK(7, 0)) << 8) +#define LCDC_RASTER_TIMING_2_ACBI(x) (((x) & GENMASK(3, 0)) << 16) +#define LCDC_RASTER_TIMING_2_VSYNC_INVERT BIT(20) +#define LCDC_RASTER_TIMING_2_HSYNC_INVERT BIT(21) +#define LCDC_RASTER_TIMING_2_PXCLK_INVERT BIT(22) +#define LCDC_RASTER_TIMING_2_DE_INVERT BIT(23) +#define LCDC_RASTER_TIMING_2_HSVS_RISEFALL BIT(24) +#define LCDC_RASTER_TIMING_2_HSVS_CONTROL BIT(25) +#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16) +#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21) +/* LCD Raster Ctrl Register */ +#define LCDC_RASTER_CTRL_ENABLE BIT(0) +#define LCDC_RASTER_CTRL_TFT_MODE BIT(7) +#define LCDC_RASTER_CTRL_DATA_ORDER BIT(8) +#define LCDC_RASTER_CTRL_REQDLY(x) (((x) & GENMASK(7, 0)) << 12) +#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20) +#define LCDC_RASTER_CTRL_TFT_ALT_ENABLE BIT(23) +#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25) +#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26) + +enum { + LCDC_MAX_WIDTH = 2048, + LCDC_MAX_HEIGHT = 2048, + LCDC_MAX_LOG2_BPP = VIDEO_BPP32, +}; + +struct tilcdc_regs { + u32 pid; + u32 ctrl; + u32 gap0; + u32 lidd_ctrl; + u32 lidd_cs0_conf; + u32 lidd_cs0_addr; + u32 lidd_cs0_data; + u32 lidd_cs1_conf; + u32 lidd_cs1_addr; + u32 lidd_cs1_data; + u32 raster_ctrl; + u32 raster_timing0; + u32 raster_timing1; + u32 raster_timing2; + u32 raster_subpanel; + u32 raster_subpanel2; + u32 lcddma_ctrl; + u32 lcddma_fb0_base; + u32 lcddma_fb0_ceiling; + u32 lcddma_fb1_base; + u32 lcddma_fb1_ceiling; + u32 sysconfig; + u32 irqstatus_raw; + u32 irqstatus; + u32 irqenable_set; + u32 irqenable_clear; + u32 gap1; + u32 clkc_enable; + u32 clkc_reset; +}; + +struct tilcdc_priv { + struct tilcdc_regs *regs; + struct clk gclk; + struct clk dpll_m2_clk; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate) +{ + struct tilcdc_priv *priv = dev_get_priv(dev); + struct tilcdc_regs *regs = priv->regs; + ulong mult_rate, mult_round_rate, best_err, err; + u32 v; + int div, i; + + best_err = rate; + div = 0; + for (i = 2; i <= 255; i++) { + mult_rate = rate * i; + mult_round_rate = clk_round_rate(&priv->gclk, mult_rate); + if (IS_ERR_VALUE(mult_round_rate)) + return mult_round_rate; + + err = mult_rate - mult_round_rate; + if (err < best_err) { + best_err = err; + div = i; + if (err == 0) + break; + } + } + + if (div == 0) { + dev_err(dev, "failed to find a divisor\n"); + return -EFAULT; + } + + mult_rate = clk_set_rate(&priv->gclk, rate * div); + v = readl(®s->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK; + v |= LCDC_CTRL_CLK_DIVISOR(div); + writel(v, ®s->ctrl); + rate = mult_rate / div; + dev_dbg(dev, "rate=%ld, div=%d, err=%ld\n", rate, div, err); + return rate; +} + +static int tilcdc_remove(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + struct tilcdc_priv *priv = dev_get_priv(dev); + + uc_plat->base -= 0x20; + uc_plat->size += 0x20; + clk_release_all(&priv->gclk, 1); + clk_release_all(&priv->dpll_m2_clk, 1); + return 0; +} + +static int tilcdc_probe(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct tilcdc_priv *priv = dev_get_priv(dev); + struct tilcdc_regs *regs = priv->regs; + struct udevice *panel, *clk_dev; + struct tilcdc_panel_info info; + struct display_timing timing; + ulong rate; + u32 reg; + int err; + + /* Before relocation we don't need to do anything */ + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + err = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (err) { + dev_err(dev, "failed to get panel\n"); + return err; + } + + err = panel_get_display_timing(panel, &timing); + if (err) { + dev_err(dev, "failed to get display timing\n"); + return err; + } + + if (timing.pixelclock.typ > (LCDC_FMAX / 2)) { + dev_err(dev, "invalid display clock-frequency: %d Hz\n", + timing.pixelclock.typ); + return -EINVAL; + } + + if (timing.hactive.typ > LCDC_MAX_WIDTH) + timing.hactive.typ = LCDC_MAX_WIDTH; + + if (timing.vactive.typ > LCDC_MAX_HEIGHT) + timing.vactive.typ = LCDC_MAX_HEIGHT; + + err = tilcdc_panel_get_display_info(panel, &info); + if (err) { + dev_err(dev, "failed to get panel info\n"); + return err; + } + + switch (info.bpp) { + case 16: + case 24: + case 32: + break; + default: + dev_err(dev, "invalid seting, bpp: %d\n", info.bpp); + return -EINVAL; + } + + switch (info.dma_burst_sz) { + case 1: + case 2: + case 4: + case 8: + case 16: + break; + default: + dev_err(dev, "invalid setting, dma-burst-sz: %d\n", + info.dma_burst_sz); + return -EINVAL; + } + + err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev); + if (err) { + dev_err(dev, "failed to get lcd_gclk device\n"); + return err; + } + + err = clk_request(clk_dev, &priv->gclk); + if (err) { + dev_err(dev, "failed to get %s clock\n", clk_dev->name); + return err; + } + + rate = tilcdc_set_pixel_clk_rate(dev, timing.pixelclock.typ); + if (IS_ERR_VALUE(rate)) { + dev_err(dev, "failed to set pixel clock rate\n"); + return rate; + } + + err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4", + &clk_dev); + if (err) { + dev_err(dev, "failed to get dpll_disp_m2 clock device\n"); + return err; + } + + err = clk_request(clk_dev, &priv->dpll_m2_clk); + if (err) { + dev_err(dev, "failed to get %s clock\n", clk_dev->name); + return err; + } + + err = clk_set_parent(&priv->gclk, &priv->dpll_m2_clk); + if (err) { + dev_err(dev, "failed to set %s clock as %s's parent\n", + priv->dpll_m2_clk.dev->name, priv->gclk.dev->name); + return err; + } + + /* palette default entry */ + memset((void *)uc_plat->base, 0, 0x20); + *(unsigned int *)uc_plat->base = 0x4000; + /* point fb behind palette */ + uc_plat->base += 0x20; + uc_plat->size -= 0x20; + + writel(LCDC_CLKC_ENABLE_CORECLKEN | LCDC_CLKC_ENABLE_LIDDCLKEN | + LCDC_CLKC_ENABLE_DMACLKEN, ®s->clkc_enable); + writel(0, ®s->raster_ctrl); + + reg = readl(®s->ctrl) & LCDC_CTRL_CLK_DIVISOR_MASK; + reg |= LCDC_CTRL_RASTER_MODE; + writel(reg, ®s->ctrl); + + reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3; + reg += uc_plat->base; + writel(uc_plat->base, ®s->lcddma_fb0_base); + writel(reg, ®s->lcddma_fb0_ceiling); + writel(uc_plat->base, ®s->lcddma_fb1_base); + writel(reg, ®s->lcddma_fb1_ceiling); + + reg = LCDC_DMA_CTRL_FIFO_TH(info.fifo_th); + switch (info.dma_burst_sz) { + case 1: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_1); + break; + case 2: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_2); + break; + case 4: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_4); + break; + case 8: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_8); + break; + case 16: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16); + break; + } + + writel(reg, ®s->lcddma_ctrl); + + writel(LCDC_RASTER_TIMING_0_HORLSB(timing.hactive.typ) | + LCDC_RASTER_TIMING_0_HORMSB(timing.hactive.typ) | + LCDC_RASTER_TIMING_0_HFPLSB(timing.hfront_porch.typ) | + LCDC_RASTER_TIMING_0_HBPLSB(timing.hback_porch.typ) | + LCDC_RASTER_TIMING_0_HSWLSB(timing.hsync_len.typ), + ®s->raster_timing0); + + writel(LCDC_RASTER_TIMING_1_VBP(timing.vback_porch.typ) | + LCDC_RASTER_TIMING_1_VFP(timing.vfront_porch.typ) | + LCDC_RASTER_TIMING_1_VSW(timing.vsync_len.typ) | + LCDC_RASTER_TIMING_1_VERLSB(timing.vactive.typ), + ®s->raster_timing1); + + reg = LCDC_RASTER_TIMING_2_ACB(info.ac_bias) | + LCDC_RASTER_TIMING_2_ACBI(info.ac_bias_intrpt) | + LCDC_RASTER_TIMING_2_HSWMSB(timing.hsync_len.typ) | + LCDC_RASTER_TIMING_2_VERMSB(timing.vactive.typ) | + LCDC_RASTER_TIMING_2_HBPMSB(timing.hback_porch.typ) | + LCDC_RASTER_TIMING_2_HFPMSB(timing.hfront_porch.typ); + + if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW) + reg |= LCDC_RASTER_TIMING_2_VSYNC_INVERT; + + if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) + reg |= LCDC_RASTER_TIMING_2_HSYNC_INVERT; + + if (info.invert_pxl_clk) + reg |= LCDC_RASTER_TIMING_2_PXCLK_INVERT; + + if (info.sync_edge) + reg |= LCDC_RASTER_TIMING_2_HSVS_RISEFALL; + + if (info.sync_ctrl) + reg |= LCDC_RASTER_TIMING_2_HSVS_CONTROL; + + writel(reg, ®s->raster_timing2); + + reg = LCDC_RASTER_CTRL_PALMODE_RAWDATA | LCDC_RASTER_CTRL_TFT_MODE | + LCDC_RASTER_CTRL_ENABLE | LCDC_RASTER_CTRL_REQDLY(info.fdd); + + if (info.tft_alt_mode) + reg |= LCDC_RASTER_CTRL_TFT_ALT_ENABLE; + + if (info.bpp == 24) + reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE; + else if (info.bpp == 32) + reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE | + LCDC_RASTER_CTRL_TFT_24BPP_UNPACK; + + if (info.raster_order) + reg |= LCDC_RASTER_CTRL_DATA_ORDER; + + writel(reg, ®s->raster_ctrl); + + uc_priv->xsize = timing.hactive.typ; + uc_priv->ysize = timing.vactive.typ; + uc_priv->bpix = log_2_n_round_up(info.bpp); + + err = panel_enable_backlight(panel); + if (err) { + dev_err(dev, "failed to enable panel backlight\n"); + return err; + } + + return 0; +} + +static int tilcdc_of_to_plat(struct udevice *dev) +{ + struct tilcdc_priv *priv = dev_get_priv(dev); + + priv->regs = (struct tilcdc_regs *)dev_read_addr(dev); + if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get base address\n"); + return -EINVAL; + } + + dev_dbg(dev, "LCD: base address=0x%x\n", (unsigned int)priv->regs); + return 0; +} + +static int tilcdc_bind(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + uc_plat->size = ((LCDC_MAX_WIDTH * LCDC_MAX_HEIGHT * + (1 << LCDC_MAX_LOG2_BPP)) >> 3) + 0x20; + + dev_dbg(dev, "frame buffer size 0x%x\n", uc_plat->size); + return 0; +} + +static const struct udevice_id tilcdc_ids[] = { + {.compatible = "ti,am33xx-tilcdc"}, + {} +}; + +U_BOOT_DRIVER(tilcdc) = { + .name = "tilcdc", + .id = UCLASS_VIDEO, + .of_match = tilcdc_ids, + .bind = tilcdc_bind, + .of_to_plat = tilcdc_of_to_plat, + .probe = tilcdc_probe, + .remove = tilcdc_remove, + .priv_auto = sizeof(struct tilcdc_priv) +}; diff --git a/drivers/video/ti/tilcdc.h b/drivers/video/ti/tilcdc.h new file mode 100644 index 00000000000..2645921df65 --- /dev/null +++ b/drivers/video/ti/tilcdc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Dario Binacchi + */ + +#ifndef _TILCDC_H +#define _TILCDC_H + +/** + * tilcdc_panel_info: Panel parameters + * + * @ac_bias: AC Bias Pin Frequency + * @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt + * @dma_burst_sz: DMA burst size + * @bpp: Bits per pixel + * @fdd: FIFO DMA Request Delay + * @tft_alt_mode: TFT Alternative Signal Mapping (Only for active) + * @invert_pxl_clk: Invert pixel clock + * @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling + * @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore + * @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most + * @fifo_th: DMA FIFO threshold + */ +struct tilcdc_panel_info { + u32 ac_bias; + u32 ac_bias_intrpt; + u32 dma_burst_sz; + u32 bpp; + u32 fdd; + bool tft_alt_mode; + bool invert_pxl_clk; + u32 sync_edge; + u32 sync_ctrl; + u32 raster_order; + u32 fifo_th; +}; + +#endif /* _TILCDC_H */ From 0347cc7732703bdf94bba5ce8a157c2174f01067 Mon Sep 17 00:00:00 2001 From: Nikhil M Jain Date: Tue, 31 Jan 2023 15:35:14 +0530 Subject: [PATCH 2/7] drivers: core: ofnode: Add panel timing decode. ofnode_decode_display_timing supports reading timing parameters from subnode of display-timings node, for displays supporting multiple resolution, in case if a display supports single resolution, it fails reading directly from display-timings node, to support it ofnode_decode_panel_timing is added. Signed-off-by: Nikhil M Jain Reviewed-by: Simon Glass --- drivers/core/ofnode.c | 47 +++++++++++++++++++++++++++++++++++++++++++ drivers/core/read.c | 6 ++++++ include/dm/ofnode.h | 12 +++++++++++ include/dm/read.h | 20 ++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 4d56b1a7675..d08578e9c4f 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -991,6 +991,53 @@ int ofnode_decode_display_timing(ofnode parent, int index, return ret; } +int ofnode_decode_panel_timing(ofnode parent, + struct display_timing *dt) +{ + ofnode timings; + u32 val = 0; + int ret = 0; + + timings = ofnode_find_subnode(parent, "panel-timings"); + if (!ofnode_valid(timings)) + return -EINVAL; + memset(dt, 0, sizeof(*dt)); + ret |= decode_timing_property(timings, "hback-porch", &dt->hback_porch); + ret |= decode_timing_property(timings, "hfront-porch", &dt->hfront_porch); + ret |= decode_timing_property(timings, "hactive", &dt->hactive); + ret |= decode_timing_property(timings, "hsync-len", &dt->hsync_len); + ret |= decode_timing_property(timings, "vback-porch", &dt->vback_porch); + ret |= decode_timing_property(timings, "vfront-porch", &dt->vfront_porch); + ret |= decode_timing_property(timings, "vactive", &dt->vactive); + ret |= decode_timing_property(timings, "vsync-len", &dt->vsync_len); + ret |= decode_timing_property(timings, "clock-frequency", &dt->pixelclock); + dt->flags = 0; + if (!ofnode_read_u32(timings, "vsync-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH : + DISPLAY_FLAGS_VSYNC_LOW; + } + if (!ofnode_read_u32(timings, "hsync-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH : + DISPLAY_FLAGS_HSYNC_LOW; + } + if (!ofnode_read_u32(timings, "de-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH : + DISPLAY_FLAGS_DE_LOW; + } + if (!ofnode_read_u32(timings, "pixelclk-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE : + DISPLAY_FLAGS_PIXDATA_NEGEDGE; + } + if (ofnode_read_bool(timings, "interlaced")) + dt->flags |= DISPLAY_FLAGS_INTERLACED; + if (ofnode_read_bool(timings, "doublescan")) + dt->flags |= DISPLAY_FLAGS_DOUBLESCAN; + if (ofnode_read_bool(timings, "doubleclk")) + dt->flags |= DISPLAY_FLAGS_DOUBLECLK; + + return ret; +} + const void *ofnode_get_property(ofnode node, const char *propname, int *lenp) { if (ofnode_is_np(node)) diff --git a/drivers/core/read.c b/drivers/core/read.c index 3e5fea87d84..e0543bbad59 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -420,6 +420,12 @@ int dev_decode_display_timing(const struct udevice *dev, int index, return ofnode_decode_display_timing(dev_ofnode(dev), index, config); } +int dev_decode_panel_timing(const struct udevice *dev, + struct display_timing *config) +{ + return ofnode_decode_panel_timing(dev_ofnode(dev), config); +} + ofnode dev_get_phy_node(const struct udevice *dev) { return ofnode_get_phy_node(dev_ofnode(dev)); diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index fa9865602d8..3f6b0843c58 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -974,6 +974,18 @@ struct display_timing; int ofnode_decode_display_timing(ofnode node, int index, struct display_timing *config); +/** + * ofnode_decode_panel_timing() - decode display timings + * + * Decode panel timings from the supplied 'panel-timings' node. + * + * @node: 'display-timing' node containing the timing subnodes + * @config: Place to put timings + * Return: 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int ofnode_decode_panel_timing(ofnode node, + struct display_timing *config); + /** * ofnode_get_property() - get a pointer to the value of a node property * diff --git a/include/dm/read.h b/include/dm/read.h index cc4f16196fd..56ac076c9f1 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -784,6 +784,20 @@ int dev_read_pci_bus_range(const struct udevice *dev, struct resource *res); int dev_decode_display_timing(const struct udevice *dev, int index, struct display_timing *config); +/** + * dev_decode_panel_timing() - decode panel timings + * + * Decode display timings from the supplied 'panel-timings' node. + * + * @dev: device to read DT display timings from. The node linked to the device + * contains a child node called 'display-timings' which in turn contains + * one or more display timing nodes. + * @config: place to put timings + * Return: 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int dev_decode_panel_timing(const struct udevice *dev, + struct display_timing *config); + /** * dev_get_phy_node() - Get PHY node for a MAC (if not fixed-link) * @@ -1183,6 +1197,12 @@ static inline int dev_decode_display_timing(const struct udevice *dev, return ofnode_decode_display_timing(dev_ofnode(dev), index, config); } +static inline int dev_decode_panel_timing(const struct udevice *dev, + struct display_timing *config) +{ + return ofnode_decode_panel_timing(dev_ofnode(dev), config); +} + static inline ofnode dev_get_phy_node(const struct udevice *dev) { return ofnode_get_phy_node(dev_ofnode(dev)); From 2f3d6a42300616630b3c9c1e52cb6e58da390393 Mon Sep 17 00:00:00 2001 From: Nikhil M Jain Date: Tue, 31 Jan 2023 15:35:15 +0530 Subject: [PATCH 3/7] test: dm: test-fdt: Add decode_panel_timing test To test decode_panel_timing add a panel-timings node and a DM test for decode panel timingd by matching the panel timing node parameters. Signed-off-by: Nikhil M Jain Reviewed-by: Simon Glass --- arch/sandbox/dts/test.dts | 18 ++++++++++++++++++ test/dm/test-fdt.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8c059276702..f98f0152ee8 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -342,6 +342,24 @@ vsync-len = <13>; }; }; + panel-timings { + clock-frequency = <6500000>; + hactive = <240>; + vactive = <320>; + hfront-porch = <6>; + hback-porch = <7>; + hsync-len = <1>; + vback-porch = <5>; + vfront-porch = <8>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + interlaced; + doublescan; + doubleclk; + }; }; junk { diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 7cd2d046122..1d2af94f568 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1157,6 +1158,41 @@ static int dm_test_decode_display_timing(struct unit_test_state *uts) } DM_TEST(dm_test_decode_display_timing, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +/* Test dev_decode_panel_timing() */ +static int dm_test_decode_panel_timing(struct unit_test_state *uts) +{ + struct udevice *dev; + struct display_timing timing; + + ut_assertok(uclass_first_device_err(UCLASS_TEST_FDT, &dev)); + ut_asserteq_str("a-test", dev->name); + + ut_assertok(dev_decode_panel_timing(dev, &timing)); + ut_assert(timing.hactive.typ == 240); + ut_assert(timing.hback_porch.typ == 7); + ut_assert(timing.hfront_porch.typ == 6); + ut_assert(timing.hsync_len.typ == 1); + ut_assert(timing.vactive.typ == 320); + ut_assert(timing.vback_porch.typ == 5); + ut_assert(timing.vfront_porch.typ == 8); + ut_assert(timing.vsync_len.typ == 2); + ut_assert(timing.pixelclock.typ == 6500000); + ut_assert(timing.flags & DISPLAY_FLAGS_HSYNC_HIGH); + ut_assert(!(timing.flags & DISPLAY_FLAGS_HSYNC_LOW)); + ut_assert(!(timing.flags & DISPLAY_FLAGS_VSYNC_HIGH)); + ut_assert(timing.flags & DISPLAY_FLAGS_VSYNC_LOW); + ut_assert(timing.flags & DISPLAY_FLAGS_DE_HIGH); + ut_assert(!(timing.flags & DISPLAY_FLAGS_DE_LOW)); + ut_assert(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE); + ut_assert(!(timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)); + ut_assert(timing.flags & DISPLAY_FLAGS_INTERLACED); + ut_assert(timing.flags & DISPLAY_FLAGS_DOUBLESCAN); + ut_assert(timing.flags & DISPLAY_FLAGS_DOUBLECLK); + + return 0; +} +DM_TEST(dm_test_decode_panel_timing, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + /* Test read_resourcee() */ static int dm_test_read_resource(struct unit_test_state *uts) { From 3ebe3c703bf549c740f5bcc08289c2bab6aca1ca Mon Sep 17 00:00:00 2001 From: Nikhil M Jain Date: Tue, 31 Jan 2023 15:35:16 +0530 Subject: [PATCH 4/7] drivers: video: simple_panel: make simple panel independent of backlight This patch updates the necessary Kconfigs to make simple panel driver independent of backlight driver and compiling backlight related code in simple-panel driver conditionally to when user has set CONFIG_BACKLIGHT. Signed-off-by: Nikhil M Jain Reviewed-by: Simon Glass --- drivers/video/simple_panel.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index c8f7022ea63..91c91ee75d8 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -63,12 +63,15 @@ static int simple_panel_of_to_plat(struct udevice *dev) return ret; } } + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, - "backlight", &priv->backlight); + "backlight", &priv->backlight); if (ret) { debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); - return log_ret(ret); + if (ret != -ENOENT) + return log_ret(ret); } + ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, GPIOD_IS_OUT); if (ret) { From 5f9f816bb8e474709d7b81aa27bd73e542fe299a Mon Sep 17 00:00:00 2001 From: Nikhil M Jain Date: Tue, 31 Jan 2023 15:35:17 +0530 Subject: [PATCH 5/7] drivers: video: tidss: TIDSS video driver support for AM62x Added tidss video driver support which enables display on oldi panel using AM62x, it creates a simple pipeline framebuffer==>vidl1==>ovr1==>vp1==>oldi_panel and calculates clock rates for panel from panel node in device tree. To compile TIDSS when user sets CONFIG_VIDEO_TIDSS add rule in Makefile. Include tidss folder location in Kconfig. TIDSS is ported from linux kernel version 5.10.145 Signed-off-by: Nikhil M Jain --- MAINTAINERS | 1 + drivers/video/Kconfig | 2 + drivers/video/Makefile | 1 + drivers/video/tidss/Kconfig | 18 + drivers/video/tidss/Makefile | 12 + drivers/video/tidss/tidss_drv.c | 943 +++++++++++++++++++++++++++++++ drivers/video/tidss/tidss_drv.h | 137 +++++ drivers/video/tidss/tidss_regs.h | 292 ++++++++++ 8 files changed, 1406 insertions(+) create mode 100644 drivers/video/tidss/Kconfig create mode 100644 drivers/video/tidss/Makefile create mode 100644 drivers/video/tidss/tidss_drv.c create mode 100644 drivers/video/tidss/tidss_drv.h create mode 100644 drivers/video/tidss/tidss_regs.h diff --git a/MAINTAINERS b/MAINTAINERS index 3e8e193ecc8..d9c959b94de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -646,6 +646,7 @@ F: drivers/soc/ti/ F: drivers/sysreset/sysreset-ti-sci.c F: drivers/thermal/ti-bandgap.c F: drivers/timer/omap-timer.c +F: drivers/video/tidss/ F: drivers/watchdog/omap_wdt.c F: include/linux/pruss_driver.h F: include/linux/soc/ti/ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index e08b7a77dd2..2a76d19cc8e 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -636,6 +636,8 @@ config VIDEO_SANDBOX_SDL source "drivers/video/stm32/Kconfig" +source "drivers/video/tidss/Kconfig" + config VIDEO_TEGRA20 bool "Enable LCD support on Tegra20" depends on OF_CONTROL diff --git a/drivers/video/Makefile b/drivers/video/Makefile index b359b078405..75c789a9570 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -26,6 +26,7 @@ obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ +obj-${CONFIG_VIDEO_TIDSS} += tidss/ obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig new file mode 100644 index 00000000000..2a5e56ea4ee --- /dev/null +++ b/drivers/video/tidss/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Nikhil M Jain, n-jain1@ti.com +# +# based on the linux tidss driver, which is +# +# (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ +# Author: Tomi Valkeinen + +menuconfig VIDEO_TIDSS + bool "Enable TIDSS video support" + depends on VIDEO + help + TIDSS supports video output options LVDS and + DPI . This option enables these supports which can be used on + devices which have OLDI or HDMI display connected. + diff --git a/drivers/video/tidss/Makefile b/drivers/video/tidss/Makefile new file mode 100644 index 00000000000..f4f8c6c470a --- /dev/null +++ b/drivers/video/tidss/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Nikhil M Jain, n-jain1@ti.com +# +# based on the linux tidss driver, which is +# +# (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ +# Author: Tomi Valkeinen + + +obj-${CONFIG_VIDEO_TIDSS} = tidss_drv.o diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c new file mode 100644 index 00000000000..078e3e82e3a --- /dev/null +++ b/drivers/video/tidss/tidss_drv.c @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Nikhil M Jain, n-jain1@ti.com + * + * based on the linux tidss driver, which is + * + * (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Author: Tomi Valkeinen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "tidss_drv.h" +#include "tidss_regs.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Panel parameters */ +enum { + LCD_MAX_WIDTH = 1920, + LCD_MAX_HEIGHT = 1200, + LCD_MAX_LOG2_BPP = VIDEO_BPP32, +}; + +static const u16 *dss_common_regmap; + +static const u16 tidss_am62x_common_regs[DSS_COMMON_REG_TABLE_LEN] = { + [DSS_REVISION_OFF] = 0x4, + [DSS_SYSCONFIG_OFF] = 0x8, + [DSS_SYSSTATUS_OFF] = 0x20, + [DSS_IRQ_EOI_OFF] = 0x24, + [DSS_IRQSTATUS_RAW_OFF] = 0x28, + [DSS_IRQSTATUS_OFF] = 0x2c, + [DSS_IRQENABLE_SET_OFF] = 0x30, + [DSS_IRQENABLE_CLR_OFF] = 0x40, + [DSS_VID_IRQENABLE_OFF] = 0x44, + [DSS_VID_IRQSTATUS_OFF] = 0x58, + [DSS_VP_IRQENABLE_OFF] = 0x70, + [DSS_VP_IRQSTATUS_OFF] = 0x7c, + + [WB_IRQENABLE_OFF] = 0x88, + [WB_IRQSTATUS_OFF] = 0x8c, + + [DSS_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x90, + [DSS_GLOBAL_OUTPUT_ENABLE_OFF] = 0x94, + [DSS_GLOBAL_BUFFER_OFF] = 0x98, + [DSS_CBA_CFG_OFF] = 0x9c, + [DSS_DBG_CONTROL_OFF] = 0xa0, + [DSS_DBG_STATUS_OFF] = 0xa4, + [DSS_CLKGATING_DISABLE_OFF] = 0xa8, + [DSS_SECURE_DISABLE_OFF] = 0xac, +}; + +/* TIDSS AM62x Features */ +const struct dss_features dss_am625_feats = { + .max_pclk_khz = { + [DSS_VP_DPI] = 165000, + [DSS_VP_OLDI] = 165000, + }, + + .subrev = DSS_AM625, + + .common = "common", + .common_regs = tidss_am62x_common_regs, + + .num_vps = 2, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + .vp_bus_type = { DSS_VP_OLDI, DSS_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vidl1", "vid1" }, + .vid_lite = { true, false }, + .vid_order = { 1, 0 }, +}; + +/* Wrapper functions to write and read TI_DSS registers */ +static void dss_write(struct tidss_drv_priv *priv, u16 reg, u32 val) +{ + writel(val, priv->base_common + reg); +} + +static u32 dss_read(struct tidss_drv_priv *priv, u16 reg) +{ + return readl(priv->base_common + reg); +} + +static void dss_vid_write(struct tidss_drv_priv *priv, u32 hw_plane, u16 reg, u32 val) +{ + void __iomem *base = priv->base_vid[hw_plane]; + + writel(val, base + reg); +} + +static u32 dss_vid_read(struct tidss_drv_priv *priv, u32 hw_plane, u16 reg) +{ + void __iomem *base = priv->base_vid[hw_plane]; + + return readl(base + reg); +} + +static void dss_ovr_write(struct tidss_drv_priv *priv, u32 hw_videoport, + u16 reg, u32 val) +{ + void __iomem *base = priv->base_ovr[hw_videoport]; + + writel(val, base + reg); +} + +static u32 dss_ovr_read(struct tidss_drv_priv *priv, u32 hw_videoport, u16 reg) +{ + void __iomem *base = priv->base_ovr[hw_videoport]; + + return readl(base + reg); +} + +static void dss_vp_write(struct tidss_drv_priv *priv, u32 hw_videoport, + u16 reg, u32 val) +{ + void __iomem *base = priv->base_vp[hw_videoport]; + + writel(val, base + reg); +} + +static u32 dss_vp_read(struct tidss_drv_priv *priv, u32 hw_videoport, u16 reg) +{ + void __iomem *base = priv->base_vp[hw_videoport]; + + return readl(base + reg); +} + +/* generate mask on a register */ +static u32 FLD_MASK(u32 start, u32 end) +{ + return ((1 << (start - end + 1)) - 1) << end; +} + +/* set the given val in specified range */ +static u32 FLD_VAL(u32 val, u32 start, u32 end) +{ + return (val << end) & FLD_MASK(start, end); +} + +/* return the value in the specified range */ +static u32 FLD_GET(u32 val, u32 start, u32 end) +{ + return (val & FLD_MASK(start, end)) >> end; +} + +/* modify the value of the specified range */ +static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) +{ + return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); +} + +/* read and modify common register region of DSS*/ +__maybe_unused +static u32 REG_GET(struct tidss_drv_priv *priv, u32 idx, u32 start, u32 end) +{ + return FLD_GET(dss_read(priv, idx), start, end); +} + +static void REG_FLD_MOD(struct tidss_drv_priv *priv, u32 idx, u32 val, + u32 start, u32 end) +{ + dss_write(priv, idx, FLD_MOD(dss_read(priv, idx), val, + start, end)); +} + +/* read and modify planes vid1 and vid2 register of DSS*/ +static u32 VID_REG_GET(struct tidss_drv_priv *priv, u32 hw_plane, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dss_vid_read(priv, hw_plane, idx), start, end); +} + +static void VID_REG_FLD_MOD(struct tidss_drv_priv *priv, u32 hw_plane, u32 idx, + u32 val, u32 start, u32 end) +{ + dss_vid_write(priv, hw_plane, idx, + FLD_MOD(dss_vid_read(priv, hw_plane, idx), + val, start, end)); +} + +/* read and modify port vid1 and vid2 registers of DSS*/ +__maybe_unused +static u32 VP_REG_GET(struct tidss_drv_priv *priv, u32 vp, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dss_vp_read(priv, vp, idx), start, end); +} + +static void VP_REG_FLD_MOD(struct tidss_drv_priv *priv, u32 vp, u32 idx, u32 val, + u32 start, u32 end) +{ + dss_vp_write(priv, vp, idx, FLD_MOD(dss_vp_read(priv, vp, idx), + val, start, end)); +} + +/* read and modify overlay ovr1 and ovr2 registers of DSS*/ +__maybe_unused +static u32 OVR_REG_GET(struct tidss_drv_priv *priv, u32 ovr, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dss_ovr_read(priv, ovr, idx), start, end); +} + +static void OVR_REG_FLD_MOD(struct tidss_drv_priv *priv, u32 ovr, u32 idx, + u32 val, u32 start, u32 end) +{ + dss_ovr_write(priv, ovr, idx, FLD_MOD(dss_ovr_read(priv, ovr, idx), + val, start, end)); +} + +static void dss_oldi_tx_power(struct tidss_drv_priv *priv, bool power) +{ + u32 val; + + if (WARN_ON(!priv->oldi_io_ctrl)) + return; + + if (priv->feat->subrev == DSS_AM625) { + if (power) { + switch (priv->oldi_mode) { + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* Power down OLDI TX 1 */ + val = OLDI1_PWRDN_TX; + break; + case OLDI_DUAL_LINK: + /* No Power down */ + val = 0; + break; + default: + /* Power down both the OLDI TXes */ + val = OLDI_BANDGAP_PWR | OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + break; + } + } else { + val = OLDI_BANDGAP_PWR | OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + } + regmap_update_bits(priv->oldi_io_ctrl, OLDI_PD_CTRL, + OLDI_BANDGAP_PWR | OLDI0_PWRDN_TX | OLDI1_PWRDN_TX, val); + } +} + +static void dss_set_num_datalines(struct tidss_drv_priv *priv, + u32 hw_videoport) +{ + int v; + u32 num_lines = priv->bus_format->data_width; + + switch (num_lines) { + case 12: + v = 0; break; + case 16: + v = 1; break; + case 18: + v = 2; break; + case 24: + v = 3; break; + case 30: + v = 4; break; + case 36: + v = 5; break; + default: + WARN_ON(1); + v = 3; + } + + VP_REG_FLD_MOD(priv, hw_videoport, DSS_VP_CONTROL, v, 10, 8); +} + +static void dss_enable_oldi(struct tidss_drv_priv *priv, u32 hw_videoport) +{ + u32 oldi_cfg = 0; + u32 oldi_reset_bit = BIT(5 + hw_videoport); + int count = 0; + + /* + * For the moment MASTERSLAVE, and SRC bits of DSS_VP_DSS_OLDI_CFG are + * set statically to 0. + */ + + if (priv->bus_format->data_width == 24) + oldi_cfg |= BIT(8); /* MSB */ + else if (priv->bus_format->data_width != 18) + dev_warn(priv->dev, "%s: %d port width not supported\n", + __func__, priv->bus_format->data_width); + + oldi_cfg |= BIT(7); /* DEPOL */ + + oldi_cfg = FLD_MOD(oldi_cfg, priv->bus_format->oldi_mode_reg_val, 3, 1); + + oldi_cfg |= BIT(12); /* SOFTRST */ + + oldi_cfg |= BIT(0); /* ENABLE */ + + switch (priv->oldi_mode) { + case OLDI_MODE_OFF: + oldi_cfg &= ~BIT(0); /* DISABLE */ + break; + + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* All configuration is done for this mode. */ + break; + + case OLDI_SINGLE_LINK_DUPLICATE_MODE: + oldi_cfg |= BIT(5); /* DUPLICATE MODE */ + break; + + case OLDI_DUAL_LINK: + oldi_cfg |= BIT(11); /* DUALMODESYNC */ + oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */ + break; + + default: + dev_warn(priv->dev, "%s: Incorrect oldi mode. Returning.\n", + __func__); + return; + } + + dss_vp_write(priv, hw_videoport, DSS_VP_DSS_OLDI_CFG, oldi_cfg); + + while (!(oldi_reset_bit & dss_read(priv, DSS_SYSSTATUS)) && + count < 10000) + count++; + + if (!(oldi_reset_bit & dss_read(priv, DSS_SYSSTATUS))) + dev_warn(priv->dev, "%s: timeout waiting OLDI reset done\n", + __func__); +} + +static const struct dss_color_lut dss_vp_gamma_default_lut[] = { + { .red = 0, .green = 0, .blue = 0, }, + { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, +}; + +static void dss_vp_write_gamma_table(struct tidss_drv_priv *priv, + u32 hw_videoport) +{ + u32 *table = priv->vp_data[hw_videoport].gamma_table; + u32 hwlen = priv->feat->vp_feat.color.gamma_size; + unsigned int i; + + dev_dbg(priv->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); + + for (i = 0; i < hwlen; ++i) { + u32 v = table[i]; + + v |= i << 24; + + dss_vp_write(priv, hw_videoport, DSS_VP_GAMMA_TABLE, v); + } +} + +static void dss_vp_set_gamma(struct tidss_drv_priv *priv, + u32 hw_videoport, const struct dss_color_lut *lut, + unsigned int length) +{ + u32 *table = priv->vp_data[hw_videoport].gamma_table; + u32 hwlen = priv->feat->vp_feat.color.gamma_size; + u32 hwbits; + unsigned int i; + + dev_dbg(priv->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", + __func__, hw_videoport, length, hwlen); + + if (priv->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) + hwbits = 10; + else + hwbits = 8; + + lut = dss_vp_gamma_default_lut; + length = ARRAY_SIZE(dss_vp_gamma_default_lut); + + for (i = 0; i < length - 1; ++i) { + unsigned int first = i * (hwlen - 1) / (length - 1); + unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); + unsigned int w = last - first; + u16 r, g, b; + unsigned int j; + + if (w == 0) + continue; + + for (j = 0; j <= w; j++) { + r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; + g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; + b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; + + r >>= 16 - hwbits; + g >>= 16 - hwbits; + b >>= 16 - hwbits; + + table[first + j] = (r << (hwbits * 2)) | + (g << hwbits) | b; + } + } + + dss_vp_write_gamma_table(priv, hw_videoport); +} + +void dss_vp_enable(struct tidss_drv_priv *priv, u32 hw_videoport, struct display_timing *timing) +{ + bool align, onoff, rf, ieo, ipc, ihs, ivs; + u32 hsw, hfp, hbp, vsw, vfp, vbp; + + dss_set_num_datalines(priv, hw_videoport); + + /* panel parameters to set clocks for video port*/ + hfp = timing->hfront_porch.typ; + hsw = timing->hsync_len.typ; + hbp = timing->hback_porch.typ; + vfp = timing->vfront_porch.typ; + vsw = timing->vsync_len.typ; + vbp = timing->vback_porch.typ; + + dss_vp_write(priv, hw_videoport, DSS_VP_TIMING_H, + FLD_VAL(hsw - 1, 7, 0) | + FLD_VAL(hfp - 1, 19, 8) | FLD_VAL(hbp - 1, 31, 20)); + + dss_vp_write(priv, hw_videoport, DSS_VP_TIMING_V, + FLD_VAL(vsw - 1, 7, 0) | + FLD_VAL(vfp, 19, 8) | FLD_VAL(vbp, 31, 20)); + + ivs = !!(timing->flags & (1 << 3)); + + ihs = !!(timing->flags & (1 << 1)); + + ieo = 0; + + ipc = 0; + + /* always use the 'rf' setting */ + onoff = true; + + rf = true; + + /* always use aligned syncs */ + align = true; + + /* always use DE_HIGH for OLDI */ + if (priv->feat->vp_bus_type[hw_videoport] == DSS_VP_OLDI) + ieo = false; + + dss_vp_write(priv, hw_videoport, DSS_VP_POL_FREQ, + FLD_VAL(align, 18, 18) | + FLD_VAL(onoff, 17, 17) | + FLD_VAL(rf, 16, 16) | + FLD_VAL(ieo, 15, 15) | + FLD_VAL(ipc, 14, 14) | + FLD_VAL(ihs, 13, 13) | + FLD_VAL(ivs, 12, 12)); + + dss_vp_write(priv, hw_videoport, DSS_VP_SIZE_SCREEN, + FLD_VAL(timing->hactive.typ - 1, 11, 0) | + FLD_VAL(timing->vactive.typ - 1, 27, 16)); + + VP_REG_FLD_MOD(priv, hw_videoport, DSS_VP_CONTROL, 1, 0, 0); +} + +enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; + +static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) +{ + u16 c12; + + c12 = c8 << 4; + + switch (mode) { + case C8_TO_C12_REPLICATE: + /* Copy c8 4 MSB to 4 LSB for full scale c12 */ + c12 |= c8 >> 4; + break; + case C8_TO_C12_MAX: + c12 |= 0xF; + break; + default: + case C8_TO_C12_MIN: + break; + } + + return c12; +} + +static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m) +{ + u8 a, r, g, b; + u64 v; + + a = (argb8888 >> 24) & 0xff; + r = (argb8888 >> 16) & 0xff; + g = (argb8888 >> 8) & 0xff; + b = (argb8888 >> 0) & 0xff; + + v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) | + ((u64)c8_to_c12(g, m) << 12) | (u64)c8_to_c12(b, m); + + return v; +} + +static void dss_vp_set_default_color(struct tidss_drv_priv *priv, + u32 hw_videoport, u32 default_color) +{ + u64 v; + + v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE); + dss_ovr_write(priv, hw_videoport, + DSS_OVR_DEFAULT_COLOR, v & 0xffffffff); + dss_ovr_write(priv, hw_videoport, + DSS_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff); +} + +int dss_vp_enable_clk(struct tidss_drv_priv *priv, u32 hw_videoport) +{ + int ret = clk_prepare_enable(&priv->vp_clk[hw_videoport]); + + if (ret) + dev_dbg(priv->dev, "%s: enabling clk failed: %d\n", __func__, + ret); + + return ret; +} + +void dss_vp_prepare(struct tidss_drv_priv *priv, u32 hw_videoport) +{ + dss_vp_set_gamma(priv, hw_videoport, NULL, 0); + dss_vp_set_default_color(priv, 0, 0); + + if (priv->feat->vp_bus_type[hw_videoport] == DSS_VP_OLDI) { + dss_oldi_tx_power(priv, true); + dss_enable_oldi(priv, hw_videoport); + } +} + +static +unsigned int dss_pclk_diff(unsigned long rate, unsigned long real_rate) +{ + int r = rate / 100, rr = real_rate / 100; + + return (unsigned int)(abs(((rr - r) * 100) / r)); +} + +int dss_vp_set_clk_rate(struct tidss_drv_priv *priv, u32 hw_videoport, + unsigned long rate) +{ + int r; + unsigned long new_rate; + + /* + * For AM625 OLDI video ports, the requested pixel clock needs to take into account the + * serial clock required for the serialization of DPI signals into LVDS signals. The + * incoming pixel clock on the OLDI video port gets divided by 7 whenever OLDI enable bit + * gets set. + */ + if (priv->feat->vp_bus_type[hw_videoport] == DSS_VP_OLDI && + priv->feat->subrev == DSS_AM625) + rate *= 7; + + r = clk_set_rate(&priv->vp_clk[hw_videoport], rate); + + new_rate = clk_get_rate(&priv->vp_clk[hw_videoport]); + + if (dss_pclk_diff(rate, new_rate) > 5) + dev_warn(priv->dev, + "vp%d: Clock rate %lu differs over 5%% from requested %lu\n", + hw_videoport, new_rate, rate); + + dev_dbg(priv->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", + hw_videoport, clk_get_rate(&priv->vp_clk[hw_videoport]), rate); + return 0; +} + +static void dss_ovr_set_plane(struct tidss_drv_priv *priv, + u32 hw_plane, u32 hw_ovr, + u32 x, u32 y, u32 layer) +{ + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + 0x1, 4, 1); + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + x, 17, 6); + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + y, 30, 19); +} + +void dss_ovr_enable_layer(struct tidss_drv_priv *priv, + u32 hw_ovr, u32 layer, bool enable) +{ + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + !!enable, 0, 0); +} + +static void dss_vid_csc_enable(struct tidss_drv_priv *priv, u32 hw_plane, + bool enable) +{ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, !!enable, 9, 9); +} + +int dss_plane_setup(struct tidss_drv_priv *priv, u32 hw_plane, u32 hw_videoport) +{ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, + priv->pixel_format, 6, 1); + + dss_vid_write(priv, hw_plane, DSS_VID_PICTURE_SIZE, + ((LCD_MAX_WIDTH - 1) | ((LCD_MAX_HEIGHT - 1) << 16))); + + dss_vid_csc_enable(priv, hw_plane, false); + + dss_vid_write(priv, hw_plane, DSS_VID_GLOBAL_ALPHA, 0xFF); + + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, 1, 28, 28); + return 0; +} + +int dss_plane_enable(struct tidss_drv_priv *priv, u32 hw_plane, bool enable) +{ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, !!enable, 0, 0); + + return 0; +} + +static u32 dss_vid_get_fifo_size(struct tidss_drv_priv *priv, u32 hw_plane) +{ + return VID_REG_GET(priv, hw_plane, DSS_VID_BUF_SIZE_STATUS, 15, 0); +} + +static void dss_vid_set_mflag_threshold(struct tidss_drv_priv *priv, + u32 hw_plane, u32 low, u32 high) +{ + dss_vid_write(priv, hw_plane, DSS_VID_MFLAG_THRESHOLD, + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static +void dss_vid_set_buf_threshold(struct tidss_drv_priv *priv, + u32 hw_plane, u32 low, u32 high) +{ + dss_vid_write(priv, hw_plane, DSS_VID_BUF_THRESHOLD, + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static void dss_plane_init(struct tidss_drv_priv *priv) +{ + unsigned int hw_plane; + u32 cba_lo_pri = 1; + u32 cba_hi_pri = 0; + + REG_FLD_MOD(priv, DSS_CBA_CFG, cba_lo_pri, 2, 0); + REG_FLD_MOD(priv, DSS_CBA_CFG, cba_hi_pri, 5, 3); + + /* MFLAG_CTRL = ENABLED */ + REG_FLD_MOD(priv, DSS_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + /* MFLAG_START = MFLAGNORMALSTARTMODE */ + REG_FLD_MOD(priv, DSS_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + + for (hw_plane = 0; hw_plane < priv->feat->num_planes; hw_plane++) { + u32 size = dss_vid_get_fifo_size(priv, hw_plane); + u32 thr_low, thr_high; + u32 mflag_low, mflag_high; + u32 preload; + + thr_high = size - 1; + thr_low = size / 2; + + mflag_high = size * 2 / 3; + mflag_low = size / 3; + + preload = thr_low; + + dev_dbg(priv->dev, + "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", + priv->feat->vid_name[hw_plane], + size, + thr_high, thr_low, + mflag_high, mflag_low, + preload); + + dss_vid_set_buf_threshold(priv, hw_plane, + thr_low, thr_high); + dss_vid_set_mflag_threshold(priv, hw_plane, + mflag_low, mflag_high); + + dss_vid_write(priv, hw_plane, DSS_VID_PRELOAD, preload); + + /* Prefech up to PRELOAD value */ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, 0, + 19, 19); + } +} + +static void dss_vp_init(struct tidss_drv_priv *priv) +{ + unsigned int i; + + /* Enable the gamma Shadow bit-field for all VPs*/ + for (i = 0; i < priv->feat->num_vps; i++) + VP_REG_FLD_MOD(priv, i, DSS_VP_CONFIG, 1, 2, 2); +} + +static int dss_init_am65x_oldi_io_ctrl(struct udevice *dev, + struct tidss_drv_priv *priv) +{ + struct udevice *syscon; + struct regmap *regmap; + int ret = 0; + + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "ti,am65x-oldi-io-ctrl", + &syscon); + if (ret) { + debug("unable to find ti,am65x-oldi-io-ctrl syscon device (%d)\n", ret); + return ret; + } + + /* get grf-reg base address */ + regmap = syscon_get_regmap(syscon); + if (!regmap) { + debug("unable to find rockchip grf regmap\n"); + return -ENODEV; + } + priv->oldi_io_ctrl = regmap; + return 0; +} + +static int tidss_drv_probe(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct tidss_drv_priv *priv = dev_get_priv(dev); + struct udevice *panel = NULL; + struct display_timing timings; + unsigned int i; + int ret = 0; + const char *mode; + + priv->dev = dev; + + priv->feat = &dss_am625_feats; + + /* + * set your plane format based on your bmp image + * Supported 24bpp and 32bpp bmpimages + */ + + priv->pixel_format = DSS_FORMAT_XRGB8888; + + dss_common_regmap = priv->feat->common_regs; + + ret = uclass_first_device_err(UCLASS_PANEL, &panel); + if (ret) { + if (ret != -ENODEV) + dev_err(dev, "panel device error %d\n", ret); + return ret; + } + + ret = panel_get_display_timing(panel, &timings); + if (ret) { + ret = ofnode_decode_panel_timing(dev_ofnode(panel), + &timings); + if (ret) { + dev_err(dev, "decode display timing error %d\n", ret); + return ret; + } + } + + mode = ofnode_read_string(dev_ofnode(panel), "data-mapping"); + if (!mode) { + debug("%s: Could not read mode property\n", dev->name); + return -EINVAL; + } + + uc_priv->bpix = VIDEO_BPP32; + + if (!strcmp(mode, "vesa-24")) + priv->bus_format = &dss_bus_formats[7]; + else + priv->bus_format = &dss_bus_formats[8]; + + /* Common address */ + priv->base_common = dev_remap_addr_index(dev, 0); + if (!priv->base_common) + return -EINVAL; + + /* plane address setup and enable */ + for (i = 0; i < priv->feat->num_planes; i++) { + priv->base_vid[i] = dev_remap_addr_index(dev, i + 2); + if (!priv->base_vid[i]) + return -EINVAL; + } + + dss_vid_write(priv, 0, DSS_VID_BA_0, uc_plat->base & 0xffffffff); + dss_vid_write(priv, 0, DSS_VID_BA_EXT_0, (u64)uc_plat->base >> 32); + dss_vid_write(priv, 0, DSS_VID_BA_1, uc_plat->base & 0xffffffff); + dss_vid_write(priv, 0, DSS_VID_BA_EXT_1, (u64)uc_plat->base >> 32); + + ret = dss_plane_setup(priv, 0, 0); + if (ret) { + dss_plane_enable(priv, 0, false); + return ret; + } + + dss_plane_enable(priv, 0, true); + dss_plane_init(priv); + + /* video port address clocks and enable */ + for (i = 0; i < priv->feat->num_vps; i++) { + priv->base_ovr[i] = dev_remap_addr_index(dev, i + 4); + priv->base_vp[i] = dev_remap_addr_index(dev, i + 6); + } + + ret = clk_get_by_name(dev, "vp1", &priv->vp_clk[0]); + if (ret) { + dev_err(dev, "video port %d clock enable error %d\n", i, ret); + return ret; + } + + dss_ovr_set_plane(priv, 1, 0, 0, 0, 0); + dss_ovr_enable_layer(priv, 0, 0, true); + + /* Video Port cloks */ + dss_vp_enable_clk(priv, 0); + + dss_vp_set_clk_rate(priv, 0, timings.pixelclock.typ * 1000); + + priv->oldi_mode = OLDI_MODE_OFF; + uc_priv->xsize = timings.hactive.typ; + uc_priv->ysize = timings.vactive.typ; + if (priv->feat->subrev == DSS_AM65X || priv->feat->subrev == DSS_AM625) { + priv->oldi_mode = OLDI_DUAL_LINK; + if (priv->oldi_mode) { + ret = dss_init_am65x_oldi_io_ctrl(dev, priv); + if (ret) + return ret; + } + } + + dss_vp_prepare(priv, 0); + dss_vp_enable(priv, 0, &timings); + dss_vp_init(priv); + + ret = clk_get_by_name(dev, "fck", &priv->fclk); + if (ret) { + dev_err(dev, "peripheral clock get error %d\n", ret); + return ret; + } + + ret = clk_enable(&priv->fclk); + if (ret) { + dev_err(dev, "peripheral clock enable error %d\n", ret); + return ret; + } + + if (IS_ERR(&priv->fclk)) { + dev_err(dev, "%s: Failed to get fclk: %ld\n", + __func__, PTR_ERR(&priv->fclk)); + return PTR_ERR(&priv->fclk); + } + + dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(&priv->fclk)); + + video_set_flush_dcache(dev, true); + return 0; +} + +static int tidss_drv_remove(struct udevice *dev) +{ + u32 val; + int ret; + struct tidss_drv_priv *priv = dev_get_priv(dev); + + priv->base_common = dev_remap_addr_index(dev, 0); + REG_FLD_MOD(priv, DSS_SYSCONFIG, 1, 1, 1); + /* Wait for reset to complete */ + ret = readl_poll_timeout(priv->base_common + DSS_SYSSTATUS, + val, val & 1, 5000); + if (ret) { + dev_warn(priv->dev, "failed to reset priv\n"); + return ret; + } + return 0; +} + +static int tidss_drv_bind(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + uc_plat->size = ((LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP)) >> 3) + 0x20; + return 0; +} + +static const struct udevice_id tidss_drv_ids[] = { + { .compatible = "ti,am625-dss" }, + { } +}; + +U_BOOT_DRIVER(tidss_drv) = { + .name = "tidss_drv", + .id = UCLASS_VIDEO, + .of_match = tidss_drv_ids, + .bind = tidss_drv_bind, + .probe = tidss_drv_probe, + .remove = tidss_drv_remove, + .priv_auto = sizeof(struct tidss_drv_priv), + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/video/tidss/tidss_drv.h b/drivers/video/tidss/tidss_drv.h new file mode 100644 index 00000000000..e229d975ff4 --- /dev/null +++ b/drivers/video/tidss/tidss_drv.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Nikhil M Jain, n-jain1@ti.com + * + * based on the linux tidss driver, which is + * + * (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Author: Tomi Valkeinen + */ + +#ifndef __TIDSS_DRV_H__ +#define __TIDSS_DRV_H__ + +#include + +#define TIDSS_MAX_PORTS 4 +#define TIDSS_MAX_PLANES 4 + +enum dss_vp_bus_type { + DSS_VP_DPI, /* DPI output */ + DSS_VP_OLDI, /* OLDI (LVDS) output */ + DSS_VP_INTERNAL, /* SoC internal routing */ + DSS_VP_MAX_BUS_TYPE, +}; + +enum dss_oldi_modes { + OLDI_MODE_OFF, /* OLDI turned off / tied off in IP. */ + OLDI_SINGLE_LINK_SINGLE_MODE, /* Single Output over OLDI 0. */ + OLDI_SINGLE_LINK_DUPLICATE_MODE, /* Duplicate Output over OLDI 0 and 1. */ + OLDI_DUAL_LINK, /* Combined Output over OLDI 0 and 1. */ +}; + +struct dss_features_scaling { + u32 in_width_max_5tap_rgb; + u32 in_width_max_3tap_rgb; + u32 in_width_max_5tap_yuv; + u32 in_width_max_3tap_yuv; + u32 upscale_limit; + u32 downscale_limit_5tap; + u32 downscale_limit_3tap; + u32 xinc_max; +}; + +enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT }; + +/* choose specific DSS based on the board */ +enum dss_subrevision { + DSS_K2G, + DSS_AM65X, + DSS_J721E, + DSS_AM625, +}; + +struct tidss_vp_feat { + struct tidss_vp_color_feat { + u32 gamma_size; + enum tidss_gamma_type gamma_type; + bool has_ctm; + } color; +}; + +struct dss_color_lut { + /* + * Data is U0.16 fixed point format. + */ + __u16 red; + __u16 green; + __u16 blue; + __u16 reserved; +}; + +struct dss_vp_data { + u32 *gamma_table; +}; + +struct dss_features { + int min_pclk_khz; + int max_pclk_khz[DSS_VP_MAX_BUS_TYPE]; + + struct dss_features_scaling scaling; + + enum dss_subrevision subrev; + + const char *common; + const u16 *common_regs; + u32 num_vps; + const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ + const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ + const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ + const enum dss_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; + struct tidss_vp_feat vp_feat; + u32 num_planes; + const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ + bool vid_lite[TIDSS_MAX_PLANES]; + u32 vid_order[TIDSS_MAX_PLANES]; +}; + +enum dss_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; + +struct dss_bus_format { + u32 bus_fmt; + u32 data_width; + bool is_oldi_fmt; + enum dss_oldi_mode_reg_val oldi_mode_reg_val; +}; + +static struct dss_bus_format dss_bus_formats[] = { + { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 }, + { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 }, + { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 }, + { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 }, + { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 }, +}; + +struct tidss_drv_priv { + struct udevice *dev; + void __iomem *base_common; /* common register region of dss*/ + void __iomem *base_vid[TIDSS_MAX_PLANES]; /* plane register region of dss*/ + void __iomem *base_ovr[TIDSS_MAX_PORTS]; /* overlay register region of dss*/ + void __iomem *base_vp[TIDSS_MAX_PORTS]; /* video port register region of dss*/ + struct regmap *oldi_io_ctrl; + struct clk vp_clk[TIDSS_MAX_PORTS]; + const struct dss_features *feat; + struct clk fclk; + struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; + enum dss_oldi_modes oldi_mode; + struct dss_bus_format *bus_format; + u32 pixel_format; + u32 memory_bandwidth_limit; +}; + +#endif diff --git a/drivers/video/tidss/tidss_regs.h b/drivers/video/tidss/tidss_regs.h new file mode 100644 index 00000000000..440db8d1c7a --- /dev/null +++ b/drivers/video/tidss/tidss_regs.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Nikhil M Jain, n-jain1@ti.com + * + * based on the linux tidss driver, which is + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Author: Jyri Sarha + */ + +#ifndef __TIDSS_REGS_H +#define __TIDSS_REGS_H + +enum dss_common_regs { + NOT_APPLICABLE_OFF = 0, + DSS_REVISION_OFF, + DSS_SYSCONFIG_OFF, + DSS_SYSSTATUS_OFF, + DSS_IRQ_EOI_OFF, + DSS_IRQSTATUS_RAW_OFF, + DSS_IRQSTATUS_OFF, + DSS_IRQENABLE_SET_OFF, + DSS_IRQENABLE_CLR_OFF, + DSS_VID_IRQENABLE_OFF, + DSS_VID_IRQSTATUS_OFF, + DSS_VP_IRQENABLE_OFF, + DSS_VP_IRQSTATUS_OFF, + WB_IRQENABLE_OFF, + WB_IRQSTATUS_OFF, + DSS_GLOBAL_MFLAG_ATTRIBUTE_OFF, + DSS_GLOBAL_OUTPUT_ENABLE_OFF, + DSS_GLOBAL_BUFFER_OFF, + DSS_CBA_CFG_OFF, + DSS_DBG_CONTROL_OFF, + DSS_DBG_STATUS_OFF, + DSS_CLKGATING_DISABLE_OFF, + DSS_SECURE_DISABLE_OFF, + FBDC_REVISION_1_OFF, + FBDC_REVISION_2_OFF, + FBDC_REVISION_3_OFF, + FBDC_REVISION_4_OFF, + FBDC_REVISION_5_OFF, + FBDC_REVISION_6_OFF, + FBDC_COMMON_CONTROL_OFF, + FBDC_CONSTANT_COLOR_0_OFF, + FBDC_CONSTANT_COLOR_1_OFF, + DSS_CONNECTIONS_OFF, + DSS_MSS_VP1_OFF, + DSS_MSS_VP3_OFF, + DSS_COMMON_REG_TABLE_LEN, +}; + +/* + * dss_common_regmap should be defined as const u16 * and pointing + * to a valid dss common register map for the platform, before the + * macros bellow can be used. + */ + +#define REG(r) (dss_common_regmap[r ## _OFF]) + +#define DSS_REVISION REG(DSS_REVISION) +#define DSS_SYSCONFIG REG(DSS_SYSCONFIG) +#define DSS_SYSSTATUS REG(DSS_SYSSTATUS) +#define DSS_IRQ_EOI REG(DSS_IRQ_EOI) +#define DSS_IRQSTATUS_RAW REG(DSS_IRQSTATUS_RAW) +#define DSS_IRQSTATUS REG(DSS_IRQSTATUS) +#define DSS_IRQENABLE_SET REG(DSS_IRQENABLE_SET) +#define DSS_IRQENABLE_CLR REG(DSS_IRQENABLE_CLR) +#define DSS_VID_IRQENABLE(n) (REG(DSS_VID_IRQENABLE) + (n) * 4) +#define DSS_VID_IRQSTATUS(n) (REG(DSS_VID_IRQSTATUS) + (n) * 4) +#define DSS_VP_IRQENABLE(n) (REG(DSS_VP_IRQENABLE) + (n) * 4) +#define DSS_VP_IRQSTATUS(n) (REG(DSS_VP_IRQSTATUS) + (n) * 4) +#define WB_IRQENABLE REG(WB_IRQENABLE) +#define WB_IRQSTATUS REG(WB_IRQSTATUS) + +#define DSS_GLOBAL_MFLAG_ATTRIBUTE REG(DSS_GLOBAL_MFLAG_ATTRIBUTE) +#define DSS_GLOBAL_OUTPUT_ENABLE REG(DSS_GLOBAL_OUTPUT_ENABLE) +#define DSS_GLOBAL_BUFFER REG(DSS_GLOBAL_BUFFER) +#define DSS_CBA_CFG REG(DSS_CBA_CFG) +#define DSS_DBG_CONTROL REG(DSS_DBG_CONTROL) +#define DSS_DBG_STATUS REG(DSS_DBG_STATUS) +#define DSS_CLKGATING_DISABLE REG(DSS_CLKGATING_DISABLE) +#define DSS_SECURE_DISABLE REG(DSS_SECURE_DISABLE) + +#define FBDC_REVISION_1 REG(FBDC_REVISION_1) +#define FBDC_REVISION_2 REG(FBDC_REVISION_2) +#define FBDC_REVISION_3 REG(FBDC_REVISION_3) +#define FBDC_REVISION_4 REG(FBDC_REVISION_4) +#define FBDC_REVISION_5 REG(FBDC_REVISION_5) +#define FBDC_REVISION_6 REG(FBDC_REVISION_6) +#define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) +#define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) +#define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) +#define DSS_CONNECTIONS REG(DSS_CONNECTIONS) +#define DSS_MSS_VP1 REG(DSS_MSS_VP1) +#define DSS_MSS_VP3 REG(DSS_MSS_VP3) + +/* VID */ + +#define DSS_VID_ACCUH_0 0x0 +#define DSS_VID_ACCUH_1 0x4 +#define DSS_VID_ACCUH2_0 0x8 +#define DSS_VID_ACCUH2_1 0xc +#define DSS_VID_ACCUV_0 0x10 +#define DSS_VID_ACCUV_1 0x14 +#define DSS_VID_ACCUV2_0 0x18 +#define DSS_VID_ACCUV2_1 0x1c +#define DSS_VID_ATTRIBUTES 0x20 +#define DSS_VID_ATTRIBUTES2 0x24 +#define DSS_VID_BA_0 0x28 +#define DSS_VID_BA_1 0x2c +#define DSS_VID_BA_UV_0 0x30 +#define DSS_VID_BA_UV_1 0x34 +#define DSS_VID_BUF_SIZE_STATUS 0x38 +#define DSS_VID_BUF_THRESHOLD 0x3c +#define DSS_VID_CSC_COEF(n) (0x40 + (n) * 4) + +#define DSS_VID_FIRH 0x5c +#define DSS_VID_FIRH2 0x60 +#define DSS_VID_FIRV 0x64 +#define DSS_VID_FIRV2 0x68 + +#define DSS_VID_FIR_COEFS_H0 0x6c +#define DSS_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) +#define DSS_VID_FIR_COEFS_H0_C 0x90 +#define DSS_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) + +#define DSS_VID_FIR_COEFS_H12 0xb4 +#define DSS_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) +#define DSS_VID_FIR_COEFS_H12_C 0xf4 +#define DSS_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) + +#define DSS_VID_FIR_COEFS_V0 0x134 +#define DSS_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) +#define DSS_VID_FIR_COEFS_V0_C 0x158 +#define DSS_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) + +#define DSS_VID_FIR_COEFS_V12 0x17c +#define DSS_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) +#define DSS_VID_FIR_COEFS_V12_C 0x1bc +#define DSS_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) + +#define DSS_VID_GLOBAL_ALPHA 0x1fc +#define DSS_VID_K2G_IRQENABLE 0x200 /* K2G */ +#define DSS_VID_K2G_IRQSTATUS 0x204 /* K2G */ +#define DSS_VID_MFLAG_THRESHOLD 0x208 +#define DSS_VID_PICTURE_SIZE 0x20c +#define DSS_VID_PIXEL_INC 0x210 +#define DSS_VID_K2G_POSITION 0x214 /* K2G */ +#define DSS_VID_PRELOAD 0x218 +#define DSS_VID_ROW_INC 0x21c +#define DSS_VID_SIZE 0x220 +#define DSS_VID_BA_EXT_0 0x22c +#define DSS_VID_BA_EXT_1 0x230 +#define DSS_VID_BA_UV_EXT_0 0x234 +#define DSS_VID_BA_UV_EXT_1 0x238 +#define DSS_VID_CSC_COEF7 0x23c +#define DSS_VID_ROW_INC_UV 0x248 +#define DSS_VID_CLUT 0x260 +#define DSS_VID_SAFETY_ATTRIBUTES 0x2a0 +#define DSS_VID_SAFETY_CAPT_SIGNATURE 0x2a4 +#define DSS_VID_SAFETY_POSITION 0x2a8 +#define DSS_VID_SAFETY_REF_SIGNATURE 0x2ac +#define DSS_VID_SAFETY_SIZE 0x2b0 +#define DSS_VID_SAFETY_LFSR_SEED 0x2b4 +#define DSS_VID_LUMAKEY 0x2b8 +#define DSS_VID_DMA_BUFSIZE 0x2bc /* J721E */ + +/* OVR */ + +#define DSS_OVR_CONFIG 0x0 +#define DSS_OVR_VIRTVP 0x4 /* J721E */ +#define DSS_OVR_DEFAULT_COLOR 0x8 +#define DSS_OVR_DEFAULT_COLOR2 0xc +#define DSS_OVR_TRANS_COLOR_MAX 0x10 +#define DSS_OVR_TRANS_COLOR_MAX2 0x14 +#define DSS_OVR_TRANS_COLOR_MIN 0x18 +#define DSS_OVR_TRANS_COLOR_MIN2 0x1c +#define DSS_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) +#define DSS_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ +/* VP */ + +#define DSS_VP_CONFIG 0x0 +#define DSS_VP_CONTROL 0x4 +#define DSS_VP_CSC_COEF0 0x8 +#define DSS_VP_CSC_COEF1 0xc +#define DSS_VP_CSC_COEF2 0x10 +#define DSS_VP_DATA_CYCLE_0 0x14 +#define DSS_VP_DATA_CYCLE_1 0x18 +#define DSS_VP_K2G_GAMMA_TABLE 0x20 /* K2G */ +#define DSS_VP_K2G_IRQENABLE 0x3c /* K2G */ +#define DSS_VP_K2G_IRQSTATUS 0x40 /* K2G */ +#define DSS_VP_DATA_CYCLE_2 0x1c +#define DSS_VP_LINE_NUMBER 0x44 +#define DSS_VP_POL_FREQ 0x4c +#define DSS_VP_SIZE_SCREEN 0x50 +#define DSS_VP_TIMING_H 0x54 +#define DSS_VP_TIMING_V 0x58 +#define DSS_VP_CSC_COEF3 0x5c +#define DSS_VP_CSC_COEF4 0x60 +#define DSS_VP_CSC_COEF5 0x64 +#define DSS_VP_CSC_COEF6 0x68 +#define DSS_VP_CSC_COEF7 0x6c +#define DSS_VP_SAFETY_ATTRIBUTES_0 0x70 +#define DSS_VP_SAFETY_ATTRIBUTES_1 0x74 +#define DSS_VP_SAFETY_ATTRIBUTES_2 0x78 +#define DSS_VP_SAFETY_ATTRIBUTES_3 0x7c +#define DSS_VP_SAFETY_CAPT_SIGNATURE_0 0x90 +#define DSS_VP_SAFETY_CAPT_SIGNATURE_1 0x94 +#define DSS_VP_SAFETY_CAPT_SIGNATURE_2 0x98 +#define DSS_VP_SAFETY_CAPT_SIGNATURE_3 0x9c +#define DSS_VP_SAFETY_POSITION_0 0xb0 +#define DSS_VP_SAFETY_POSITION_1 0xb4 +#define DSS_VP_SAFETY_POSITION_2 0xb8 +#define DSS_VP_SAFETY_POSITION_3 0xbc +#define DSS_VP_SAFETY_REF_SIGNATURE_0 0xd0 +#define DSS_VP_SAFETY_REF_SIGNATURE_1 0xd4 +#define DSS_VP_SAFETY_REF_SIGNATURE_2 0xd8 +#define DSS_VP_SAFETY_REF_SIGNATURE_3 0xdc +#define DSS_VP_SAFETY_SIZE_0 0xf0 +#define DSS_VP_SAFETY_SIZE_1 0xf4 +#define DSS_VP_SAFETY_SIZE_2 0xf8 +#define DSS_VP_SAFETY_SIZE_3 0xfc +#define DSS_VP_SAFETY_LFSR_SEED 0x110 +#define DSS_VP_GAMMA_TABLE 0x120 +#define DSS_VP_DSS_OLDI_CFG 0x160 +#define DSS_VP_DSS_OLDI_STATUS 0x164 +#define DSS_VP_DSS_OLDI_LB 0x168 +#define DSS_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ +#define DSS_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ +#define DSS_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ + +/* + * OLDI IO_CTRL register offsets. On AM654 the registers are found + * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from + * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL + * register range. + */ +#define OLDI_DAT0_IO_CTRL 0x00 +#define OLDI_DAT1_IO_CTRL 0x04 +#define OLDI_DAT2_IO_CTRL 0x08 +#define OLDI_DAT3_IO_CTRL 0x0C +#define OLDI_CLK_IO_CTRL 0x10 + +/* Only for AM625 OLDI TX */ +#define OLDI_PD_CTRL 0x100 +#define OLDI_LB_CTRL 0x104 + +#define OLDI_BANDGAP_PWR BIT(8) +#define OLDI_PWRDN_TX BIT(8) +#define OLDI0_PWRDN_TX BIT(0) +#define OLDI1_PWRDN_TX BIT(1) + +/* Supported plane formats */ +#define DSS_FORMAT_ARGB4444 0x0 +#define DSS_FORMAT_ABGR4444 0x1 +#define DSS_FORMAT_RGBA4444 0x2 + +#define DSS_FORMAT_RGB565 0x3 +#define DSS_FORMAT_BGR565 0x4 + +#define DSS_FORMAT_ARGB1555 0x5 +#define DSS_FORMAT_ABGR1555 0x6 + +#define DSS_FORMAT_ARGB8888 0x7 +#define DSS_FORMAT_ABGR8888 0x8 +#define DSS_FORMAT_RGBA8888 0x9 +#define DSS_FORMAT_BGRA8888 0xa + +#define DSS_FORMAT_RGB888 0xb +#define DSS_FORMAT_BGR888 0xc + +#define DSS_FORMAT_ARGB2101010 0xe +#define DSS_FORMAT_ABGR2101010 0xf + +#define DSS_FORMAT_XRGB4444 0x20 +#define DSS_FORMAT_XBGR4444 0x21 +#define DSS_FORMAT_RGBX4444 0x22 + +#define DSS_FORMAT_XRGB1555 0x25 +#define DSS_FORMAT_XBGR1555 0x26 + +#define DSS_FORMAT_XRGB8888 0x27 +#define DSS_FORMAT_XBGR8888 0x28 +#define DSS_FORMAT_RGBX8888 0x29 +#define DSS_FORMAT_BGRX8888 0x2a + +#define DSS_FORMAT_XRGB2101010 0x2e, +#define DSS_FORMAT_XBGR2101010 0x2f, + +#endif /* __TIDSS_DSS_REGS_H */ From d5f563ccddfeefe624457e137ef76dc203d63c9c Mon Sep 17 00:00:00 2001 From: Nikhil M Jain Date: Tue, 31 Jan 2023 15:35:19 +0530 Subject: [PATCH 6/7] board: ti: am62x: evm: Add splash screen support Splash screen function needs splash source information to load image and display it, splash_location provides the necessary info, Set default_splash_location to MMC at partition 1:1. Probe DSS for splash screen display. Signed-off-by: Nikhil M Jain --- board/ti/am62x/evm.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index d65ee1d6960..20b2a701223 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -7,17 +7,36 @@ * */ -#include +#include #include -#include +#include +#include #include #include +#include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPLASH_SCREEN +static struct splash_location default_splash_locations[] = { + { + .name = "mmc", + .storage = SPLASH_STORAGE_MMC, + .flags = SPLASH_STORAGE_FS, + .devpart = "1:1", + }, +}; + +int splash_screen_prepare(void) +{ + return splash_source_load(default_splash_locations, + ARRAY_SIZE(default_splash_locations)); +} +#endif + int board_init(void) { return 0; From 03610ebf3520ae768ff90c4831f39088088ee666 Mon Sep 17 00:00:00 2001 From: Nikhil M Jain Date: Tue, 31 Jan 2023 15:35:20 +0530 Subject: [PATCH 7/7] tools: logos: Add TI logo files The default splashfile name saved is ti.gz. User can use these logo files and use it to test splash screen. Signed-off-by: Nikhil M Jain --- tools/logos/ti.bmp | Bin 0 -> 160770 bytes tools/logos/ti.gz | Bin 0 -> 12285 bytes 2 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 tools/logos/ti.bmp create mode 100644 tools/logos/ti.gz diff --git a/tools/logos/ti.bmp b/tools/logos/ti.bmp new file mode 100644 index 0000000000000000000000000000000000000000..7fee6e81e07576efedf6fbb045c7b8c3335f8e08 GIT binary patch literal 160770 zcmeI53*2Q>-S`nRu7hFRnQA%oX&9KQ%GbC`C%712<;eY@0`ac_Qy6u4>26w|2 z{4>m)NmP0JUjzU7&wplyo#7NX0e)7(@x+}3$HGc56YKydgK_!1h8g!2n7v(Xk!J?; z!4KgQ7?Ul7YvZ?o@4;f}^}@K@g6+H={sC{nzu=$n6xkxGCXd3W!aYZgY)-8>Gj;W8^QPC zT6hASmyXT1;d!_lehz!Ua^SqPtXMTwSRZPDd-*=t8E$~rz;&ev$Ho*m8hxxNN{ukg@STI`#*Rz7_s^j(u_%d7#j$PYYCdRv#UJ1Lx zyihu}iFeI#Ex!bwhHPK+e#`y?dm#GYMY{u7KEBbKSWU_JjsoO_*c# zP?!p?`6Kd`7zX>mU*R3d>M-j!&NPRB?e+eD4<3NBeAzNu^{a2!Ysaf&XmfC!#&i(w z%`wE!m+xQMHR-*N&Png#V=x((FUw;bY3%=ja1+GZ6#D6Xei+VyRaz+5zPji1zFq)3 z!ujwxsN*vEH<7Qx?eI+)2e!3YwN-o{Xdu0pj@5634(tVKzv{0IqqLfYZS_ z6U1?I6?_off3>U)(}LxG7M=vfGfK_w;5W@ua1SVsZP%lLhXgJ1nvQ@Wu`Cedm3*#=ci|gm^lBw4r72P8;wGExF7B>UDMQmOr9d}C|DERdxm_= z;y(>ug29OP^GFyC4GkqseJluv!Rrvj_IkEj9<(oYdA)|E;V+;(1RsD{I`gjvH$ahG zNyI8JGXx#Xf`1K|2%VM(DR5=5uAl?&L*BOknXrvO8&%i0vJ2CK<$etQ2FfGQirq1< z^KB9MKD-GrxrM+FLrZNVo%ZY(plGv-%1siK{O=v&u7UNzK9;GXit7^%cpp<-53Yrn zI6vG+CTT<0!Zq&N@B{>T5zm%TmpWt za5h{B&K=JpdC_M68Ww}1<^?_JI`__jm{`wT(6sL%4ekPP6U5{O0*x;$FO6Fm_adk*M?I;7yja%La3lN*PJt8PG|*1m0oui^c>eqjG^|gAg?bmlZ@+?g zAGd&LAJg!?a2M+Tq?JSvPU5TfP4kf|z~}sB2f@U`!)IdfYWYyA`A*yJInA2-v3kLjf7rv0?jL zZX0Qr0-u@1Pmy$@2uR4-Gvs z3>F9HToC8plF*R8D8RHS?#2HES-F{utle=>`)znHlgK^QJ#ZAb?;8j6z-%xQ=7dGy zR%-uC?}$=&$Bvk7W=-;phc z_?f|VIJ?$ySrgAvdx7bKo^?mT=@6UeuCexIJ z^G>!B($5Rmg#t3}8~C?^Z1O_C>A>fS`7`|Egq;bWhVd{T%nl<{cMPsNI1-+Lyj)Dc zB83%K5q+lt?&nN!bpA%C*H7cFUDPS!T+eSw)9Sb%T(~HGKAf~+{x}w$pV|4tWy5ne z=j9>T5jGmu}yTnqPrqGylpjbm$7DuJ_|o2r?PZ%5{w?xgc$*Z&Cc`Lw+m{#O^q+u7te2MnLH|E!n1$)^pu= zAk1UWH@}4SVKxYDFLFnc=F9LhWW{#uldY@r_qPVPpTX{gv68*t&fj+I&Ywx&uH9Lf zJkFo@ATKu)kUj6L#Py^!(Ve*4LT!y~b|*;dcz0hl8M5Ns{R%WI!u*Foey$TVAiLu{ z`-Pb!(#-D6Odj`#F}+#beV|>c>l4@N>omxV<(vhc59{(2U6>9&3E6YP16+@f}lW_L!B=z@?i=ell>E~w)}#A##lV%R|J&fVl27pto%jPzk$T?PNOZ~`RfXznx-B*7X zislbdb#}*g9sxIkbGfbYYzb$nlV35sMm?atOT>K<@^*s$lRyHSw~@`SPNUNkTNj%4Zk zAUat$M!5DF$Y@vy+#}BeHT#Xf@B3^A=!a{;(J&;>+0+}jZaRNngfh`SB+uD!J=?4S zt3g}3H+_c9@IMQAxrBf@niWi%Ua&hpzqvo(f%Mwv8(ToMD}=i)$IcOV6TU<=Q%N9s z+@EG`$-7)friWCfdnl|52*|4`IV*cc{BI&O)0)SmwHIyOWmT zI=($T31u>zc4r(7+Yp@Jq03EO(`Hx-|EKdRXiZ^?IM&8@c92zj;t6#IbSm5D#kl@5Tn&Eb6I+)EPQ>{z30nTnqnGtU zKZeBaP>=d{UbZ@aNcw+vCp%`d`Xo*EJ_f(__#E8(x-RSu?jxRpn0UXx1=*sbe$pHQ zu6cR!%viSuMhnOUl3x4pi+n-p_1U;%KszJuiPnNsA@*$2ar<5H9dV|XdM|N3YjOdfmWoa><$es z(wk%7@$K`A9pD6b0K&b+TPJ_1-Q+&?(3_wOpAT;X*MRS0Ta|}N*z|8k^n-fnN7wBR zbp(Akn?Krxmm$c_cxvCX<@HHiC|6fIvm9&=UxS~+ZQwJtx1mh_LF7h|ucG0aG(%-~ ze4cV0T$`dU9)qmSb1i-qCc;iI2Q;)f8$f(7+a1T^f5BUj7xl3YtPjtmk*3=RYUd05 zowhsLz$G9%)?$92!=DZJz*1SAXZ^&rYj?(z=W6g?$0U0OG=A9ZPPU)=X-gK*GwN{z zaF2g7Oa#YtY#&8%O`N}n=gaS>YuX=lu_*o@foo2?at0Zi{?4!;^g=(nYIi6<=zDqm zW%K7z;$1`B!v=}k9U?=SK9kYb>;)Hq`=u8lyEb!KD(?|{CX8z3ev$4Fh?Rdd;hjA1 zP+U`ahZNVruCN$*FB9Dq^@aGJv^#0L7r~tfd2!8kAE8}!-S%DwaZGs@OuCHQX}dFp zGPQ-DgY6^iOxS+ldHQv@7nUs1e@k|UGQ5wA!*3uq-Uv?Cu7hwL13@0aGc4axXZuVW z!W>-)|8{U1cxH1S7<-OJaG~5nO!RkN**bgGPuqhoR>Xf1IB(mPx5=;z^lCTTY8UuaC;^}gWVx6l(_)@{Xsj`?l>k(BDUuma6Gi6H_{EI-EqCm zLr|UA_vb)e**5L)j1cV);jYW!ynweR>V4SW?@+gG-VuC9m6sO?_#}jT|5^N=^ORTM z(~$HR*Zw^Xc` z+wP2}j<2zhyzfLmb;@GRIc76|(g^rGFFmv;R(#N>AbCV!_H*L$!q+yFs* z7oB|PgKPgfX?H>$t-6D#>h>qok!QEp4v|C+>Ys_G54%w4;28;Jt7YE!N`qLG=L%Cu8d=LMd5EI9i>-F4V z`ck`-rg5%m$6RCE75A#n%k#m#n9t;svC*mmNq-0oh261_vw-&}%LuML>un7;L2Uo@ zFyWg(!yb{ap0hi&$$Q}X@;v0_4FYzDT3__T0q_nePr!O$Ii0pUj#2e_e*q5=J{f|I z7_i-;4BPMh{R+GUF>&0V4UPfRdoJoFyE8NG`7*e#Yge3C?uk6V?E{O0eQb4l_EfsG z?XGDTLTsKA+_GFw%IM$d=&4S(*ckfKal1pAj+K$%bFiZE=bCXQjDe)JxZb0}^N#6Y z8;I@o39gg(xOyEPgX`gB_#&(Z?kAJ+tlN%|eyHq@?e*T&+8ObGkTBP|m^gPm7u0o+ z>t3`wv(m0JASRx9ll3Qbgll!;9#UJNc&~p9u6b+2(~uX#2J)OuyRsoH1ItEOjxfiR zYwcvX7utT#Mjrd*zJ6yYIw#oAi(woj>cH(8yJMSRc_3jZ#sZKo~XJD+E0!}Ibg0iNmVy2*8~ z*`4vUX-$|6d3l$BuS4yu6FNhf`_n~|^WO#6 z(01+4%4vC<;ZA}g@!8`0A*jJN^_tyrZ#NZU;y9fGSHsWXOW-+mQJ4)p$JX>*>tr8# z=!bLj^AJ136Wq3(LylSdP!-W8)0b}8olj71v-uO|TCH8=ar~8?cNQT2M##&X1Zc;+ z&&$C)V83c(IO`7;X2XI%#1*-uI|O_lke8zgD1E;}e62l}&$VmkFCZo-6WGk|SjNWi zLZkrKV{LEpZ(4``aNSFG=ONnTI{H0`=~P>?5`^a0T*F`kcnXxMus_(pPTHNjDQ{e@ z;sOt8Y|m1#70gwT%rtYsWe{XC9_NDg@(w5x+p#WKMy+`Kg?1;T&8Dwq%y@{O8?J=B zyhcFN-zkzNX%ntsQ%o@6UBF*`2@9 zo~^+(H80wsW1!*Rwa(lN@7ej8jMwA$jQ3F+a2=SXXnkFsrz%>yxc*6&m9`{ zQ`eBpMVi*N$@x;ZcgiH|NiXeHA4kHw&?&i;g68hY4iBJF^re$_$GQF25=H-=xGkVz z{@8TFo7tVkNt0irUMK7`&~ooh3qG^k540nr;c(avqHPO>6F(TcvkLi7fMwGD4$AIO zj{PXIBSaYjRb@VVAKunr_?L*C$~ z;ceNSP!_H>^S|L1{g#P4V7o)!(4XD$$JTA<`wyUQugGfdMc-g&0Zi*26(b3jmkgKHct1QS6q-xPSwi=1@*yp!J3a9_q#{{+}N+iOH{zPv z9nY^n0>^R?_lZ6yOy(wT7`rjo{A<7jcmrIYwgJ!|D*rZ&<0_DafbIITL)Z z>ikUp{wS{c@EKuDOrPv=af{lrByo8=9Lln9_Ni`6aIIZ+50ICR+8qk7tJe#{9BV(z zR~)&1p0F*Tp^SV0X`h3 zY!P*S;>zrf>-S0UHXH{FK)$_R&keRWFOH$jA(qE`xh~uao;N=Qrt|#i+{((;Tr2{y zab!Q^+u0&|dqp5j+W<7Ikq1)a@gOvAct++J1oRc6Kf2GLdKa zf7$z;#fWeA?kvn7pZ}J&m3Y_ZJ0Zwzcoqqn@Oxi3g#3NAo!YfU!Fg}GfY|a1kZYFS9(4J;-9dZtba;s)8~ns;cU;$lJc?(1?4VCzTv}l4&Mk_vF?*#d2q~YUu>J$2FLVD z@LzBfI9HTcU~6dTcP|FePWy2N#MTFb2QA*CC7~C)-&ULGgZI5HyJNpoR>PePMdJK9 z6-wt1@u58D?cX8DBY0MU5U=an{{skP6K^8UE!XN3;ahM(>blNd1y6u$Vpd%9lW!Ao zXNR9>B45IP3;Yr+^QUkQJOwfN2Z85-=}dnvTn~l^xf{wvT&UMaf|9+F> zVy^!T&q0wqM#R=o`~DbzsPi-U)m2_xuig(yx@LnYq{DT+y$FIh=Y9gNQAshnDXv); zK$-lL$lah>6Ke6KbuIfbyaz?{DiNQ8y8eZ0-0dNz7t7Qpp9bFBJjW5{TJt-27`$(a z?mm#*1Kgm4ariB-NUZNdSORK&%zKPWaqo8<1bG3^#~{Ry$A4cM>AiUzu7tC}xncV+ z1@#`2zY=&d*zZ%o@puQk4na=G6aGC_*AsP_9rvbt2Q2FxI1HShUx%aNf8Zf_3$k(# z7s-6d_rKS!X{Y-B2s{bh67{n`)aF*N>7mv3&WAR;x zNti#26Is|C<5EWAs?+TFckUhzb3#&vE-Va=^=w)$>m=5nYy#W8FJ#O8BG>t`pUpE^ zzioEywGWP+&7qUyRJ(c?d=6%TY~QSNG`QY)Z}MWlzXsliOAAvGm+Gq8z4zlgiKL*Z)W@CmVEz5(XbPu1c zYZTXqK+(9h{%c?b$ak~u+IVmb?Eo)95XZo&5c=tO%kHN_x=y){o1GwOpDtLZbJ_Ky zNLtbL1Ty!%)6kvz`vi=b?cZfE|e$73Ki zPG2VcBuJizsbBo!T5%Bk4V-Ju#PKi%E{5m9x;_NSEz^Y$z+~u#sH*;3eIX@Ev#r^71AD+R;_Oy1xXi%n_2cEf13;d9D{4$+dNAdp-*{fn&cF zd67iFhx@^O;a*TXvxo9~&83a@cXgNq-4^eo`wI6ky{3wm+e6#iwL3GD=PPgnTn`g- z7L5Ou2Isb~KoNVh6Ebu6N6UZQmNMhFE_m5?;o2#9t1smGS-)(L90YaWUuVlp%ltTLY)4U&Z~i4bd>VVA)sFe9|m-%Uw(1;q3p z>hLTy1FQhQg%Cawe^pE*BY2G6LsgZJT+;B%B+ z!1lU_$`{>p*R;`jcLa3Hwo`PSsJkzN=iQ#uM=K4Y-OdTu+J8e{o*^LroXxQ`7dSqO za85h!nl>R#HwW$*C@RnJhVyosH>n5zJmCCVAGQF;uxsOL;QC@eLt5>N`-Qr_R2pww zSvv+AXZw=>ySN&Q>GVX9gzoI%%)6I+9O542;4Z6wSNYc2UZC2iB(%8mU z(pr`}s=FuodW){fXW!iuS!c6$CHI1KwyjmYG%GV3?>%xYN}8(+j`3`oyg%uC$WzqM z5Kg*QbejBjh_sIVZuHYWIA21u>RiJ!cO?3rmcY5{y+b;SNrI*`WwXM>?^rV5<9PQWsr+pcR zdn>dezO#A*UV`V~Y4EvYGkg~LESNtpe<5Haa2-$9zkbkX+TNC*v-Lxtsy0>{s5DS% zpxYWq*ZIA1--05UO2l7b0{AZ0cW$2m-v{`N@q;a}CTYxbKg8r-0)4O0H}89BtIxzw zfS72LKLXvpg;n{L1}Y6y8tAG9T*u02r}DI%#c*$cBAHCYH^BElvqNe9P2zo@cM%lH zWFqzf-_7>qxhJ$Mb$yTQ_ct-oj_(OIeYJCMsC@cghFd<8xO ze%H|QI}*~m9(uOe58i~B`0UKG-PhOFPyGWC^4Y%cLz%ovq~8Uu2uXi%2U1;E^4J#e zd7w7Ov!CrPl0OmQnaA&^y3(Gi&`JZ91}Y77O9QT3Da+#eY-bAi9YA>BG7BR%?r|gx8^& zJVFBRSMvA!yWPI3{7M6r1}Y77N&~E0!A@L`zvwqM_Y=1Xl%9LivOF{W3}Wy32~KR< zPPm=wLQ)RptqXo%(2Bf5q6^?-V0#n$qdQze-Jbn+gp=WTP=`erugy6I>VB6zToivm=4$970 zvG(}Q+?lWu_`Azm-}Dcqq;+f8Jy*8FfPT|Alzpq}sx(k(pwd9l0PCB3?ERtWJq%HG zax+(cYnD87!_BVKvv9o~`243#UL&&h_fq0rwtgM;;{cH^J`@7KMdiRX7YDhi39F3BCv& z)d1yr);bEBo!dxKD4x@Nlr_-&-Od-<7u;^u7s@YkJ5jG?w_8q8d#dnC1JjcR(s?r$_cj;~`2&^C9dwSr zrMVo^>lWns5aG{2Cq*0d9NYrCL)ZQ;9%Z-tekXYz81zDZ_0nz`?mt>3sjtmCLi1{F z7us2;hgwBB&j9NUIt_i#jy<1K`}aT>gJoenjDz`MR;bI9Yfg1pX<)k2Ksq0G#eD;Y zLwr`ZLQp#Xd0{j76l|Ttu&rP$Bw2L9=W0vAMqs@8_5#l--I9|iIQcjHLfbp(Qnt_b zz7IcuBb#s(@%zH4&<6ajbL!%U&`KH2>d41`j&fa3{reBi>acy^h9yJ$f=ig~+!mUZ zk*_~?Z5g{m@^6%eI$|zqM!;@ho>*DgF!lEx@HYWF!rtJwkB+-#z%ainyaMiozrjOr zFWdy@!@;ltIKC5m6>C=&R%u{b*FZY{-J@Ly!zC|Lv47hpQ8(_ga2NQyl^CxQejtRu zS??U)1U#=j53hmww4`OE8+2(g)t}tftyPkgr{!)6 zbWgtxcxLq+SR{WZ!gYCEXkTy%3+?7D_Iibuk8uN7rLfN z(=La50~CpM`t8hopxp_!@h$uV-Pb%z-Xp;KTiC`bqSC;$r~$^jYqrl520DMp+7UU4 zQj)U+?npSfNvSsyzkv4y*FLze4z+aK?$|fcZn&Pu#I%=p~Vc_$v zmEcy$iuTB{kd&9NCx0E%;X2;Vf|$4``Y~9i<@#Mowr^Y};#uo)_#=2OIwR#GT+c_^ zuDrZSz%eiv)v-iaLyOWWFl6{q~C{Y=l)Pi zSM5$1bacq)K}B}>IpRJ7A$im#UfY#lrwK~dP}jbtV388W66adKDSRIsGwxN~w|fRi z*80?41=qDUi02~D3-+U^edeDXehRTYkZb+9;F%+gksa~B0zodvQ}^#;M=Q$&lHRfw z0Kb=y$=?VJHdEVkVJ?wpvx(p{x3yp)upjnS%(Dc13T$6~Oxyllp!&UU=Dt+kX;TA? zbLX4SJr0MVUazULK^`JxyxPW0OIY2hSisfpAt0`L`o1dp{;|y$-~h7xLH+?O05F z-={rG^6P@nsQv&!)J0PpoNWNI_-V(t_auXarZ-z`|#`w+UwAVGIwdx zT>*K~<}H+MSLLrXFs*5TG49;(OtA&{Y@ip!=Me6t6LsUR2oFP%xNrOhgm*&A;CCGu zN*QXq<2sm^X9yUK-O+Ar-O3mzU4Bg+P1rHuIcn)pMw)JR+@m1uX>9wiAUUsuw7P`J zc(?^(@&bW7f%dnS6~AM6FL)Ca&qPN+k`6bNUFObAI@=jLW4%oHR+)0P#{Vif_AUj_ zH+6N@8kh5sF0^5L{I5e+p66l{$mOaoD-BE=8gOiEHz2gX6thPp-a2c7uR`yDwN5ML?+KCa9zueD@)vk zxarpJgc*QN!0@7u26*&-&_5jYNNV7J2S8Zcy`S2HRiW21&i4+^n0%ZHnu&xK7Fx3Uhy!REMj5 zTMxz=Cap+Fo4W7ARTsWf%S&ZP#tU@b)-)exd>^yPq z?g8!}ds$qMHV(?h@3#e$N*e5Xbr2+3aF+#b*HFoHV|P%f<7feJU;g26k6Lllyq;@( z#unsOJU;>V4tepuUI+_9(<(^gy1pO04MF~b=UDi03AcpAIrmMjcZQ~Qo4|BAX5xBI zSOz?c9SqvVqCJ$)7(WRu)mJ5|G|j_RN@HL&J3#M=znno!S}qq_+&$;$6VKh2kDRYbTPx^ndOh)`FI* zF&(T74?>Wu@GJ~I=ZoQ3`7OlcP6C&P!upNNpxv7fR)f!hw%PYaeqU*Sn?3vW`<`)y zl~oay2Kqz;jN>rZKaKwh=odMbhK9ep<};nsn>74J;>UPfa9v+~$LxN2C}di&J5y1V zI&*)oUC6T=Vf(`I@EE)UJG46u$m9L-n>6dPj3Rl3h%bV6s^w}(J1d+F;od)we-p6Y z7#|}1amb6$0zD%odzn}RhzsRer}ptsxDqDA8_0wLoe4%K6egX~eq6pKb9Rk^Yahb?-{QqMRt>5qzpXq9!CWE$W zAmTVZ9p;Bq-`~34g!RBR z!)HN5AtzBu*Zv-L7;n_!I(am>mgeOd0tWND(R_K$t_NgyDAfDovpV0${S#v1`NMNa z=z7bpd0+v!4uaf;r{Q@SVZJxYrVHtHFNZ=qK%Dj1#);sw!hwos$HQSEXt|$N!b$_Z ztO3UIy5L!$SH->FC7^BmS&Gkcj)1X2xA<3vzeABY_dOGZzgw^{{=>ksLb>`NDM`yH4lJbuBv*TssFV z?$=L*C7|m=ggUxuciy7>FQt7MhZ|!&;eOM81-Ld3#O^FfzH6YFJVAowH#_YrmVDm( zRUx}ixq$2Jze(gfK%c+GMEmNq>1fr2JEjhWVAt>#%D;%w&O8X0!4Kgxurzq?v#rs3 zs=!JE{i*@R^q-)Y#r0p?=sJ+h!K@qfPMCYb)1gcz5*fZNXef)g5VjNkqGvorwIn`g z@+_r29Fnzzdb(+M)W_DLFHPJHiT4cMvfW9`n;qA8A+ddsYxq?#34&aUM>`dULCY?A z{B~gig#E>1_}7Lo1}wMeo#$D^75+P=#4Q9jL6LYSydBPiZ@`wI&7KDu#(B$~suETj z=o1Yv&R>CEm;a`LwY_LewZzW|K1VCtV?Ij!`(yb-81b$<>%dbmP;o7D@46_2qPy-= zSJ&-MvrgDwa838zvsAP6#;18~`wrlm9FyA!^o+4Dyq+e|K6xgY6I!XNmd5n39fa}k zxcN4CRx!@DgnIDSXNb}TRU?PTyd;u0_$g#OpLq0D@I2(R2q1O2Q4 z#jLt`i9-^*eClPh+XIVou>T&?wt^m7YW=EEO$Qm6=>TP*K*INwP&vR@?+Pex2#1V zdoH<=>xE%fI0s^K3xSKr$_!z|Zv@ZfGW*=|Q1DDw(~tf#Nz-b_lYC`qtGG%7{h|TJ zv*-G5;ofmQa2+0u_-~$kq?t}h<9_(>B^9|pJ`hTaBHlTE5e!s*K}Oe#(t0`_Nqs$M zchmu>&(Y9e8`5~=eh%+JUJN@0=7O+ZuZ9192;%o>t3q2UCB5VG5b&&{gnh}%_$MVH z_5b@9mq$S9HzLHZ56?nYJpUwZ#BJJ6)1)kjdkpO6btRPsrUeb8V>^uTZn%SeW_vw26n?^3RZGC70Dgeef@R6GZP=aalV zNx-^LS_knf!6eAaqg-gun&q`kfu->KF3B_eZiZJqHEtYQ{GI&OEY$$KQS0VWZtW_P8-m{oCE65XgvS+CfuIm|i?q+411}=lF zXji`g?r9R;g>u4m#~IojOV5 z+^dGQ2ycTphgS+Z#2@nI-47F&e^$~^SR~+j!WInW52Z`Jow7SONBZUZcPPvOo;PA> z_veJAVMn+Ie75N`CeIZ$b?Ar1;P(&{pRc)xNS?3NGNvBF&A$fR2SK!7ABE&z=JUj^ z)3iI_YPW*K#*cRQi%@3+3(C~CdGmixYkav@7n3OTWEq z)KX_csCU42hrB@#%izzh?ip*wL_bR%B9``*&XtQHQGJ5 z`Yp5DM7JexlKKk}>d;*jegIk9#ATg4$JJ(#7N9kfcE-5K{P?!U8pQB$#>! zV|PAC{^Q^&=%n0FVdKGd*n9K;;5x{jQMioCt%U9g4e#R!^O@9Ma6820NdnJ;O`+L) zLEE+-JPk2%&$BtSe4k94vJ~!*;c^-VH<&KvuR@OweE><1T?)Lq!|T2gna+K zJ`oyhU%pNGYx0D9I2-q-OD zy9SsuLt%G3ugs~gam8om??RC{?~`u}a82*CCHIz{kO>shbe(H9E+|7=AkC82;z>JD zyQ2FZdBFtxkvGn;cpQE<&Er2@EKIHRz zJx42L)NVx1Lte`k?~nRi5jKF$;1jSuEDv)*NULkxYx>I-TU}Nfs5DTZ0p`t6*qwW+ zC;6K!xX#yY;58@`_n6N2FvmZJ-@RuiWCDeB!tSg`IXl2eD9~0rvJ?`ivG<@4vSTWMQ9PdnGGlwX#now};Dl?JAF4KSC6!tOjvJsUW0 z72H)|G8Bntp|3!AHs|{4dx%cR1PbYd-Pw+E9)f+q{dOzswsyyN2{Czwz_p>3a!j)% zoDV+ds=ndv!bC=|$-U@8(N&R^2BvEbFt>)n?z}}k$v0Cf8~*}uBb3Q0L?(Z?0M}h{?YR{4*Q|o}tXM9~=PRf}`OV za2sf&lqukEGy7}MRjsWwP-$Sg)&OhPP}!YJs4ICMgzNtO8}KhEl1W6Y=*_{Ey9rw zTxp=vz_hFZ)~%tkJ3e39SY6`EYA^+g#67>yrV{nzE(;I9VC5VN=#<^@UCy!K*=DHa z5h`32rsd&T^{vuCrGaTs1FT!!usc2@^WDcW;P+c{6x4oSh<{%AD!6WkG*QhHNn2c>graQI`g^X?9Xtw1}Y6y8W?H~uoiaB?lkKQ zb^CjiCBff?##oy0IiXomReYs^N&}S!Dh>3B23XUF)9$Q9{nvqiiy(&I!1+F=PqbMz zv(iANfl33F2AXMrHGMek&RFWd1IomA^VPqp)$B%A@s$QD4OANF6AiGY52xLki~27t zGdjdw3d8d6gZ9ZSteRPApwd94fxglJYx;279sd^Dkx=%Ve4n)~-B(Jj8e3_g(mP-$RDG|&Tf z$KU6i3$MV-5ez>Ml7A-lh>cl@?s1^768EP~2jgNi6RNfEU}v*-QNWnomGZAl|uGtp8qzy>@v079W`p z6JLL4q{Yg4B`)GR`^z^@V!Hh=tox$Q%zO&2Fla8fs{hi|=t)8_n@f%<`?^zWCrvNV6oh0EG}BagP>^wUahzCGTg>i62#k&TMwG72uij+N=ab|@p- z1q>}W+&k8Ba4_x@3+q zE0Vq|_aW*VZAtcDN58!IB@@8hJB5VdZ_9)utulIeI4I2j*5U;g8_T{pmcuSU*l`~Y zngR)=YJvrQtu^Ik7qwYXWx2<4i-IhNcAB`Gi&B<7BmrLxI#Oeq@NI7`RE?H*^y&`? zT#!4TgcULA6J!ta{fwFQlwl8g)t0rh!YFt%bh*Y#v*J-eg|yL-Fh@{gU9hWW!axwr zv1J1FAz)jB#j<_tO^@8-*c&c`02e<^`M;Z=g%!b6YT8Ju1iq9+>N}n)$&KXSkz%ni z?W^}QP*4uG=;LN*q`jH4>04r%wCZZqw=4i~oNcS0(B&jG6y=Wl+C}sF%q_f`GVMcs zB7?iAcIPm->ReBOo%e5^DY>WFKzrpEBUui$H4%ZmrI)LN6+G=s`aA`F3wvzFELqSl z@`sN!h1tgnU%iSMRUGM@2_=;QWIC|9YNvK1Q0P z0k}4bWZW0SF=oIT$dB9&V`O_)0JLMkwdIDFcRs!GkBW2Lq}$0adR|u_9)X{HB=FMo zAZ+30kJH%psd}4f0K+F$$Tm=~Enq6I_lMSaCtVM{AJmQTh}wLPdyZ9zG~iJ*)ONJT zb>|4ySotataJUa~ull{$lQ%>UBMlExpB}FV9ns&&NiTj5_g-4z*l9xN=DJ+oIeK$s z(*B(tF1TX?`Zm|eZYh&NzjZ~$hhJmHRE-L==TiTXyH+^yHGpmlqp89xT&9q9xolB0 zK##EM#pkPzrg<0n^kv4L&+F4_nk1a_sD~Ls%??tO<}i*R7ft9FVEMxqXs_&x z;U~CS9D={bD3hDjSvj8891h8TD&GKoD;j}86Ty!k|Zs~)i zCX*=)jNHvr-cMQy5dYRXe~F^Hc-v6WF~)lZV%{$ONy1p5agxH`_~;?xmO49R(-5|o z&#}`BO>H?M|81z}++xAbMOQ(VNxdoFInU*PajAULSM$q~c4+uW^VnGNp3-hVa(3dZ z8ds<|0%>iut+WyKaE+w?F2CguAhoHa!MK={zKu#z{OBBsc_Bk zRi=>Yx}Er3RM$_2t`f>lGgw+z5O&;P@ylm3=ib@}Knxp<++44_aG~z&oEFKNGK)6u z$PcNl5ANIzyLEK00-Zw@8_3UT@W1YKa|cMiPlovVAo&+vR%=J9l9oiJBLojC%-9&0 zwx-_U>o9YJo}tHIlVqNb!!4XvXEL;pxTq+yKW!%6gVSdD5g>(H=FvTDDvPZ^1x5)$ zLJu0PJ6kZdy6r-f+#)Lm6q}tddJnP;w+^S4)Q@G2P+|&0h?gRAmCaLMXGNUS5|4Co zL#99UnzXk#sSaisUPY3&4ub1a0mTvb9D_0>xg< z)5^P&y5Lz`ea**mee@i`oy-!C0VM~+9lro~_Yr~0c2RLcMFcne?NL)?{AsoAvQU3y zO)e^PN4kK-Q{aY!Y?Pf=pq`bPa)uti*;fBXf?Qm#!&@Jea(1plNDkfTE;r!80yf|O zFx$u;w_yCD?Xk~c(g7?ug zx3W>bhvB~GbErIq@Pea=$uOb1eGP>w2>FYwt;RMjJY2!{+T^Cl&?w@pbEq0N?8xht z)5NJpN~Yovuc`&_7M?`w01 z;-JRI$-BR|&CZQ^nMWl_a7KNm@@Kx_XGA)( z>iWjTrPHK-bW2!8!jBmFG@;SN3Q^U4;92T)MIdb1Ty4#s%X%dx4DAgg?_b9j%wOuf z^vCK{|PD&y~m82#ObaNmX@~?r8h)Gw8_gpH;1@i?{lqPe|5!<4)VZ;r7#95XZ;+s%QZZ& zn=F9G*bZccZ-}Nb0BbIvd+hieJ?TFivYZeJCZe=ty2|`?X0R=J^eI+51FwMhRefCr zq2R_jum#RsYk)uRsV@Mlb2y2?&By^VSSq?oUmVEwTRj@(^vaXHW`14wtt`);k4_gR zL_OY<9}wsQP^aHslZ2nixJ~j}5Ll5SxBJa(iTDb`;1TY67f`-SAY%s7#vV9wEw2=^ zA+oBRw2p{3|nNvD34q6&D+U6#~;G~?DJ{RhgiM^1#= z77^jsE0xb3HGxR|3M1_~lJkHtp`zdLA%Pm(vFyA`9rX!lxZ2PsLsaCj%N~c9EdJ4q zj~HPtMvZH)*`;knJ_=YqSs-x6=?zlvV;OLIeDq}?_Bc!1ZD-t8cu9s-r+|LcnRA_# z0j*x+p?Si>v>Hz_@%l9r=Gh=@t7;kIjw>#;o$k9PzL70>5A%2ioI+o|e~ivOxBiDx zw>y=?PU7A6NQ@it2?KF6tR=8>Df;CR!5lTc?RWNj{#oJ65Vgrt$xNI)tdm47%lv@& zpj$DBcK@qjj??Dc%1Zm9sE9{V)cf1JXSFDBt$Buy#@C%Dh&RmD zI0Z?pgewi+WA@(a+Q${$D;pxk*4QS5Z615`ESTT1ZNdfZh!Zo&R=EH(hSd#L+*vXK z&g_UVZ|^s%2#%AjWmgK7T<}^Uk3y*T8H`Z*@1T^k$l`qK^N`j+)`M<*f8xr8V^yWv zk-)ngJufP$pJInU?Qt>07&Oy|v2C&nS->{|A>FWp@BP;Q8f2puzz0W7mmmrF03Hcc z)&Lq&9#~?cJB(x#Re{@nj;L&vkeMc_8h;9?PYC*$r#PXpq$? zo|-3X@*BfeG2?z6R8Q33i(THTX}F91^{Uo!HsJ9)>Zg$JX95OTL5(&Za`%>`N&Wtc zIZA9}ge=YYkcw}fO`C&VCC%3zo@Uxg7$L25``85P?S<0)@m;$d zcZddMhmWUnSV@p&#TBrx`i70^ z?@2!~*4?9lb$zqM&216bnXg0KKA8t;t3MZW%SGe}@aK3U&W{nuUrDhMzZeid1eL~~ zh28@OXKNoQABm91pWG5dKtQ+g)hu)7g*aqnbs{i6woU5Z_MMon_Fqjdl^ge{(>oRV z*n!Iun<8t#AQ2Z<*tW3f{q>hUL*KBFl>;SHY{42O_T2s_ZLflo+yr9yUYKyZ6aBQp zXG-iZpHq;q!=lOJaxuqQuyHwXtE(O9QtvjYr00Eu)bC>MwowHxR82IrNE^{fZ1YdO z()2X9H+dGklQi<#S=2#FZ+Ncs9K}VO6nB_4(tHhI6hwsY2v_31quDunE^E!}MlULy%8@UKQcsRba(RIR9YxuN*mW>}{#|7MY^- z{xVkk>ix+EV94581Q^}rfVc9a@lN&>~#czynNW$&NoT=yleK4soA04U#h^{T^`_D zl%iw~KWum&)C&K!Ge=nX#2ujK!)qa$&2RDMd(vd#JY$vPQ%X~n(ciXz3qyYF$IPyB zC2nqr3~_Io=IzQ`3a+^5veJ{)u&qbFMs4+)3r;!Hoc}a*ZZN%Bd8d?KFPK^OxGZU6 zu2N7~5n62GMZQeN4^nGju_rPzpzKMHx|M*^Na7S>#H+Y?w`?NUnOAYtPklW0Z+kU} zixM@eeRA7C=yAJz^h{Bylo>8W?}be;#XtJy z!Fd#ie~h)=wEiwpZxsQouZc$Jz~rqX{$3oj>3VJY1!{4Z;{BrvK9CN^XJoV=I!k9tj{O zfkfZlIPW2h`d_!3n3zqGy?H3hGJJf~9)M{z!b(JMTk4X*1{!Fr7srA)qLmume=+H7 znts@BLt?H6M2D4n?+QOTe+)f_T4DdALAqA&G|13IU$ulJOhwAVSaPqOl#ZfAQGW|2(SUUkE3 z5=t`%8Puk;^OeAfidXJu<`wMBD#7Lo)FT{i7*CT7ujCIhuL=!sW{xJH(DoE>6DtiAT1z{N_NJ3Xao1HUNB4llI{AA3MjAq zrAzhyWF#SJetzGM2o^fCmnsL(d7OFQ0vD&Y z_(V;%R&+3|%MTsYVf478d-noUzne@@S_SG|a}Gce6%n(AYV%-pbB}eC{rBZ-oD=;P zCQv58tKH8fQYtB@JD$z43jz@&tqsnRl&_rqc8*>#yg7CAr0%;#Xn2zucvaOf#B?j0 z2uAAf81=;Dc|tTF9&S@?Rq?#5nYaCs`h=hYAzb#nMJ;Usa+len{_uC;#N}8Pmqvk< zZV)RVj+&TR*aLq)Y`CV83ZuCw8*)`?GSzU}E6#gOe+>4nAUko?kH@+=2l__P)Ga{ zc*AqAq3-%Q2c)5li( zMI%6Xh45JrlJbyZb8s(G?eG`;9ME1we6B^te@JPZRy`cKekR;bV|)pGtia}i$LCwv z$w0;rYYm1fflTem4d^PmD^U4WoOi|mJ|Qt7O40RML`crym;&R>8XM)buEtlsR_ju- z79io~eGcqg7XW5b_cWGog)O_<`%q=R>J@JON5ZOq3g;Ft4ZW&|MRtzCDhQ&FUM&eO z<5qo$VMGiT^9zGB9uGmUGIUhyBjxB2Sw4;VOVN}X$>H8Y#?@ZFVDDPag=1}hNXrt3 z_d>D6eAU8CaPS)M4^~?{zdDSfe(7*wD2VHKLC9eTM&dz+a_WeuJiNm}l$WILY3PS> z?tM3D;}O~uX!%e$tFAK53tik%7y7ujgPeyRIUHqk{+0Y&o>p|~r_ZPxu_Of7ff<}8 z?PnDlXt+5)sbe2(S8YX@#)X=Qe#_}pTv!7ck1=l_~;IsSV7#whwxj;%#4y?k$=1T@Iv zB|XU|Qa*j_q|J``Rn30{z0GpFheU}JKO_3*)!$Z#Bi^@qLzE0VK)R9kxC?8&JHpHn z_N1UGiNex{KwY=W0YwJ9(eS~kbP0j2i?+d&Gt+01xnmE5MHwlV=odCTeA1Mf?+m?M5SMffJ~wyGR8gj1xk*L-)vn&Bfd zm9F;6`oEzbsGda*XkQ~*n{~J|$+!#`cZTpXY^W8}r6EgN%(bSOtip-8i=jIXEs-+1 zdf`wpw`ZF#42c6lU^DR75cDW+onQUM$f2rMLGiFThn0zT^|Pwy$v2MC1%g zk0dS`2o@2XJz81t7Ut3a-mF+(dGYp9UOF2GcIF_fbV;5j03&L7nT*s<7YscMd0hG+ zo+f#>9sJiVb6#WQOI2oJylmk8O3h2fA=dXX`%{#&gGaM`n<54B(RZgG8OB>CV$kG4pn`Z?29*wf>e?wt;XXnu6EoHUWwWhb@xeg1CB69_2`0> zTbN;a#=%fH+NKOYWf$11x5<>K6{%9#2P5P+pRc%KYW$&KB6PPpzVh>G#_R}{QFF~ebcpj{;&QLE*~9g20Kjwo@H{DMmZzu;ojJN_vyu84$3fEZWpuEtghRBmcL ztV%+D;7x7)12Bqh)SJ%!Ef8X|9J$fHW@NIEh?P~aZ*4K_VEjtezIE9ry_r|lM;_2+ zcPd!Z*8Ivpo_>$PV}Go3J&emCU;tGJG9lrVs6W zmxXHId)89NUuHib<l)3jd>8K?c z*!YC;J}D`QH|+Y@{*{!r(Gs^e;NqXDZ*0X0$JJlTkFNa6fj8haZL$Q%s~!hSp00rI zB{?=co1W`+V|tvhRA8KP;g-OjJ)F4%@@mK`kSx!8@Q5w^m8R{?h)oBn|68QDO|3h0 zjhW1jJsagCA-D0w%Uf%QWenro;bU967B>?E^Tn(&|3?0o!DST$B(S)0ZQ_lv8_muNt56!z$#$IZ(H0>(;A=WABk8g^muT;?>VgbOP$Z!NpA z`(f-lofAaiQeF}wyhz@~IrCpHjNkDTEYqpJS$9CPekFimX+K8HMWhdHz^KE6L z7rnt`A%@nf^@n)=Gaw&woz#LyoUi@1aNgmNtx#u$aKRL%lz0-AJQ9w{GI9%%o0_kF z&N*#lHQeYq1GQMD`br4?iQX-9n-GMtLQ+P!fqR+6Y<#o)hJ&(H!0_X^THL?RPEJm@ z&Mji@aU~ZuoFmq^*@)tSuj|AM@w%5fDg}vUA zo24*s!Jgl9k`9C>JbyJSPOwxN1PN5kO~@!vL$(5rbG69b*1+=icjWa_TmpuM%`UM%)0>JqGxAe_M;LfS#lA_?Er@|DuF|8M~cumbo_`3&9gmpZ)O@=+=$w3(8{R4p$J zba~d%bf(Jl2f9?2({TbBc_<`&(c61aBx-MvXm%S8ji7r}UF1!MV|;VivbHbR`^~CP853SK^(b+RS z0(n)-;hjC>Kf$PADfu+_!$5(de z=N7=J)52!=##*M}MLGwpJ){P~4XY%DK47%tficUq0UtZL#*$1yrlW!o1r7w!6&lq; zgSfeCd)*{-ff9;VOp22_;zKlhrbT1#y{1@o`qUDHh z1%H8{O{os%?oL4;KnZ56veG13*bD%~oHkzPOU6dZp4+lr|FWhXt_c_gAP5}2>9FeTzhV3s4quxN z)4;n5A7PG50z{hzejBg*t)fhi-g?;^BipBNd}mYzUQ$WC$#y$qEzCvzy`4<_nK^wI zdF=gIt}R_@KU4iIfIqH14z}JKSL+#FCy_dSKA2=gL!m^42l=PW?=RTS*t8%aOhKuQ35!+*dc&lNi722-*yxS-`GWJy4*l zbndR8Z7w*{?*QWYuIbJgnNnSxZaJxJ=Tytu#g}fohD`M1WNwfg44LB};m-?WWm}{U zORDN#3t91>+=Z)k8b+FE7Y?vFLgVi}l$mSWZ8Jc|)uW3Ch`eSXc9+%Y_+c)WZ(@a7 zuaDF@rB?pvaIUSw4N7)(&YJ9v;9uMw>diV`4O!Qr?}u%@11Dw&9p_$tL`THNPPLB8 zBn})wz6}+z&?IS_^JCA3_Q5ZwuGQIlqA<;?-E$tZJav{QqOS0V-Cb%{vA568jG&tF zL##GQDXL#qtA({z=_wYQz} z%##e4ac6d$pAiCBRV5s+Bq}^lL7mFDT@(3Om`G?+Tf0$IcN2GoIhxe7P5k4rbx_mx ztPOs>#ZfDG8?B8F$V)+hNy!?d1tvBp-RJH#`?KgrrO0Bg)#`#Q=7pK(pskEDwj&yk z>u1XMISGP1!909Ds23^aXrxK`(anw0w(p^{)U4STcW3Q?Zgk;migOEw+J155Z6pj4 z;2XvEnPYXD<7LM{jh`Jn$bw>UF!yeZf1c;L-h%+YCk8}2DEr2}wdvi0KM8ZtIi5Mf zp3l${^o*Z_oerS`YumjTdJ=;=|1DZ&SHh}R^^w_{p;1Oi({ zUW1k6*Ii~~S3^yAJ1ZgDSyTNm@1dWWo5D5~hh^1=mq^uhztf*P?eO+kN>K;v-4;+e zA+ayF%N+(9J}(5qIB0#8QNs<8VF$ccXpd{tA{MZ9SbfI#W4hu^@-qppn7wZ%mOH1% zG*`Z;$rDr`W+I9o?31NXnTopGRlj+~F^Zp#9XWIaEo}z`t)vb%Kft_q+>;g>{QAo( ztDH#&gg24pF%tL*z2?NbqFw(Q0Ex#IwT5qD9F0BN0*mC zVR!Z6)cfGiD{C-V`&i1MiuA5DfgL=RDF5&a_2X>miUe#||F=)&5~c#>il`UczT9w= z@}krHGLJ+|b71(tAX)oNl_$(o4)pSOvMowSD$?|`wAd$drC#=>bTJi@_XM)|g5{=& zw1?l`9IPR;AKIrq7HdS5(~l3khR6`Y8FiucA33LR-!GBzNbUE&k`I0_<3v?D>?STs z;K}LO67K~=L1GX&C0yAyH(WMydqL3vS~=dnWpQQ*qL$Qc74kT^Ak{Ban;g5UkaPOm zzUm*bI=667RRe68wN}?{$Z>^k)Ky*RUxx7b=%FZ7JY)Y}4Au~TR-YaiE-y77E40Ofj4)^0^6{yk zFu`w>&A;D&Ob`!Gug*iUBL4Z|1@UawH-H+$IF$4OR!{Dc_pa<7DXugi8lPHk$oC+L>rWy~a18{0T~dj|}u9xbC~xdoZOh^-8s%E-VV+yGE7;u z4?b?USRo^8vX8rj*N3NcgTeQHxkL~>k3M~2yd$m4w>AvwFm-Q<`0MNt_7OU$t+9;2 zCxrYrLd|IFaLg8l$nZF`RZv>C6d7moZk~E(6;w-E$FE)}z|)glf@cH63fYi)okAm0 zhsW{ihH`Z);&agn^8m(Gik+Mfj+=m$8Wzu z^Q79)N#61Co31VTpU87xmoeQ$^M4Ze0vqJckMiOc;Sz2t{1bs&ec@O!ZnHK4FuS&2gUU&zNM%0Hp-rN@k4Y*}(sc_6KWQvKd4S$TU zPv2i6Jg{mA7y9tzhyw}2S3f00UB&^WTIpveVdLq442mo8f4w5{u8)~%N&RN$Xi?>^ zPc!*jicvw6jeK+Z4UI*&U>wi>ri68`Po#R>;F<;ad5Exmk~+z~D!dm~kbW4{)S^g~ zn)nGAh~5ml`m)`G6l(YSsDscwU>9)Mm#uNZ0~x|e=t)9+G_UU)mD|#WelO<&(aRV} z4q@ud1!^N+MB!= zr`G-{(j;`kr;7~}pDVP-rkmUEoS(&{1^H>N+z@T|Tyx8#PrFe484qvWq3jpHo%9$n zax~jwgIO}Hf!P-dfB27&6zE7paKm(qO}2J!Znu4yyTL8#JH+>v?_Nn)No?%f^Ggxb zkc8zRu5~XrbVk|p@r#4$ zCh~mAu0-^VZ10CHv`I`w%qH8yfQ&MPv4*|D)w6CrxG=(nYTB?()ej zOy=vXP-S=4Vl$ukdW$=sRmdZ20798ibu!|}LYqyVH2{!(|PaJwx0Nl>pgE-44KXU zvL#>1ZJ$upE0F`e*QwT-Cm5Y%n0aQrmu7NhRzlTR;=ZKi&Biy=(eedvv-Ht)Zhn?#$T>_5HNfGlo2c)B>T zvcgDAN;1-FoCBX~prwgA00Zk%kl~7m;lC-Z8mZ&U+fA2uyg=Bi_0~sCk9!&|N>of# z7OF(wQtjDV1qXIDg!UeC^{eeE;iM!hbRNcYu20QiW3B~f31$AxfX#AgiLsu_QKygn z-Dk=B@?GCabk*)L_N}mRi-oy&MuB zGRr?wM(O?olud2BJ_oDkg=bGDX8z*T>^dY{@VQNgk>HKr)}y>eL;8hXkI#8BUxx(+ z#5Z}ybJb)hDgXyuV1Awge0pX~4LrFHZIf$rpxh9D)6q!W*>V=S7*;Er@?iBs5T{Z- zaOwECh!!~l*}LOHoX%XFbnIPAOFD7SCeMHuWxm!z&SwUiPMsM#bm-Y0No{Q8b9mM` z1J?iW@rU9&tTyLh&*`xnTlA-v(uH#D38a!4raIJ#bjgwLQ6Lcf^5LzJdG0&~|NGJf zMeaVKA=6m%t%$K~I&7?sUzqeC!+*D>UxPy0KU_n(U}pXhw!Sv%;=EnQ8)xwI2WhBbqe z^wXfKr@VKTRB#>bB6L?UC^V%`l{P$*5m%J{;nf~jLn{&SD7MvlJ?z{YY8KFS_$uka zEjDra1!mhwgEuEtNGzk+$tm`~L6SBkO!36$IiU=7Ie37N-rD~%^BDW&e925t{W5**wSNRtN)@QDuChtOpPNot zICyj`N3l-1=d=6e0_{yMcv^F1Zdwcg+Ow8SA6}@XKr>6)*5K zyIrhq`Uy%@T(bVL?Nwm)9~*UH`XqjRz0L(%37ERp4a2U1;e$Wg0VD2?okXJflf>Vf zA}6=NVYO@C(QP#MkVnC9QtFE4oK@f`;jV{z6gVFLXDGYiq^qQAr@a(u|L|XC7l|jR zw8FVsgT)tsF2&We8Nl%r56aI!a?sEO{ZC+Qn0%zQg3Uz3*<-$4b(CF6}|5rq$>8==jleB^aUSOCaPe=B7yYHeV|=p&uLfr>F=o zWDmC zeL6@xJSr6NasdoDi5RvM-b+~|9g{jT;HsIQ6a7Eb0yd-+CH(gZ(8#;QeS`l960V;(;{N+BldAl# WZU3*j%PDxwEs^l$+!^09r~U_*!;3}$ literal 0 HcmV?d00001