From 5054560e0c6ee2c3594798cda852aad518070394 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 1 Feb 2023 19:58:40 -0600 Subject: [PATCH 001/109] imx: imx8mm-beacon: Enable FlexSPI in U-Boot In order to use the FlexSPI interface in U-Boot, configure the alias to make spi0 point to flexspi. With that enabled, sf probe detects the QSPI part as: SF: Detected n25q256ax1 with page size 256 Bytes, erase size 4 KiB, total 32 MiB Signed-off-by: Adam Ford --- arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index fd0061f00fd..00abbeb22fe 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -6,6 +6,10 @@ #include "imx8mm-u-boot.dtsi" / { + aliases { + spi0 = &flexspi; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; From cacf0f8a193c0e8bbd7db6a5c7d4c463f0600710 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 1 Feb 2023 19:58:41 -0600 Subject: [PATCH 002/109] configs: imx: imx8mm_beacon: Add config option for QSPI booting The imx8mm_beacon SOM has a QSPI part attached to the FSPI controller. Update the header and spl files to support booting from NOR flash and add imx8mm_beacon_fspi_defconfig to support this configuration. Signed-off-by: Adam Ford --- board/beacon/imx8mm/spl.c | 7 ++ configs/imx8mm_beacon_fspi_defconfig | 155 +++++++++++++++++++++++++++ include/configs/imx8mm_beacon.h | 9 ++ 3 files changed, 171 insertions(+) create mode 100644 configs/imx8mm_beacon_fspi_defconfig diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index a5f337aa17c..b2830c5223a 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -36,6 +36,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) return BOOT_DEVICE_MMC2; case USB_BOOT: return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; default: return BOOT_DEVICE_NONE; } @@ -46,6 +48,11 @@ static void spl_dram_init(void) ddr_init(&dram_timing); } +void spl_board_init(void) +{ + arch_misc_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig new file mode 100644 index 00000000000..805fd3f6715 --- /dev/null +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -0,0 +1,155 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" +CONFIG_SPL_TEXT_BASE=0x7E2000 +CONFIG_TARGET_IMX8MM_BEACON=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_LTO=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;" +CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_CRC32=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_POWER=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x800000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="FEC" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_SPL_PHY=y +CONFIG_SPL_NOP_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y +CONFIG_FSPI_CONF_HEADER=y +CONFIG_FSPI_CONF_FILE="fspi_header.bin" diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index d85ae21e231..6d70957e5ed 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,8 +9,17 @@ #include #include +#define UBOOT_ITB_OFFSET 0x57C00 +#define FSPI_CONF_BLOCK_SIZE 0x1000 +#define UBOOT_ITB_OFFSET_FSPI \ + (UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE) +#ifdef CONFIG_FSPI_CONF_HEADER +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI) +#else #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#endif #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ From ce38c6432ba02794dcbd4851d380a9a1fb5b4bdd Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 3 Apr 2023 13:14:25 +0200 Subject: [PATCH 003/109] colibri-imx8x: print firmware versions Print firmware versions during U-Boot start: BuildInfo: - SCFW f5623878, SECO-FW c9de51c0, IMX-MKIMAGE 0, ATF c6a19b1 - U-Boot 2022.04-00335-g65192567f81-dirty Signed-off-by: Andrejs Cainikovs --- board/toradex/colibri-imx8x/colibri-imx8x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 52fc7a391bb..afdd24a5f42 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -170,6 +170,8 @@ int board_late_init(void) env_set("board_rev", "v1.0"); #endif + build_info(); + select_dt_from_module_version(); return 0; From 04e08e3c549d065bd49e3d5c23a944a4e0da0a0a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 6 Apr 2023 18:17:13 +0200 Subject: [PATCH 004/109] arm: mx6: module_fuse: fix build failure due to wrong argument name nodeoff variable should be variable off returned by fdt_path_offset() so let's rename it to off. Signed-off-by: Giulio Benetti Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/mx6/module_fuse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 0f4565e3117..b58f11c1e56 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -206,7 +206,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) if (off < 0) continue; /* Not found, skip it */ add_status: - rc = fdt_setprop(blob, nodeoff, "status", status, + rc = fdt_setprop(blob, off, "status", status, strlen(status) + 1); if (rc) { if (rc == -FDT_ERR_NOSPACE) { From d31ffce81db8a5a5687cf13d00cf9ecf2805f658 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Tue, 11 Apr 2023 20:27:41 +0300 Subject: [PATCH 005/109] ARM: imx9: support env in fat and ext4 Change boot device logic to also allow environment stored in fat and in ext4 when booting from SD or eMMC. As the boot device check for SD and for eMMC was depending on ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location to use IS_ENABLED instead for all modes, returning NOWHERE when no valid mode is found. This solution is based on (with added SPL support): Link: https://lore.kernel.org/all/20211020191626.3648540-1-ricardo@foundries.io/ Signed-off-by: Oleksandr Suvorov Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx9/soc.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 64e8ac610e5..a0565f3aea0 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -600,35 +600,31 @@ int timer_init(void) enum env_location env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); - enum env_location env_loc = ENVL_UNKNOWN; if (prio) - return env_loc; + return ENVL_UNKNOWN; switch (dev) { -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) case QSPI_BOOT: - env_loc = ENVL_SPI_FLASH; - break; -#endif -#if defined(CONFIG_ENV_IS_IN_MMC) + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + return ENVL_NOWHERE; case SD1_BOOT: case SD2_BOOT: case SD3_BOOT: case MMC1_BOOT: case MMC2_BOOT: case MMC3_BOOT: - env_loc = ENVL_MMC; - break; -#endif + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)) + return ENVL_EXT4; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) + return ENVL_FAT; + return ENVL_NOWHERE; default: -#if defined(CONFIG_ENV_IS_NOWHERE) - env_loc = ENVL_NOWHERE; -#endif - break; + return ENVL_NOWHERE; } - - return env_loc; } static int mix_power_init(enum mix_power_domain pd) From 7a63432e9d1b474a9bffb814b4e08e338256989c Mon Sep 17 00:00:00 2001 From: Sergio Prado Date: Tue, 2 May 2023 10:57:50 +0200 Subject: [PATCH 006/109] configs: verdin-imx8mp: enable ARCH_MISC_INIT This is required to boot a FIT image, otherwise the caam_jr driver is not initialized and the hash verification fails with the following error: Verifying Hash Integrity ... sha256dev_get_priv: null device CAAM was not setup properly or it is faulty Signed-off-by: Sergio Prado Signed-off-by: Marcel Ziswiler --- configs/verdin-imx8mp_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index f1fa2b8f496..faf57fd473e 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -42,6 +42,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-verdin-${variant}-${ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 From 8849cc7bd9925ad31193ad2f6e3f172d3d8953ed Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2023 10:44:44 -0700 Subject: [PATCH 007/109] board: gateworks: venice: add GPIO name lookup Add GPIO name lookup so that you can act on GPIO's by name vs controller id: Before: u-boot=> gpio input pci_wdis# GPIO: 'pci_wdis#' not found Command 'gpio' failed: Error -22 After: u-boot=> gpio input pci_wdis# gpio: pin pci_wdis# (gpio 103) value is 1 Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 9d0d0ee315e..2e729923af9 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -89,6 +89,7 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 3974a384d1e..dc0bb01976d 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -90,6 +90,7 @@ CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index a6f6ec67c52..3f68900fbe7 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -87,6 +87,7 @@ CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y From c226f84256e6c8c917f253a98ca444439bf605cf Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2023 10:45:54 -0700 Subject: [PATCH 008/109] board: gateworks: venice: add eraseenv command Add eraseenv command and remove the unnecessary env command. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- board/gateworks/venice/venice.env | 1 - configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 4 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/gateworks/venice/venice.env b/board/gateworks/venice/venice.env index f81804ca12c..2054c029a3e 100644 --- a/board/gateworks/venice/venice.env +++ b/board/gateworks/venice/venice.env @@ -31,4 +31,3 @@ update_rootfs=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize 100000 1000000 update_all=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize -erase_env=mmc dev $dev; mmc erase 0x7f08 0x40 diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 2e729923af9..5bf93db8377 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index dc0bb01976d..8a0b8c2db48 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 3f68900fbe7..f8e4a8415d8 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y From 8236c05ddb2a86080a1748c333764dd50013774b Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2023 17:05:53 -0700 Subject: [PATCH 009/109] board: gateworks: venice: dynamically determine U-Boot raw sector CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to adjust for IMX8MN and IMX8MP when booting from an eMMC boot partition due to IMX BOOTROM v2 using an SPL offset of 0 for boot partitions and 32K for the user partition. In order to allow the same firmware to run on both user and boot hardware partitions adjust raw_sect dynamically at runtime. Signed-off-by: Tim Harvey --- board/gateworks/venice/spl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 4eb7bdfcee6..50056da3ee0 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -327,6 +327,21 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) } } +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) +{ + if (!IS_SD(mmc)) { + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: + case 2: + if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) + raw_sect -= 32 * 2; + break; + } + } + + return raw_sect; +} + const char *spl_board_loader_name(u32 boot_device) { switch (boot_device) { From 2c2cc1eaabc7b4bb5af66830c59a810e97280545 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2023 17:05:54 -0700 Subject: [PATCH 010/109] board: gateworks: venice: dynamically determine U-Boot env partition Determine the U-Boot env hardware partition depending on the boot device. This allows the same boot firmware image to be placed on user, boot0, or boot1 without changing CONFIG_SYS_MMC_ENV_PART. Signed-off-by: Tim Harvey --- board/gateworks/venice/venice.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index ca62f0be6d2..7aca7550384 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -139,6 +140,20 @@ int board_mmc_get_env_dev(int devno) return devno; } +uint mmc_get_env_part(struct mmc *mmc) +{ + if (!IS_SD(mmc)) { + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: + return 1; + case 2: + return 2; + } + } + + return 0; +} + int ft_board_setup(void *fdt, struct bd_info *bd) { const char *base_model = eeprom_get_baseboard_model(); From 7b39e5b53a88f973da08e2f8d3e1161e51a77ed4 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2023 17:05:55 -0700 Subject: [PATCH 011/109] board: gateworks: venice: dynamically update the update_firmware script The update_firmware script is intended to update the boot firmware but the details including the offset and hardware partition are dependent on the boot device. Specifically: - IMX8MM/IMX8MP (BOOTROM v2) the offset is 32KiB for SD and eMMC user hardware partition and 0KiB for eMMC boot partitions. - IMX8MM the offset is 33KiB for SD and eMMC regardless of hardware partition. Dynamically set soc, dev, bootpart, and bootblk env vars at runtime and use these in the update_firmware script. Remove the splblk env var from config files as its no longer needed. Signed-off-by: Tim Harvey --- board/gateworks/venice/venice.c | 71 +++++++++++++++++++++++++++++++ board/gateworks/venice/venice.env | 6 +-- include/configs/imx8mm_venice.h | 1 - include/configs/imx8mn_venice.h | 1 - include/configs/imx8mp_venice.h | 1 - 5 files changed, 74 insertions(+), 6 deletions(-) diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 7aca7550384..803582c55b9 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -6,10 +6,12 @@ #include #include #include +#include #include #include #include #include +#include #include "eeprom.h" @@ -94,10 +96,12 @@ int board_init(void) int board_late_init(void) { const char *str; + struct mmc *mmc = NULL; char env[32]; int ret, i; u8 enetaddr[6]; char fdt[64]; + int bootdev; /* Set board serial/model */ if (!env_get("serial#")) @@ -132,6 +136,73 @@ int board_late_init(void) i++; } while (!ret); + /* + * set bootdev/bootblk/bootpart (used in firmware_update script) + * dynamically depending on boot device and SoC + */ + bootdev = -1; + switch (get_boot_device()) { + case SD1_BOOT: + case MMC1_BOOT: /* SDHC1 */ + bootdev = 0; + break; + case SD2_BOOT: + case MMC2_BOOT: /* SDHC2 */ + bootdev = 1; + break; + case SD3_BOOT: + case MMC3_BOOT: /* SDHC3 */ + bootdev = 2; + break; + default: + break; + } + if (bootdev != -1) + mmc = find_mmc_device(bootdev); + if (mmc) { + int bootblk; + + if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) + bootblk = 32 * SZ_1K / 512; + else + bootblk = 33 * SZ_1K / 512; + mmc_init(mmc); + if (!IS_SD(mmc)) { + int bootpart; + + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: /* boot0 */ + bootpart = 1; + break; + case 2: /* boot1 */ + bootpart = 2; + break; + case 7: /* user */ + default: + bootpart = 0; + break; + } + /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */ + if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) && + (bootpart == 1 || bootpart == 2)) + bootblk = 0; + env_set_hex("bootpart", bootpart); + env_set_hex("bootblk", bootblk); + } else { /* SD */ + env_set("bootpart", ""); + env_set_hex("bootblk", bootblk); + } + env_set_hex("dev", bootdev); + } + + /* override soc=imx8m to provide a more specific soc name */ + if (IS_ENABLED(CONFIG_IMX8MN)) + env_set("soc", "imx8mn"); + else if (IS_ENABLED(CONFIG_IMX8MP)) + env_set("soc", "imx8mp"); + else if (IS_ENABLED(CONFIG_IMX8MM)) + env_set("soc", "imx8mm"); + return 0; } diff --git a/board/gateworks/venice/venice.env b/board/gateworks/venice/venice.env index 2054c029a3e..a0d6c43325c 100644 --- a/board/gateworks/venice/venice.env +++ b/board/gateworks/venice/venice.env @@ -8,11 +8,11 @@ bootm_size=0x10000000 dev=2 preboot=gsc wd-disable console=ttymxc1,115200 -update_firmware=tftpboot $loadaddr $image && +update_firmware=tftpboot $loadaddr $dir/venice-$soc-flash.bin && setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 && - mmc dev $dev && - mmc write $loadaddr $splblk $blkcnt + mmc dev $dev $bootpart && + mmc write $loadaddr $bootblk $blkcnt loadfdt=if $fsload $fdt_addr_r $dir/$fdt_file1; then echo loaded $fdt_file1; elif $fsload $fdt_addr_r $dir/$fdt_file2; diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 5579a05d165..b33b8283085 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -26,7 +26,6 @@ func(DHCP, dhcp, na) #include #define CFG_EXTRA_ENV_SETTINGS \ - "splblk=0x42\0" \ BOOTENV #define CFG_SYS_INIT_RAM_ADDR 0x40000000 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 80c2df9f30f..3db997e9e7f 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -20,7 +20,6 @@ func(DHCP, dhcp, na) #include #define CFG_EXTRA_ENV_SETTINGS \ - "splblk=0x40\0" \ BOOTENV #define CFG_SYS_INIT_RAM_ADDR 0x40000000 diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 4b32d5a77ef..b5ee8c98fbb 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -20,7 +20,6 @@ func(DHCP, dhcp, na) #include #define CFG_EXTRA_ENV_SETTINGS \ - "splblk=0x40\0" \ BOOTENV #define CFG_SYS_INIT_RAM_ADDR 0x40000000 From 13897ff6d9f341ff70f7e1765562b9ae7a66e521 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2023 17:05:56 -0700 Subject: [PATCH 012/109] board: gateworks: venice: move env location To allow U-Boot to fit within emmc boot partitions move the env from just under 16MiB to just under 4MiB as some emmc devices used on venice boards have 4MiB boot partitions. This still leaves plenty of room for U-Boot. Signed-off-by: Tim Harvey --- configs/imx8mm_venice_defconfig | 4 ++-- configs/imx8mn_venice_defconfig | 4 ++-- configs/imx8mp_venice_defconfig | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 5bf93db8377..e533a40f24a 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_OFFSET=0xff0000 +CONFIG_ENV_OFFSET=0x3f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice" CONFIG_SPL_TEXT_BASE=0x7E1000 @@ -19,7 +19,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xff8000 +CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 8a0b8c2db48..c066f6d8ba0 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_OFFSET=0xff0000 +CONFIG_ENV_OFFSET=0x3f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mn-venice" CONFIG_SPL_TEXT_BASE=0x912000 @@ -19,7 +19,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xff8000 +CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index f8e4a8415d8..f9065e7bf09 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_OFFSET=0xff0000 +CONFIG_ENV_OFFSET=0x3f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-venice" CONFIG_SPL_TEXT_BASE=0x920000 @@ -19,7 +19,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xff8000 +CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SYS_MEMTEST_START=0x40000000 From 79e315761c5c3dbbfe457edfe421932f40d88520 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 May 2023 17:05:57 -0700 Subject: [PATCH 013/109] board: gateworks: venice: update board doc to show other emmc parts Update the venice board documentation to show how to install to the various eMMC hardware partitions available as the same binary firmware can be placed in either user/boot0/boot1 without build-time config changes. Note that the boot offsets differ depending on the SoC and the eMMC hardware partition. Signed-off-by: Tim Harvey --- doc/board/gateworks/imx8mm_venice.rst | 4 +++- doc/board/gateworks/imx8mn_venice.rst | 4 +++- doc/board/gateworks/imx8mp_venice.rst | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/doc/board/gateworks/imx8mm_venice.rst b/doc/board/gateworks/imx8mm_venice.rst index f1e7e499445..ea78dfd7ae6 100644 --- a/doc/board/gateworks/imx8mm_venice.rst +++ b/doc/board/gateworks/imx8mm_venice.rst @@ -47,4 +47,6 @@ Update eMMC => tftpboot $loadaddr flash.bin => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 - => mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt + => mmc dev 2 0 && mmc write $loadaddr 0x42 $blkcnt # emmc user hw part + => mmc dev 2 1 && mmc write $loadaddr 0x42 $blkcnt # or emmc boot0 hw part + => mmc dev 2 2 && mmc write $loadaddr 0x42 $blkcnt # or emmc boot1 hw part diff --git a/doc/board/gateworks/imx8mn_venice.rst b/doc/board/gateworks/imx8mn_venice.rst index 7ba953a4a85..7015f4ef31c 100644 --- a/doc/board/gateworks/imx8mn_venice.rst +++ b/doc/board/gateworks/imx8mn_venice.rst @@ -47,4 +47,6 @@ Update eMMC => tftpboot $loadaddr flash.bin => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 - => mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt + => mmc dev 2 0 && mmc write $loadaddr 0x40 $blkcnt # emmc user hw part + => mmc dev 2 1 && mmc write $loadaddr 0 $blkcnt # or emmc boot0 hw part + => mmc dev 2 2 && mmc write $loadaddr 0 $blkcnt # or emmc boot1 hw part diff --git a/doc/board/gateworks/imx8mp_venice.rst b/doc/board/gateworks/imx8mp_venice.rst index 632cd742d1f..a219caadff2 100644 --- a/doc/board/gateworks/imx8mp_venice.rst +++ b/doc/board/gateworks/imx8mp_venice.rst @@ -47,4 +47,6 @@ Update eMMC => tftpboot $loadaddr flash.bin => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 - => mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt + => mmc dev 2 0 && mmc write $loadaddr 0x40 $blkcnt # emmc user hw part + => mmc dev 2 1 && mmc write $loadaddr 0 $blkcnt # or emmc boot0 hw part + => mmc dev 2 2 && mmc write $loadaddr 0 $blkcnt # or emmc boot1 hw part From 8f70f3df6201f28ac0ea604840d1c0e62d521629 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 6 May 2023 13:14:02 -0300 Subject: [PATCH 014/109] power: imx8m-power-domain: Add delay to align with kernel driver In the imx8m power domain kernel driver, there is an extra udelay(5) prior to requesting the domain to power up: https://github.com/torvalds/linux/blob/v6.3/drivers/soc/imx/gpcv2.c#L347-L375 Haven't observed any issues due to the lack of this delay in U-Boot yet, but better to align it with the kernel driver implementation. Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- drivers/power/domain/imx8m-power-domain.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index 145f6ec0cd3..df5d7d69562 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -338,6 +338,9 @@ static int imx8m_power_domain_on(struct power_domain *power_domain) } } + /* delay for reset to propagate */ + udelay(5); + if (domain->bits.pxx) { /* request the domain to power up */ setbits_le32(base + regs->pup, domain->bits.pxx); From 1c3c601ac54d3e3f301f391c4aa86a891d4db6c2 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 9 May 2023 16:32:39 +0200 Subject: [PATCH 015/109] arm: mxs: Provide Kconfig option to to not use VDD5V as IMX28 PMU source This option sets the current limit for 5V source to zero, so all the PMU outputs are primarily powered from battery source (DCDC_BAT). This option may be set on systems, where the 5V is NOT supposed to be in any scenario powering the system - for example on systems where DCDC_BAT is connected to fixed and regulated 4.2V source (so the "battery" is not present). Signed-off-by: Lukasz Majewski --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++++ arch/arm/mach-imx/mxs/Kconfig | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d3..9965810ac27 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,6 +752,10 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + if (CONFIG_IS_ENABLED(MXS_PMU_MINIMAL_VDD5V_CURRENT)) + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_ILIMIT_EQ_ZERO); + mxs_power_enable_4p2(); } diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index b2026a3758a..3232b0fb677 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -51,6 +51,14 @@ endchoice config SYS_SOC default "mxs" +config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT + bool "Force minimal current draw from VDD5V by MX28 PMU" + default n + help + After setting this option, the current drawn from VDD5V + by the PMU is reduced to zero - the DCDC_BATT is used as + the main power source for PMU. + source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" From 249a3cc1afa2bc84788addac46657ca26bb555ac Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 9 May 2023 16:32:40 +0200 Subject: [PATCH 016/109] arm: mxs: Provide Kconfig option to disable battery charging at IMX28 PMU This new Kconfig option allows disabling the in-PMU battery charging block. This may be required when DCDC_BAT source is powered not from battery, but from already regulated, good quality source. Signed-off-by: Lukasz Majewski --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 7 +++++++ arch/arm/mach-imx/mxs/Kconfig | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 9965810ac27..7c584db27c9 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -756,6 +756,13 @@ static void mxs_batt_boot(void) setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ILIMIT_EQ_ZERO); + if (CONFIG_IS_ENABLED(MXS_PMU_DISABLE_BATT_CHARGE)) { + writel(POWER_CHARGE_PWD_BATTCHRG, + &power_regs->hw_power_charge_set); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_set); + } + mxs_power_enable_4p2(); } diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 3232b0fb677..f5e45ae8467 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -59,6 +59,10 @@ config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT by the PMU is reduced to zero - the DCDC_BATT is used as the main power source for PMU. +config SPL_MXS_PMU_DISABLE_BATT_CHARGE + bool "Disable Battery Charging in MX28 PMU" + default n + source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" From 79230640cb4fb780e2be9bb9a47b31976b18cac4 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 9 May 2023 16:32:41 +0200 Subject: [PATCH 017/109] arm: mxs: Provide Kconfig option to not enable 4P2 regulator in IMX28 PMU The IMX28 PMU (Power Management Unit) has a dedicated Linear Regulator to produce (by default) 4.2V output - available outside the chip as VDD_4P2. When system is supposed to not use VDD5V as a main power source - instead the DCDC_BATT is used; it is safe to disable this regulator. As the in-PMU DCDC switching regulator (from which DCDC_VDDA, DCDC_VDDIO and DCDC_VDDD are generated) can be driven from DCDC_BATT or output of this 4P2 regulator - by disabling the latter the use of the DCDC_BATT is forced. To be more specific - according to NXP's AN4199 the DCDC_BATT source is preferred (over VDD5V), as more efficient and stable source for industrial applications. Signed-off-by: Lukasz Majewski --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 3 ++- arch/arm/mach-imx/mxs/Kconfig | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 7c584db27c9..24f61b4b56c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -763,7 +763,8 @@ static void mxs_batt_boot(void) &power_regs->hw_power_5vctrl_set); } - mxs_power_enable_4p2(); + if (CONFIG_IS_ENABLED(MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR)) + mxs_power_enable_4p2(); } /** diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index f5e45ae8467..5cffc26103a 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -63,6 +63,13 @@ config SPL_MXS_PMU_DISABLE_BATT_CHARGE bool "Disable Battery Charging in MX28 PMU" default n +config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR + bool "Enable the 4P2 linear regulator in MX28 PMU" + default y + help + This option enables the 4P2 linear regulator (derived + from VDD5V) - so the VDD4P2 power source is operational. + source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" From 301c6e6e691fef88fe2f3ff24d4c9d05f2a5b409 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 9 May 2023 16:32:42 +0200 Subject: [PATCH 018/109] arm: mxs: Add function to dump PMU registers This commit provides function, which when debugging output is enabled dumps the IMX28 PMU registers. Signed-off-by: Lukasz Majewski --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 24f61b4b56c..7ea029e3712 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -41,6 +41,29 @@ static void mxs_power_clock2xtal(void) &clkctrl_regs->hw_clkctrl_clkseq_set); } +static void mxs_power_regs_dump(void) +{ + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; + + debug("ctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_ctrl)); + debug("5vctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_5vctrl)); + debug("minpwr:\t\t 0x%x\n", readl(&power_regs->hw_power_minpwr)); + debug("charge:\t\t 0x%x\n", readl(&power_regs->hw_power_charge)); + debug("vddctrl:\t 0x%x\n", readl(&power_regs->hw_power_vdddctrl)); + debug("vddactrl:\t 0x%x\n", readl(&power_regs->hw_power_vddactrl)); + debug("vddioctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddioctrl)); + debug("vddmemctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddmemctrl)); + debug("dcdc4p2:\t 0x%x\n", readl(&power_regs->hw_power_dcdc4p2)); + debug("misc:\t\t 0x%x\n", readl(&power_regs->hw_power_misc)); + debug("dclimits:\t 0x%x\n", readl(&power_regs->hw_power_dclimits)); + debug("loopctrl:\t 0x%x\n", readl(&power_regs->hw_power_loopctrl)); + debug("sts:\t\t 0x%x\n", readl(&power_regs->hw_power_sts)); + debug("speed:\t\t 0x%x\n", readl(&power_regs->hw_power_speed)); + debug("battmonitor:\t 0x%x\n", + readl(&power_regs->hw_power_battmonitor)); +} + /** * mxs_power_clock2pll() - Switch CPU core clock source to PLL * @@ -1280,6 +1303,7 @@ void mxs_power_init(void) POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); + mxs_power_regs_dump(); early_delay(1000); } From e7c1c0811bc27ff246864773f1aecd4f9200bed8 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 9 May 2023 16:32:43 +0200 Subject: [PATCH 019/109] arm: config: Adjust imx287 based XEA board PMU configuration This patch adjusts XEA's PMU setup as this board is supposed to be mainly powered from DCDC_BATT source. Moreover, in this HW design the VDD_4P2 is not used as well. Signed-off-by: Lukasz Majewski --- configs/imx28_xea_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 06dd6b1f0ed..6469e596141 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -14,6 +14,9 @@ CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="imx28-xea" CONFIG_SPL_TEXT_BASE=0x1000 CONFIG_TARGET_XEA=y +CONFIG_SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT=y +CONFIG_SPL_MXS_PMU_DISABLE_BATT_CHARGE=y +# CONFIG_SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR is not set CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x20000 From 611b94bf6939a2401041611795b47f27259eade9 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Mon, 15 May 2023 15:06:41 +0200 Subject: [PATCH 020/109] toradex: tdx-cfg-block: add 0070 verdin i.mx 8m plus quad sku Add new i.MX 8M Plus Quad SKU to ConfigBlock handling. 0070: Verdin iMX8M Plus Quad 8GB WB IT This SKU is identical to 0066 but supporting Industrial Temperature range. Signed-off-by: Emanuele Ghidoli Signed-off-by: Francesco Dolcini --- board/toradex/common/tdx-cfg-block.c | 1 + board/toradex/common/tdx-cfg-block.h | 2 ++ board/toradex/verdin-imx8mp/verdin-imx8mp.c | 3 ++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 11f4d5e14a8..e513f4a2919 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -139,6 +139,7 @@ const struct toradex_som toradex_modules[] = { [66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, [67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, [68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [70] = { "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, }; const char * const toradex_carrier_boards[] = { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 32e4c6f6879..45fa04ca38a 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -94,6 +94,8 @@ enum { VERDIN_IMX8MPQ_8GB_WIFI_BT, APALIS_IMX8QM_8GB_WIFI_BT_IT, VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN, + /* 69 */ + VERDIN_IMX8MPQ_8GB_WIFI_BT_IT = 70, /* 70 */ }; enum { diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 5490d3ed44a..e16a771e3ec 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -81,7 +81,8 @@ static void select_dt_from_module_version(void) */ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) || - (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT); + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT) || + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT); } if (is_wifi) From 0d30b6c4ecc4ca5c27cf441c9b5154e11fce1357 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:43 +0200 Subject: [PATCH 021/109] dts: xea: Delete not used in u-boot DTS nodes After the re-sync with Linux Kernel's DTS (SHA1: 7d08ddd09b75e7a3c103cc0d0d3ed700287f268e), the XEA's descripion has nodes and properties, which are NOT utilized in the u-boot. To avoid confusion - those are deleted. Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-xea-u-boot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi index f6488154d8d..22dd7bc8a8b 100644 --- a/arch/arm/dts/imx28-xea-u-boot.dtsi +++ b/arch/arm/dts/imx28-xea-u-boot.dtsi @@ -12,6 +12,11 @@ */ #include "imx28-u-boot.dtsi" / { + aliases { + /delete-property/ spi1; + /delete-property/ usbphy0; + /delete-property/ usbphy1; + }; apb@80000000 { bootph-pre-ram; @@ -34,6 +39,8 @@ }; &pinctrl { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; bootph-pre-ram; }; @@ -46,3 +53,12 @@ spi-max-frequency = <40000000>; bootph-pre-ram; }; + +/delete-node/ &ssp2; +/delete-node/ &usb0; +/delete-node/ &usbphy0; +/delete-node/ &usb1; +/delete-node/ &usbphy1; +/delete-node/ &hog_pins_a; +/delete-node/ &hog_pins_tiva; +/delete-node/ &hog_pins_coding; From c5e8c336ec9f1b9f3b51b631f7d127e7365a8e1e Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:44 +0200 Subject: [PATCH 022/109] dts: xea: Provide missing FEC required properties (mac0 and reg_fec_3v3) After the commit (SHA1: 7d08ddd09b75e7a3c103cc0d0d3ed700287f268e) some u-boot specific XEA FEC related properties have been replaced by ones from the Linux kernel. To be more specific - XEA board (and imx287 in general) has built L2 switch connected to FEC, which needs some special treatment. In u-boot it is handled with 'mac0' node, whereas Linux uses dedicated switch DTS node. Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-xea-u-boot.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi index 22dd7bc8a8b..9f1e261b2f5 100644 --- a/arch/arm/dts/imx28-xea-u-boot.dtsi +++ b/arch/arm/dts/imx28-xea-u-boot.dtsi @@ -38,12 +38,34 @@ bootph-pre-ram; }; +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-post-delay = <1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + &pinctrl { /delete-property/ pinctrl-names; /delete-property/ pinctrl-0; bootph-pre-ram; }; +®_fec_3v3 { + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; +}; + &ssp0 { bootph-pre-ram; }; From 11194c0d11bab4ad567af8b7a03c65e8fe3f0846 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:45 +0200 Subject: [PATCH 023/109] defconfig: xea: Change default spi-nor memory bus to 2 After the re-sync with Linux kernel (v6.0) of the XEA DTS (SHA1: 7d08ddd09b75e7a3c103cc0d0d3ed700287f268e) the alias for SPI bus, to which SPI-NOR memory is connected, has changed from 'spi3' to 'spi2'. To be in sync with current u-boot's xea dts, the default bus number (which allows running 'sf probe' without any extra parameters given) has been adjusted. Signed-off-by: Lukasz Majewski --- configs/imx28_xea_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 6469e596141..10be4af9927 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -98,7 +98,7 @@ CONFIG_MMC_MXS=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 +CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_SPANSION=y From 9c2eefaf0d15368e9ca1bb7325e2b3baa263e448 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:46 +0200 Subject: [PATCH 024/109] spl: xea: Provide stub DM driver for imx28 clocks This code fixes following WARNING: DTOC spl/dts/dt-plat.c fsl_imx28_clkctrl: WARNING: the driver fsl_imx28_clkctrl was not found in the driver list As imx28 doesn't yet support common clock framework, this prevents from DTOC warnings during SPL build. Signed-off-by: Lukasz Majewski --- board/liebherr/xea/xea.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 38e841c5f67..ed2b39f70e1 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -203,5 +203,22 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif +/* + * NOTE: + * + * IMX28 clock "stub" DM driver! + * + * Only used for SPL stage, which is NOT using DM; serial and + * eMMC configuration. + */ +static const struct udevice_id imx28_clk_ids[] = { + { .compatible = "fsl,imx28-clkctrl", }, + { } +}; +U_BOOT_DRIVER(fsl_imx28_clkctrl) = { + .name = "fsl_imx28_clkctrl", + .id = UCLASS_CLK, + .of_match = imx28_clk_ids, +}; #endif /* CONFIG_SPL_BUILD */ From 9a1efecb2c63c65c65124eb6f984f9417db0eddc Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:47 +0200 Subject: [PATCH 025/109] dts: xea: Enable debug UART support in XEA's SPL (DM_SERIAL) After enabling DM_SERIAL for XEA board, the same serial shall be used in the SPL (with SPL_OF_PLATDATA support). Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-xea-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi index 9f1e261b2f5..e40a6d240ce 100644 --- a/arch/arm/dts/imx28-xea-u-boot.dtsi +++ b/arch/arm/dts/imx28-xea-u-boot.dtsi @@ -34,6 +34,10 @@ bootph-pre-ram; }; +&duart { + bootph-pre-ram; +}; + &gpio0 { bootph-pre-ram; }; From 70b4d610f8952510a441faf89d4f6b54637ef0f4 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:48 +0200 Subject: [PATCH 026/109] dts: xea: Add u-boot specific 'type' property to duart The DM_SERIAL implicitly requires CONFIG_PL01X_SERIAL, which allows support for both serial IP block versions (i.e. PL011 and PL010). The decision about used IP block is based on the compatible string, when DM is used. In the XEA, the OF_PLATDATA is used to allow usage of serial driver in the SPL (as the size of SPL is crucial). In this case one cannot extract the type of IP block from .data field (corresponding to compatible) and it must be explicitly read at probe from dtoc generated, u-boot specific property. Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-xea-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi index e40a6d240ce..50289cf6d74 100644 --- a/arch/arm/dts/imx28-xea-u-boot.dtsi +++ b/arch/arm/dts/imx28-xea-u-boot.dtsi @@ -36,6 +36,7 @@ &duart { bootph-pre-ram; + type = <1>; /* TYPE_PL011 */ }; &gpio0 { From 01744484cbb0aeff848485b20ee567805a4ab628 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:49 +0200 Subject: [PATCH 027/109] dts: xea: Remove clocks property from debug UART on XEA The imx287 SoC doesn't support common clock framework (CCF), so the 'clocks' property is removed to avoid early (i.e. in SPL) errors when SPL_OF_PLATDATA is used. Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-xea-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi index 50289cf6d74..52fec31fbb6 100644 --- a/arch/arm/dts/imx28-xea-u-boot.dtsi +++ b/arch/arm/dts/imx28-xea-u-boot.dtsi @@ -35,6 +35,7 @@ }; &duart { + /delete-property/ clocks; bootph-pre-ram; type = <1>; /* TYPE_PL011 */ }; From b8ce78a8c9ec2b986c9fad95f3667c45d6ca4f37 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:50 +0200 Subject: [PATCH 028/109] dts: xea: Disable 'clks' node for xea (imx287) As imx28 family of SoCs is NOT supporting the Common Clock Framework (CCF) the 'clks' property shall NOT be enabled by default. Without this change u-boot proper before relocation tries to bind driver (which doesn't exists) for this device. As a result, pre-relocation DTB parsing is finished with error and the board hangs in a very early stage of u-boot proper boot process. Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-xea-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi index 52fec31fbb6..bdbeca528c6 100644 --- a/arch/arm/dts/imx28-xea-u-boot.dtsi +++ b/arch/arm/dts/imx28-xea-u-boot.dtsi @@ -32,6 +32,7 @@ &clks { bootph-pre-ram; + status = "disable"; }; &duart { From fdef5e1502a6b847acf3252c0f21739a3a4e181c Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:51 +0200 Subject: [PATCH 029/109] serial: pl01x: Change OF_CONTROL to OF_REAL Before this change, building this driver for SPL with enabled SPL_DM_SERIAL was problematic, as '-Wunused-const-variable=' warning was visible. Now, the code is only considered when u-boot proper is build. Signed-off-by: Lukasz Majewski --- drivers/serial/serial_pl01x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index f5468353e10..18332c21925 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -331,7 +331,7 @@ static const struct dm_serial_ops pl01x_serial_ops = { .setbrg = pl01x_serial_setbrg, }; -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id pl01x_serial_id[] ={ {.compatible = "arm,pl011", .data = TYPE_PL011}, {.compatible = "arm,pl010", .data = TYPE_PL010}, From 875752adc8b6a25ebaf9f45cb3fd206065a80f0e Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:52 +0200 Subject: [PATCH 030/109] serial: pl01x: Prepare the driver to support SPL_OF_PLATDATA This commit prepares the pl01x serial driver to be used with SPL_OF_PLATDATA enabled. Signed-off-by: Lukasz Majewski --- drivers/serial/serial_pl01x.c | 12 ++++++++++++ include/dm/platform_data/serial_pl01x.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 18332c21925..dbf2b2df34e 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -291,8 +291,16 @@ int pl01x_serial_probe(struct udevice *dev) struct pl01x_serial_plat *plat = dev_get_plat(dev); struct pl01x_priv *priv = dev_get_priv(dev); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_serial_pl01x *dtplat = &plat->dtplat; + + priv->regs = (struct pl01x_regs *)dtplat->reg[0]; + plat->type = dtplat->type; +#else priv->regs = (struct pl01x_regs *)plat->base; +#endif priv->type = plat->type; + if (!plat->skip_init) return pl01x_generic_serial_init(priv->regs, priv->type); else @@ -380,8 +388,10 @@ int pl01x_serial_of_to_plat(struct udevice *dev) U_BOOT_DRIVER(serial_pl01x) = { .name = "serial_pl01x", .id = UCLASS_SERIAL, +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = of_match_ptr(pl01x_serial_id), .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat), +#endif .plat_auto = sizeof(struct pl01x_serial_plat), .probe = pl01x_serial_probe, .ops = &pl01x_serial_ops, @@ -389,6 +399,8 @@ U_BOOT_DRIVER(serial_pl01x) = { .priv_auto = sizeof(struct pl01x_priv), }; +DM_DRIVER_ALIAS(serial_pl01x, arm_pl011) +DM_DRIVER_ALIAS(serial_pl01x, arm_pl010) #endif #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h index e3d4e308a14..811697ce5c6 100644 --- a/include/dm/platform_data/serial_pl01x.h +++ b/include/dm/platform_data/serial_pl01x.h @@ -20,7 +20,11 @@ enum pl01x_type { * @skip_init: Don't attempt to change port configuration (also means @clock * is ignored) */ +#include struct pl01x_serial_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_serial_pl01x dtplat; +#endif unsigned long base; enum pl01x_type type; unsigned int clock; From a21789194873d768ba829eb0169c7f0e3ceb85ef Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:53 +0200 Subject: [PATCH 031/109] serial: pl01x: Modify pending callback to test if transmit FIFO is empty Before this change the FR_TXFF (Transmit FIFO full) bit (5 in HW_UARTDBG_FR) has been used to assess if there is still data pending to be sent via UART. This approach is problematic, as it may happen that serial is in the middle of transmission (so the TX FIFO is NOT full anymore) and this test returns true infinitely. As a result, for example in _serial_flush() DM serial function we are locked in endless while(). The fix here is to test explicitly if the TX FIFO is empty. Signed-off-by: Lukasz Majewski --- drivers/serial/serial_pl01x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index dbf2b2df34e..428a4d210de 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -329,7 +329,7 @@ int pl01x_serial_pending(struct udevice *dev, bool input) if (input) return pl01x_tstc(priv->regs); else - return fr & UART_PL01x_FR_TXFF ? 0 : 1; + return fr & UART_PL01x_FR_TXFE ? 0 : 1; } static const struct dm_serial_ops pl01x_serial_ops = { From 191f683ee204c68eab2d6b28b9e4e81b1c6a0885 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:54 +0200 Subject: [PATCH 032/109] arm: mxs: Prevent serial console init when in very early SPL boot code When DM_SERIAL is enabled on mxs (i.e. imx28) platform, the console early initialization must be postponed until the driver model is correctly setup. Signed-off-by: Lukasz Majewski --- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 763d79e8036..5598c552ab9 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -128,8 +128,10 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); - mxs_spl_console_init(); - debug("SPL: Serial Console Initialised\n"); + if (!CONFIG_IS_ENABLED(DM_SERIAL)) { + mxs_spl_console_init(); + debug("SPL: Serial Console Initialised\n"); + } mxs_power_init(); From 8134853b9329e751c206b5e713e340de4e789ca2 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:55 +0200 Subject: [PATCH 033/109] arm: xea: Call spl_early_init() before DM serial console is enabled in SPL The in-spl enabled DM serial console requires the board setup to be able to parse SPL_OF_PLATDATA based serial driver (pl01x) for the imx28 based XEA board. Signed-off-by: Lukasz Majewski --- board/liebherr/xea/xea.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index ed2b39f70e1..e4d2eb65cc4 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -62,6 +62,7 @@ static void init_clocks(void) void board_init_f(ulong arg) { init_clocks(); + spl_early_init(); preloader_console_init(); } From 474c0866514677d40594490d250bc6266319bb6c Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:56 +0200 Subject: [PATCH 034/109] arm: Kconfig: Switch XEA (imx287 based) board to use CONFIG_PL01X_SERIAL The CONFIG_PL011 used by all other ARCH_MX28 based boards is not supporting DM_SERIAL. Instead, other define - namely CONFIG_PL01X_SERIAL shall be used by boards supporting DM_SERIAL. Signed-off-by: Lukasz Majewski --- arch/arm/Kconfig | 2 +- arch/arm/mach-imx/mxs/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a64780..4604d41410c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -919,7 +919,7 @@ config ARCH_MX28 bool "NXP i.MX28 family" select CPU_ARM926EJS select GPIO_EXTRA_HEADER - select PL011_SERIAL + select PL011_SERIAL if !TARGET_XEA select MACH_IMX select SUPPORT_SPL diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 5cffc26103a..b4a281e82d4 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -45,6 +45,7 @@ config TARGET_MX28EVK config TARGET_XEA bool "Support XEA" + select PL01X_SERIAL endchoice From de27953c2990944e539f503fa47281c2c72b53f6 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:57 +0200 Subject: [PATCH 035/109] config: xea: Enable DM_SERIAL for the XEA (imx287 based) board The XEA board now supports the DM_SERIAL feature in u-boot. The SPL is using the SPL_OF_PLATDATA - i.e. NOT SPL_DM_SERIAL to reduce the overall size of the SPL binary. Signed-off-by: Lukasz Majewski --- configs/imx28_xea_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 10be4af9927..c6c6a032453 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -116,7 +116,8 @@ CONFIG_PINCTRL_MXS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_CONS_INDEX=0 +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXS_SPI=y From 72235cd96ae8d61f8d9f4b669719526fc8ab0f09 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 19 May 2023 12:43:58 +0200 Subject: [PATCH 036/109] config: xea: Enable DM_SERIAL for the XEA - single binary (SB) u-boot The single binary version of u-boot for XEA board is used to debrick and factory programming. The produced u-boot.sb is a single file, which allows having fully operational u-boot prompt loaded with imx287 ROM. Signed-off-by: Lukasz Majewski --- configs/imx28_xea_sb_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index bb7bf5d9dab..a43183444d7 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -94,7 +94,9 @@ CONFIG_PINCTRL_MXS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXS_SPI=y From cb4e79b7ba9aef961e7a6549ec35467e3c1f8e85 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Mon, 22 May 2023 11:27:28 +0200 Subject: [PATCH 037/109] imx8m: soc.c: demote some printfs to debug Getting Found /vpu_g1@38300000 node Modify /vpu_g1@38300000:status disabled Found /vpu_g2@38310000 node Modify /vpu_g2@38310000:status disabled etc. on the console on every boot is needlessly verbose. Demote the "Found ..." lines to debug(), which is consistent with other instances in soc.c. Signed-off-by: Rasmus Villemoes Reviewed-by: Frieder Schrempf Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5ffdcabbb51..d5254886bed 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -737,7 +737,7 @@ static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int siz if (nodeoff < 0) continue; /* Not found, skip it */ - printf("Found %s node\n", nodes_path[i]); + debug("Found %s node\n", nodes_path[i]); add_status: rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1); @@ -1266,7 +1266,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) if (nodeoff >= 0) { const char *speed = "high-speed"; - printf("Found %s node\n", usb_dwc3_path[v]); + debug("Found %s node\n", usb_dwc3_path[v]); usb_modify_speed: From fc1b8e1e7ecd927d6f65ea2dc256f8b81134759e Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 25 May 2023 17:02:25 -0400 Subject: [PATCH 038/109] imx8mn-var-som: read and print SoM infos from eeprom on startup Enable support to read and display configuration/manufacturing infos from 4Kbit EEPROM located on SOM board. Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch. Signed-off-by: Hugo Villeneuve --- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 4 + arch/arm/dts/imx8mn-var-som.dtsi | 10 ++ arch/arm/mach-imx/imx8m/Kconfig | 2 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 134 ++++++++++++++++++ configs/imx8mn_var_som_defconfig | 1 + 5 files changed, 151 insertions(+) diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi index af80aaea0b8..7272fc2b4ca 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi @@ -68,3 +68,7 @@ &usdhc3 { bootph-pre-ram; }; + +&eeprom_som { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi index 87b5e23c766..dea9eff3f00 100644 --- a/arch/arm/dts/imx8mn-var-som.dtsi +++ b/arch/arm/dts/imx8mn-var-som.dtsi @@ -11,6 +11,10 @@ model = "Variscite VAR-SOM-MX8MN module"; compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; + aliases { + eeprom-som = &eeprom_som; + }; + chosen { stdout-path = &uart4; }; @@ -222,6 +226,12 @@ }; }; }; + + eeprom_som: eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + pagesize = <16>; + }; }; &i2c3 { diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 7639439bdc9..3450399d6fe 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -245,6 +245,8 @@ config TARGET_IMX8MN_VAR_SOM select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 + select MISC + select I2C_EEPROM config TARGET_KONTRON_PITX_IMX8M bool "Support Kontron pITX-imx8m" diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index d40f4d01761..a89457e8f57 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -1,11 +1,49 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2021 Collabora Ltd. + * Copyright 2018-2020 Variscite Ltd. + * Copyright 2023 DimOnOff Inc. */ #include +#include #include +#include +#include +#include +#include #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Optional SOM features flags. */ +#define VAR_EEPROM_F_WIFI BIT(0) +#define VAR_EEPROM_F_ETH BIT(1) /* Ethernet PHY on SOM. */ +#define VAR_EEPROM_F_AUDIO BIT(2) +#define VAR_EEPROM_F_MX8M_LVDS BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ only */ +#define VAR_EEPROM_F_MX8Q_SOC_ID BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */ +#define VAR_EEPROM_F_NAND BIT(4) + +#define VAR_IMX8_EEPROM_MAGIC 0x384D /* "8M" */ + +/* Number of DRAM adjustment tables. */ +#define DRAM_TABLES_NUM 7 + +struct var_imx8_eeprom_info { + u16 magic; + u8 partnumber[3]; /* Part number */ + u8 assembly[10]; /* Assembly number */ + u8 date[9]; /* Build date */ + u8 mac[6]; /* MAC address */ + u8 somrev; + u8 eeprom_version; + u8 features; /* SOM features */ + u8 dramsize; /* DRAM size */ + u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */ + u8 partnumber2[5]; /* Part number 2 */ +} __packed; static void setup_fec(void) { @@ -28,3 +66,99 @@ int board_mmc_get_env_dev(int devno) { return devno; } + +#if !defined(CONFIG_SPL_BUILD) + +#if defined(CONFIG_DISPLAY_BOARDINFO) + +static void display_som_infos(struct var_imx8_eeprom_info *info) +{ + char partnumber[sizeof(info->partnumber) + + sizeof(info->partnumber2) + 1]; + char assembly[sizeof(info->assembly) + 1]; + char date[sizeof(info->date) + 1]; + + /* Read first part of P/N. */ + memcpy(partnumber, info->partnumber, sizeof(info->partnumber)); + + /* Read second part of P/N. */ + if (info->eeprom_version >= 3) + memcpy(partnumber + sizeof(info->partnumber), info->partnumber2, + sizeof(info->partnumber2)); + + memcpy(assembly, info->assembly, sizeof(info->assembly)); + memcpy(date, info->date, sizeof(info->date)); + + /* Make sure strings are null terminated. */ + partnumber[sizeof(partnumber) - 1] = '\0'; + assembly[sizeof(assembly) - 1] = '\0'; + date[sizeof(date) - 1] = '\0'; + + printf("SOM board: P/N: %s, Assy: %s, Date: %s\n" + " Wifi: %s, EthPhy: %s, Rev: %d\n", + partnumber, assembly, date, + info->features & VAR_EEPROM_F_WIFI ? "yes" : "no", + info->features & VAR_EEPROM_F_ETH ? "yes" : "no", + info->somrev); +} + +static int var_read_som_eeprom(struct var_imx8_eeprom_info *info) +{ + const char *path = "eeprom-som"; + struct udevice *dev; + int ret, off; + + off = fdt_path_offset(gd->fdt_blob, path); + if (off < 0) { + pr_err("%s: fdt_path_offset() failed: %d\n", __func__, off); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + pr_err("%s: uclass_get_device_by_of_offset() failed: %d\n", + __func__, ret); + return ret; + } + + ret = i2c_eeprom_read(dev, 0, (uint8_t *)info, + sizeof(struct var_imx8_eeprom_info)); + if (ret) { + pr_err("%s: i2c_eeprom_read() failed: %d\n", __func__, ret); + return ret; + } + + if (htons(info->magic) != VAR_IMX8_EEPROM_MAGIC) { + /* Do not fail if the content is invalid */ + pr_err("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n", + htons(info->magic), VAR_IMX8_EEPROM_MAGIC); + } + + return 0; +} + +int checkboard(void) +{ + int rc; + struct var_imx8_eeprom_info *info; + + info = malloc(sizeof(struct var_imx8_eeprom_info)); + if (!info) + return -ENOMEM; + + rc = var_read_som_eeprom(info); + if (rc) + return rc; + + display_som_infos(info); + +#if defined(CONFIG_BOARD_TYPES) + gd->board_type = info->features; +#endif /* CONFIG_BOARD_TYPES */ + + return 0; +} + +#endif /* CONFIG_DISPLAY_BOARDINFO */ + +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 350c0225a69..9de7c91f1da 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" +CONFIG_BOARD_TYPES=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y From 26f4bfae73b58b412206c6f289c8cb22f974dc89 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 25 May 2023 17:02:26 -0400 Subject: [PATCH 039/109] imx8mn-var-som: fix non-applied PHY reset-gpios properties Select DM_ETH_PHY so that the reset-gpios property of the ethphy node can be used. Also select DM_PCA953X, which is needed for resetting the ethernet PHY on the carrier board via the PCA9534 I/O expander. Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did synchronise device tree with linux, which in effect removed obsolete PHY reset properties and replaced them with new mdio DM properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X. Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux") Signed-off-by: Hugo Villeneuve --- arch/arm/mach-imx/imx8m/Kconfig | 1 + configs/imx8mn_var_som_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 3450399d6fe..a940d8a9509 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -247,6 +247,7 @@ config TARGET_IMX8MN_VAR_SOM select IMX8M_DDR4 select MISC select I2C_EEPROM + select DM_ETH_PHY config TARGET_KONTRON_PITX_IMX8M bool "Support Kontron pITX-imx8m" diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 9de7c91f1da..e54c20e1531 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -77,6 +77,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y From 89bd008da43e50155d940bd02922bd87103d509f Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 25 May 2023 17:02:27 -0400 Subject: [PATCH 040/109] arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay While testing the ethernet interface on a Variscite symphony carrier board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware configuration), the ethernet PHY is not detected. The ADIN1300 datasheet indicate that the "Management interface active (t4)" state is reached at most 5ms after the reset signal is deasserted. The device tree in Variscite custom git repository uses the following property: phy-reset-post-delay = <20>; Add a new MDIO property 'reset-deassert-us' of 20ms to have the same delay inside the ethphy node. Adding this property fixes the problem with the PHY detection. Note that this SOM can also have an Atheros AR8033 PHY. In this case, a 1ms deassert delay is sufficient. Add a comment to that effect. Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board") Signed-off-by: Hugo Villeneuve --- arch/arm/dts/imx8mn-var-som.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi index dea9eff3f00..4eb578a03fc 100644 --- a/arch/arm/dts/imx8mn-var-som.dtsi +++ b/arch/arm/dts/imx8mn-var-som.dtsi @@ -102,11 +102,17 @@ #address-cells = <1>; #size-cells = <0>; - ethphy: ethernet-phy@4 { + ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */ compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + /* + * Deassert delay: + * ADIN1300 requires 5ms. + * AR8033 requires 1ms. + */ + reset-deassert-us = <20000>; }; }; }; From 2ae1267342a28aa7fa9cdf8303d81d87acf05bce Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 25 May 2023 17:02:28 -0400 Subject: [PATCH 041/109] imx8mn-var-som: read eth MAC address from EEPROM Read ethernet MAC address from EEPROM located on the SOM. Signed-off-by: Hugo Villeneuve --- arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 13 +++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi index 7272fc2b4ca..e0caf3179ea 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi @@ -13,6 +13,19 @@ bootph-pre-ram; }; +&eeprom_som { + #address-cells = <1>; + #size-cells = <1>; + eth_mac_address: eth-mac-address@19 { + reg = <0x19 0x06>; + }; +}; + +&fec1 { + nvmem-cells = <ð_mac_address>; + nvmem-cell-names = "mac-address"; +}; + &gpio1 { bootph-pre-ram; }; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index a940d8a9509..67db3e46ecd 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -248,6 +248,7 @@ config TARGET_IMX8MN_VAR_SOM select MISC select I2C_EEPROM select DM_ETH_PHY + select NVMEM config TARGET_KONTRON_PITX_IMX8M bool "Support Kontron pITX-imx8m" From b2d8d6e6251aa9dd61c735f7e88927c6fee8d8f6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 May 2023 14:18:00 -0500 Subject: [PATCH 042/109] imx: imx8mm-beacon: Move environment definition to env file Instead of cluttering up a header file with a bunch of defines, move the default environmental variables to a file called imx8mm_beacon.env and reference it from the defconfig. Signed-off-by: Adam Ford --- board/beacon/imx8mm/imx8mm_beacon.env | 19 ++++++++++ configs/imx8mm_beacon_defconfig | 1 + include/configs/imx8mm_beacon.h | 50 --------------------------- 3 files changed, 20 insertions(+), 50 deletions(-) create mode 100644 board/beacon/imx8mm/imx8mm_beacon.env diff --git a/board/beacon/imx8mm/imx8mm_beacon.env b/board/beacon/imx8mm/imx8mm_beacon.env new file mode 100644 index 00000000000..00bf67edd5b --- /dev/null +++ b/board/beacon/imx8mm/imx8mm_beacon.env @@ -0,0 +1,19 @@ +boot_fit=try +bootscript=echo Running bootscript from mmc ...; source +console=ttymxc1 +fdt_addr=0x45000000 +fdt_file=imx8mm-beacon-kit.dtb +finduuid=part uuid mmc ${mmcdev}:2 uuid +image=Image +initrd_addr=0x46000000 +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs} +mmcautodetect=yes +mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +mmcdev=1 +mmcpart=1 +netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; fi; +script=boot.scr diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index bb02b9bfcc9..52edb2ed19d 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="imx8mm_beacon" CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 6d70957e5ed..fa20651d2df 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -28,56 +28,6 @@ #endif -/* Initial environment variables */ -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=Image\0" \ - "console=ttymxc1,115200\0" \ - "fdt_addr=0x43000000\0" \ - "boot_fit=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate}" \ - " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ - "bootm ${loadaddr}; " \ - "else " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi;\0" - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 From e6ac438d166a4ca71fdcccb9fdc9a1c8abe79e44 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 May 2023 14:18:01 -0500 Subject: [PATCH 043/109] imx8m: imx8mm-beacon: Migrate README to rst Since U-Boot builds HTML documentation, migrate the contents of the README file to an rst file which can generate the proper outputs. Signed-off-by: Adam Ford --- board/beacon/imx8mm/README | 37 -------------------- doc/board/beacon/beacon-imx8mm.rst | 55 ++++++++++++++++++++++++++++++ doc/board/beacon/index.rst | 1 + 3 files changed, 56 insertions(+), 37 deletions(-) delete mode 100644 board/beacon/imx8mm/README create mode 100644 doc/board/beacon/beacon-imx8mm.rst diff --git a/board/beacon/imx8mm/README b/board/beacon/imx8mm/README deleted file mode 100644 index 32b24bc03eb..00000000000 --- a/board/beacon/imx8mm/README +++ /dev/null @@ -1,37 +0,0 @@ -U-Boot for the Beacon EmbeddedWorks Devkit - -Quick Start -=========== -- Build the ARM Trusted firmware binary -- Get ddr firmware -- Build U-Boot -- Boot - -Get and Build the ARM Trusted firmware -====================================== -Note: $(srctree) is U-Boot source directory - -$ git clone https://github.com/nxp-imx/imx-atf -$ git lf-5.10.72-2.2.0 -$ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu- -$ cp build/imx8mm/release/bl31.bin $(srctree) - -Get the DDR firmware -==================== -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin -$ chmod +x firmware-imx-8.9.bin -$ ./firmware-imx-8.9 -$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree) - -Build U-Boot -============ -$ make imx8mm_beacon_defconfig -$ make CROSS_COMPILE=aarch64-linux-gnu- - -Burn U-Boot to microSD Card -=========================== -$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 - -Boot -==== -Set Boot switch to SD boot diff --git a/doc/board/beacon/beacon-imx8mm.rst b/doc/board/beacon/beacon-imx8mm.rst new file mode 100644 index 00000000000..8bf983bff77 --- /dev/null +++ b/doc/board/beacon/beacon-imx8mm.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Beacon EmbeddedWorks i.MX8M Mini Devkit +====================================================== + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get DDR firmware +- Build U-Boot +- Burn U-Boot to microSD Card +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6 + $ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu- + $ cp build/imx8mm/release/bl31.bin ../ + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin + $ chmod +x firmware-imx-8.15.bin + $ ./firmware-imx-8.15 + $ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +------------ + +.. code-block:: bash + + $ make imx8mm_beacon_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- + +Burn U-Boot to microSD Card +--------------------------- + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +---- + +Set baseboard DIP switches for micoSD Card: +- S11 (1:8) 01101000 +- S10 (1:8) 11001000 +- S17 (1:8) 0110xxxx diff --git a/doc/board/beacon/index.rst b/doc/board/beacon/index.rst index 1fe1046a4ce..8eba5e81cdc 100644 --- a/doc/board/beacon/index.rst +++ b/doc/board/beacon/index.rst @@ -7,3 +7,4 @@ Beacon :maxdepth: 2 beacon-imx8mp + beacon-imx8mm From 7131514ca6b0202654e7a93127345b9f5530afd7 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 May 2023 14:18:02 -0500 Subject: [PATCH 044/109] imx: imx8mn-beacon: Move environment definition to env file Instead of cluttering up a header file with a bunch of defines, move the default environmental variables to a file called imx8mn_beacon.env and reference it from the defconfigs. Signed-off-by: Adam Ford --- board/beacon/imx8mn/imx8mn_beacon.env | 25 +++++++++++ configs/imx8mn_beacon_2g_defconfig | 1 + configs/imx8mn_beacon_defconfig | 1 + configs/imx8mn_beacon_fspi_defconfig | 1 + include/configs/imx8mn_beacon.h | 61 --------------------------- 5 files changed, 28 insertions(+), 61 deletions(-) create mode 100644 board/beacon/imx8mn/imx8mn_beacon.env diff --git a/board/beacon/imx8mn/imx8mn_beacon.env b/board/beacon/imx8mn/imx8mn_beacon.env new file mode 100644 index 00000000000..ca90053d477 --- /dev/null +++ b/board/beacon/imx8mn/imx8mn_beacon.env @@ -0,0 +1,25 @@ +boot_fdt=try +bootdelay=2 +bootscript=echo Running bootscript from mmc ...; source +console=ttymxc1 +fdt_addr=0x45000000 +fdt_file=imx8mn-beacon-kit.dtb +finduuid=part uuid mmc ${mmcdev}:2 uuid +image=Image +initrd_addr=0x46000000 +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage} +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs} +mmcautodetect=yes +mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else echo wait for boot; fi; +mmcdev=1 +mmcpart=1 +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else booti; fi; +ramargs=setenv bootargs console=${console},${baudrate} root=/dev/ram rw ${optargs} +ramboot=echo Booting from RAMdisk...; run loadimage; run loadfdt; fdt addr $fdt_addr; run loadramdisk; run ramargs; booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs} +ramdisk_addr=0x46000000 +ramdiskimage=rootfs.cpio.uboot +script=boot.scr diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 494085b373c..00e7cd01c27 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="imx8mn_beacon" CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 629025a7eb4..d9a413f96d9 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="imx8mn_beacon" CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index dade877a14e..6c626aee6a9 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="imx8mn_beacon" CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_ENV_SIZE=0x2000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 1880d0311e4..699e2090449 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -12,67 +12,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -/* Initial environment variables */ -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=Image\0" \ - "ramdiskimage=rootfs.cpio.uboot\0" \ - "console=ttymxc1,115200\0" \ - "fdt_addr=0x43000000\0" \ - "ramdisk_addr=0x44000000\0" \ - "boot_fdt=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} " \ - " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ - "ramargs=setenv bootargs console=${console} root=/dev/ram rw " \ - " ${optargs}\0" \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}\0"\ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "echo wait for boot; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "booti; " \ - "fi;\0" \ - "ramboot=echo Booting from RAMdisk...; "\ - "run loadimage; run loadfdt; fdt addr $fdt_addr; "\ - "run loadramdisk; run ramargs; " \ - "booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}\0" - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 From 89c30846f85819728dd974fba2b3716a13970da1 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 May 2023 14:18:03 -0500 Subject: [PATCH 045/109] imx8m: imx8mn-beacon: Migrate README to rst Since U-Boot builds HTML documentation, migrate the contents of the README file to an rst file which can generate the proper outputs. Signed-off-by: Adam Ford --- board/beacon/imx8mn/README | 38 --------------------- doc/board/beacon/beacon-imx8mn.rst | 53 ++++++++++++++++++++++++++++++ doc/board/beacon/index.rst | 1 + 3 files changed, 54 insertions(+), 38 deletions(-) delete mode 100644 board/beacon/imx8mn/README create mode 100644 doc/board/beacon/beacon-imx8mn.rst diff --git a/board/beacon/imx8mn/README b/board/beacon/imx8mn/README deleted file mode 100644 index 49da03c8d83..00000000000 --- a/board/beacon/imx8mn/README +++ /dev/null @@ -1,38 +0,0 @@ -U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit - -Quick Start -=========== -- Build the ARM Trusted firmware binary -- Get ddr firmware -- Build U-Boot -- Boot - -Get and Build the ARM Trusted firmware -====================================== -Note: $(srctree) is U-Boot source directory - -$ git clone https://github.com/nxp-imx/imx-atf -$ git lf-5.10.72-2.2.0 -$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu- -$ cp build/imx8mn/release/bl31.bin $(srctree) - -Get the DDR firmware -==================== -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin -$ chmod +x firmware-imx-8.9.bin -$ ./firmware-imx-8.9 -$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree) - -Build U-Boot -============ -$ make imx8mn_beacon_defconfig -$ make CROSS_COMPILE=aarch64-linux-gnu- - -Burn U-Boot to microSD Card -=========================== -$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 - -Boot -==== -Set baseboard DIP switch: -S17: 1100XXXX diff --git a/doc/board/beacon/beacon-imx8mn.rst b/doc/board/beacon/beacon-imx8mn.rst new file mode 100644 index 00000000000..bb4a86369bb --- /dev/null +++ b/doc/board/beacon/beacon-imx8mn.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit +====================================================== + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get DDR firmware +- Build U-Boot +- Burn U-Boot to microSD Card +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6 + $ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu- + $ cp build/imx8mn/release/bl31.bin ../ + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin + $ chmod +x firmware-imx-8.15.bin + $ ./firmware-imx-8.15 + $ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +------------ + +.. code-block:: bash + + $ make imx8mn_beacon_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- + +Burn U-Boot to microSD Card +--------------------------- + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +---- + +Set baseboard DIP switches for micoSD Card: +S17 (1:8): 1100xxxx diff --git a/doc/board/beacon/index.rst b/doc/board/beacon/index.rst index 8eba5e81cdc..bf62b09fbad 100644 --- a/doc/board/beacon/index.rst +++ b/doc/board/beacon/index.rst @@ -8,3 +8,4 @@ Beacon beacon-imx8mp beacon-imx8mm + beacon-imx8mn From b161ffbb0e2e3fde3f03056010b70f6f2f47522b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 May 2023 14:18:04 -0500 Subject: [PATCH 046/109] imx8m: beacon: Update MAINTAINER file to include beacon rst files With variou README files migrated to rst, add them to the MAINTAINER file for Beacon. Signed-off-by: Adam Ford --- board/beacon/imx8mm/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/beacon/imx8mm/MAINTAINERS b/board/beacon/imx8mm/MAINTAINERS index e887db20a21..d48ba8605bb 100644 --- a/board/beacon/imx8mm/MAINTAINERS +++ b/board/beacon/imx8mm/MAINTAINERS @@ -5,3 +5,4 @@ S: Maintained F: board/beacon/imx8mm/ F: include/configs/imx8mm_beacon.h F: configs/imx8mm_beacon_defconfig +F: doc/board/beacon/ From a59b3cd03539817dfbbeff5d47b9e4b8d6e6fe01 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 9 Jun 2023 09:51:46 -0700 Subject: [PATCH 047/109] board: gateworks: venice: assume emmc device for USB boot When booting from USB (SDP) setup firmware-update environment for emmc device. Signed-off-by: Tim Harvey --- board/gateworks/venice/venice.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 803582c55b9..3067480e6ac 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -155,6 +155,7 @@ int board_late_init(void) bootdev = 2; break; default: + bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */ break; } if (bootdev != -1) From 80fbbf4c810452bfbd140a36658aaaaca406b7a0 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 9 Jun 2023 09:54:01 -0700 Subject: [PATCH 048/109] board: gateworks: venice: display dram speed Display dram speed during configuration. Signed-off-by: Tim Harvey --- board/gateworks/venice/spl.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 50056da3ee0..c81498e830d 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -83,9 +83,12 @@ static void spl_dram_init(int size) printf("DRAM : LPDDR4 "); if (size > 512) - printf("%d GiB\n", size / 1024); + printf("%d GiB", size / 1024); else - printf("%d MiB\n", size); + printf("%d MiB", size); + printf(" %dMT/s %dMHz\n", + dram_timing->fsp_msg[0].drate, + dram_timing->fsp_msg[0].drate / 2); ddr_init(dram_timing); } From 48c6f9777ceeed8447223d6a9b6dcfd4979764d5 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 9 Jun 2023 09:54:51 -0700 Subject: [PATCH 049/109] board: gateworks: venice: add imx8mp-gw7905-2x support The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW7905 Baseboard contains the following: - GPS - microSD - off-board I/O connector with I2C, SPI, GPIO - EERPOM - PCIe clock generator - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB 3.0 HUB - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support Signed-off-by: Tim Harvey --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi | 12 + arch/arm/dts/imx8mp-venice-gw702x.dtsi | 587 ++++++++++++++++++ .../dts/imx8mp-venice-gw7905-2x-u-boot.dtsi | 51 ++ arch/arm/dts/imx8mp-venice-gw7905-2x.dts | 28 + arch/arm/dts/imx8mp-venice-gw7905.dtsi | 309 +++++++++ board/gateworks/venice/eeprom.c | 5 + board/gateworks/venice/lpddr4_timing.h | 1 + board/gateworks/venice/lpddr4_timing_imx8mp.c | 532 ++++++++++++++++ board/gateworks/venice/spl.c | 19 +- configs/imx8mp_venice_defconfig | 2 +- 11 files changed, 1544 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-venice-gw702x.dtsi create mode 100644 arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-venice-gw7905-2x.dts create mode 100644 arch/arm/dts/imx8mp-venice-gw7905.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 17f506a8fa0..6a40ac78f96 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1017,6 +1017,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-venice.dtb \ imx8mp-venice-gw74xx.dtb \ + imx8mp-venice-gw7905-2x.dtb \ imx8mp-verdin-wifi-dev.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ diff --git a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi new file mode 100644 index 00000000000..b9e3db7de93 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ + +#include "imx8mp-venice-u-boot.dtsi" + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw702x.dtsi b/arch/arm/dts/imx8mp-venice-gw702x.dtsi new file mode 100644 index 00000000000..560c68e4da6 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw702x.dtsi @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include +#include +#include + +/ { + aliases { + ethernet0 = &eqos; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck3_reg>; +}; + +&A53_1 { + cpu-supply = <&buck3_reg>; +}; + +&A53_2 { + cpu-supply = <&buck3_reg>; +}; + +&A53_3 { + cpu-supply = <&buck3_reg>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0x0>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + tx-fifo-depth = ; + rx-fifo-depth = ; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@16 { + gw,mode = <4>; + reg = <0x16>; + label = "fan_tach"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_1p0"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_1p8"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_2p5"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_dram"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_soc"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_arm"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + + fan-controller@0 { + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; + + pmic@69 { + compatible = "mps,mp5416"; + reg = <0x69>; + + regulators { + /* vdd_soc */ + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_dram */ + buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_arm */ + buck3_reg: buck3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_1p8 */ + buck4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT2: nvcc_snvs_1p8 */ + ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT3: vdd_1p0 */ + ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT4: vdd_2p5 */ + ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT5: vdd_3p3 */ + ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +/* off-board header */ +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* off-board */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + status = "okay"; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi new file mode 100644 index 00000000000..981841cee0a --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ +#include "imx8mp-venice-gw702x-u-boot.dtsi" + +&gpio1 { + app_gpioa { + gpio-hog; + input; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "gpioa"; + }; +}; + +&gpio4 { + app_gpiod { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "gpiod"; + }; + + app_gpiob { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "gpiob"; + }; + + app_gpioc { + gpio-hog; + input; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "gpioc"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts new file mode 100644 index 00000000000..4a1bbbbe19e --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw7905.dtsi" + +/ { + model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; + +/* Disable SOM interfaces not used on baseboard */ +&eqos { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905.dtsi b/arch/arm/dts/imx8mp-venice-gw7905.dtsi new file mode 100644 index 00000000000..0d40cb0f05f --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw7905.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include +#include +#include + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + compatible = "regulator-fixed"; + regulator-name = "SD2_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "gpioa", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "gpiod", "", "", + "gpiob", "gpioc", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "pci_usb_sel", "", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* USB1 - Type C front panel SINK port J14 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB: + * P1 - USBC connector (host only) + * P2 - USB2 test connector + * P3 - miniPCIe full card + * P4 - miniPCIe half card + */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ + MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index 6aea60ad05c..241be4ee630 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -218,6 +218,11 @@ const char *eeprom_get_dtb_name(int level, char *buf, int sz) int rev_base_bom = get_bom_rev(base_info.model); snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som); + /* GW79xx baseboards have no build options */ + if (base == 79) { + base = (int)strtoul(base_info.model + 2, NULL, 10); + snprintf(buf, sz, "%s%4d-%dx", pre, base, som); + } switch (level) { case 0: /* full model (ie gw73xx-0x-a1a1) */ if (rev_base_bom) diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index 62b860610c5..d19902f10ec 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -16,6 +16,7 @@ extern struct dram_timing_info dram_timing_1gb_single_die; extern struct dram_timing_info dram_timing_2gb_single_die; extern struct dram_timing_info dram_timing_2gb_dual_die; #elif CONFIG_IMX8MP +extern struct dram_timing_info dram_timing_1gb_single_die; extern struct dram_timing_info dram_timing_4gb_dual_die; #endif diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 2e96332f8b5..7bfd1b556bb 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1314,6 +1314,538 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0xd0000, 0x1 } }; +/* + * Generated code from MX8M_DDR_tool v3.30 using MX8MP Plus RPAv9 + * - 1GiB: ixm8mp-gw7020 1x Micron MT53E256M32D2DS 2-ch single-die per channel + */ +struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1203 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b0087 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x402 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0x8d }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0xf070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1001 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0012 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x302 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x13 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1001 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30005 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x302 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x5 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0x599 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x3 }, + { 0x100a3, 0x2 }, + { 0x100a4, 0x5 }, + { 0x100a5, 0x4 }, + { 0x100a6, 0x7 }, + { 0x100a7, 0x6 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x3 }, + { 0x130a3, 0x4 }, + { 0x130a4, 0x5 }, + { 0x130a5, 0x2 }, + { 0x130a6, 0x7 }, + { 0x130a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1gb_single_die), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1gb_single_die = { + .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), + .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_1gb_single_die), + .fsp_msg = ddr_dram_fsp_msg_1gb_single_die, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1gb_single_die), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + /* * Generated code from MX8M_DDR_tool v3.30 using MX8M Plus RPAv7 * - 4GiB: imx8mp-gw7401 1x Micron MT53D1024M32D4DT 2-ch dual-die per channel diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index c81498e830d..606738a8c97 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -71,6 +71,9 @@ static void spl_dram_init(int size) dram_timing = &dram_timing_2gb_dual_die; size = 2048; #elif CONFIG_IMX8MP + case 1024: + dram_timing = &dram_timing_1gb_single_die; + break; case 4096: dram_timing = &dram_timing_4gb_dual_die; break; @@ -124,7 +127,8 @@ static int power_init_board(void) if ((!strncmp(model, "GW71", 4)) || (!strncmp(model, "GW72", 4)) || - (!strncmp(model, "GW73", 4))) { + (!strncmp(model, "GW73", 4)) || + (!strncmp(model, "GW7905", 6))) { ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); @@ -135,11 +139,22 @@ static int power_init_board(void) printf("PMIC : failed probe: %d\n", ret); return ret; } - puts("PMIC : MP5416\n"); +#ifdef CONFIG_IMX8MM + puts("PMIC : MP5416 (IMX8MM)\n"); /* set VDD_ARM SW3 to 0.92V for 1.6GHz */ dm_i2c_reg_write(dev, MP5416_VSET_SW3, BIT(7) | MP5416_VSET_SW3_SVAL(920000)); +#elif CONFIG_IMX8MP + puts("PMIC : MP5416 (IMX8MP)\n"); + + /* set VDD_ARM SW3 to 0.95V for 1.6GHz */ + dm_i2c_reg_write(dev, MP5416_VSET_SW3, + BIT(7) | MP5416_VSET_SW3_SVAL(950000)); + /* set VDD_SOC SW1 to 0.95V for 1.6GHz */ + dm_i2c_reg_write(dev, MP5416_VSET_SW1, + BIT(7) | MP5416_VSET_SW1_SVAL(950000)); +#endif } else if (!strncmp(model, "GW74", 4)) { diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index f9065e7bf09..ee4b84db191 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -76,7 +76,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx" +CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 From b3fad716476c639f32af758ff56d63197535096b Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Wed, 14 Jun 2023 09:12:19 +0200 Subject: [PATCH 050/109] doc: board: phytec: add phycore_imx8mm Add documentation on how to build a bootable U-Boot image for the PHYTEC phyCORE-i.MX 8M Mini. Signed-off-by: Yannic Moog --- doc/board/index.rst | 1 + doc/board/phytec/index.rst | 9 +++++ doc/board/phytec/phycore-imx8mm.rst | 60 +++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100644 doc/board/phytec/index.rst create mode 100644 doc/board/phytec/phycore-imx8mm.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index 9ef25b10915..ce1fbe2fffa 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -32,6 +32,7 @@ Board-specific doc nokia/index nxp/index openpiton/index + phytec/index purism/index qualcomm/index renesas/index diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst new file mode 100644 index 00000000000..30292d0d76b --- /dev/null +++ b/doc/board/phytec/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +PHYTEC +====== + +.. toctree:: + :maxdepth: 2 + + phycore-imx8mm diff --git a/doc/board/phytec/phycore-imx8mm.rst b/doc/board/phytec/phycore-imx8mm.rst new file mode 100644 index 00000000000..e9dc2259907 --- /dev/null +++ b/doc/board/phytec/phycore-imx8mm.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +phyCORE-i.MX 8M Mini +==================== + +The phyCORE-i.MX 8M Mini with 2GB of main memory is supported. + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get ddr firmware +- Build U-Boot +- Boot + +Build the ARM Trusted firmware binary +------------------------------------- + +.. code-block:: bash + + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + $ export CROSS_COMPILE=aarch64-linux-gnu + $ export IMX_BOOT_UART_BASE=0x30880000 + $ make PLAT=imx8mm bl31 + +Get the ddr firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin + $ chmod +x firmware-imx-8.19.bin + $ ./firmware-imx-8.19.bin + +Build U-Boot for SD card +------------------------ + +Copy binaries +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ cp /build/imx8mm/release/bl31.bin . + $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make phycore-imx8mm_defconfig + $ make flash.bin + +Flash SD card +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=sync From 8a81326d79031843d714daf854d07762f8d560f0 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Wed, 14 Jun 2023 09:12:20 +0200 Subject: [PATCH 051/109] doc: board: phytec: add phycore_imx8mp Add documentation on how to build a bootable U-Boot image for the PHYTEC phyCORE-i.MX 8M Plus. Signed-off-by: Yannic Moog --- doc/board/phytec/index.rst | 1 + doc/board/phytec/phycore-imx8mp.rst | 60 +++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 doc/board/phytec/phycore-imx8mp.rst diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 30292d0d76b..a5b442045ed 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -7,3 +7,4 @@ PHYTEC :maxdepth: 2 phycore-imx8mm + phycore-imx8mp diff --git a/doc/board/phytec/phycore-imx8mp.rst b/doc/board/phytec/phycore-imx8mp.rst new file mode 100644 index 00000000000..fda751aeffb --- /dev/null +++ b/doc/board/phytec/phycore-imx8mp.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +phyCORE-i.MX 8M Plus +==================== + +The phyCORE-i.MX 8M Plus with 2GB of main memory is supported. + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get ddr firmware +- Build U-Boot +- Boot + +Build the ARM Trusted firmware binary +------------------------------------- + +.. code-block:: bash + + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + $ export CROSS_COMPILE=aarch64-linux-gnu + $ export IMX_BOOT_UART_BASE=0x30860000 + $ make PLAT=imx8mp bl31 + +Get the ddr firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin + $ chmod +x firmware-imx-8.19.bin + $ ./firmware-imx-8.19.bin + +Build U-Boot for SD card +------------------------ + +Copy binaries +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ cp /build/imx8mp/release/bl31.bin . + $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make phycore-imx8mp_defconfig + $ make flash.bin + +Flash SD card +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=sync From 44103cf331eeb83e7b41391526c074b1432f8dba Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Wed, 14 Jun 2023 11:01:37 +0200 Subject: [PATCH 052/109] colibri_imx6: fix RALAT and WALAT values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Running a memtest in U-Boot and Linux shows that some Colibri iMX6 produce bitflips at temperatures above 60°C. This happens because the RALAT and WALAT values on the Colibri iMX6 are too low. The problems were introduced by commit 09dbac8174c4 ("mx6: ddr: Restore ralat/walat in write level calibration") before the calibration process overwrote the values and set them to the maximum value. With this commit, we make sure that the RALAT and WALAT values are set to the maximum values again. This has been proven to work for years. Fixes: 09dbac8174c4 ("mx6: ddr: Restore ralat/walat in write level calibration") Signed-off-by: Stefan Eichenberger Signed-off-by: Francesco Dolcini --- board/toradex/colibri_imx6/colibri_imx6.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 65e0e9a156a..677caa4a4eb 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -767,8 +767,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, /* * MDMISC mirroring interleaved (row/bank/col) */ -/* TODO: check what the RALAT field does */ -MX6_MMDC_P0_MDMISC, 0x00081740, +MX6_MMDC_P0_MDMISC, 0x000b17c0, /* * MDSCR con_req @@ -900,8 +899,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, /* * MDMISC mirroring interleaved (row/bank/col) */ -/* TODO: check what the RALAT field does */ -MX6_MMDC_P0_MDMISC, 0x00081740, +MX6_MMDC_P0_MDMISC, 0x000b17c0, /* * MDSCR con_req From b70a1686c84f742cc8938748f38c8b00462d1d82 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Wed, 14 Jun 2023 14:36:47 +0200 Subject: [PATCH 053/109] configs: phycore-imx8mp_defconfig: Enable LTO Enable LTO for binary size reduction. Signed-off-by: Teresa Remmet --- configs/phycore-imx8mp_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 3d076204ad0..7bf404be860 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_STACK=0x960000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_LTO=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y From e064fe4f37b924741efbfe4d0db0d49fea143380 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Wed, 14 Jun 2023 14:36:48 +0200 Subject: [PATCH 054/109] configs: phycore-imx8mm_defconfig: Enable LTO Enable LTO for binary size reduction. Signed-off-by: Teresa Remmet --- configs/phycore-imx8mm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index ffdb5cce8eb..4a27d15cb11 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_STACK=0x920000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_LTO=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y From dd654caac0ea10bbf40d09985cccc8c9d9294287 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:08:58 +0800 Subject: [PATCH 055/109] imx: mach: correct SCU API usage The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan --- arch/arm/mach-imx/cmd_dek.c | 2 +- arch/arm/mach-imx/imx8/ahab.c | 10 +- arch/arm/mach-imx/imx8/cpu.c | 6 +- arch/arm/mach-imx/imx8/fdt.c | 2 +- arch/arm/mach-imx/imx8/snvs_security_sc.c | 175 +++++++++--------- .../power/domain/imx8-power-domain-legacy.c | 9 +- 6 files changed, 98 insertions(+), 106 deletions(-) diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 69ed57537b3..d77a49df860 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -154,7 +154,7 @@ error: static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) { - sc_err_t err; + int err; sc_rm_mr_t mr_input, mr_output; struct generate_key_blob_hdr hdr; u8 in_size, out_size; diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 9addb824b6d..86b0e0b755f 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -147,7 +147,7 @@ int authenticate_os_container(ulong addr) } exit: - if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE) + if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) printf("Error: release container failed!\n"); return ret; @@ -263,7 +263,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, u16 lc; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in get lifecycle\n"); return -EIO; } @@ -271,7 +271,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, display_life_cycle(lc); err = sc_seco_get_event(-1, idx, &event); - while (err == SC_ERR_NONE) { + while (!err) { printf("SECO Event[%u] = 0x%08X\n", idx, event); display_ahab_auth_event(event); @@ -312,7 +312,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, return -EACCES; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in get lifecycle\n"); return -EIO; } @@ -324,7 +324,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, } err = sc_seco_forward_lifecycle(-1, 16); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in forward lifecycle to OEM closed\n"); return -EIO; } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 7b292c07ef9..2b34077438f 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -195,7 +195,7 @@ enum boot_device get_boot_device(void) #define FUSE_UNIQUE_ID_WORD1 17 void get_board_serial(struct tag_serialnr *serialnr) { - sc_err_t err; + int err; u32 val1 = 0, val2 = 0; u32 word1, word2; @@ -206,13 +206,13 @@ void get_board_serial(struct tag_serialnr *serialnr) word2 = FUSE_UNIQUE_ID_WORD1; err = sc_misc_otp_fuse_read(-1, word1, &val1); - if (err != SC_ERR_NONE) { + if (err) { printf("%s fuse %d read error: %d\n", __func__, word1, err); return; } err = sc_misc_otp_fuse_read(-1, word2, &val2); - if (err != SC_ERR_NONE) { + if (err) { printf("%s fuse %d read error: %d\n", __func__, word2, err); return; } diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index 02b3ee5c111..491c8bb8c75 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -110,7 +110,7 @@ static int config_smmu_resource_sid(int rsrc, int sid) err = sc_rm_set_master_sid(-1, rsrc, sid); debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); - if (err != SC_ERR_NONE) { + if (err) { if (!check_owned_resource(rsrc)) { printf("%s rsrc[%d] not owned\n", __func__, rsrc); return -1; diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index d7b20a1fcbf..1eaa68f8d5f 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -286,16 +286,15 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, u32 *_p3, u32 *_p4, u32 *_p5, u32 _cnt) { - int scierr = 0; + int err; u32 d1 = ptr_value(_p1); u32 d2 = ptr_value(_p2); u32 d3 = ptr_value(_p3); u32 d4 = ptr_value(_p4); u32 d5 = ptr_value(_p5); - scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3, - &d4, &d4, _cnt); - if (scierr != SC_ERR_NONE) { + err = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3, &d4, &d4, _cnt); + if (err) { printf("Failed to set secvio configuration\n"); debug("Failed to set conf id 0x%x with values ", id); debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n", @@ -315,7 +314,7 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, *(u32 *)_p5 = d5; exit: - return scierr; + return err; } #define SC_CHECK_WRITE1(id, _p1) \ @@ -323,7 +322,7 @@ exit: static int apply_snvs_config(struct snvs_security_sc_conf *cnf) { - int scierr = 0; + int err = 0; debug("%s\n", __func__); @@ -365,92 +364,88 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf) cnf->lp.act_tamper_routing_ctl1, cnf->lp.act_tamper_routing_ctl2); - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg), - &cnf->lp.tamper_filt_cfg, - &cnf->lp.tamper_filt1_cfg, - &cnf->lp.tamper_filt2_cfg, NULL, - NULL, 3); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg), + &cnf->lp.tamper_filt_cfg, + &cnf->lp.tamper_filt1_cfg, + &cnf->lp.tamper_filt2_cfg, + NULL, NULL, 3); + if (err) goto exit; /* Configure AT */ - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg), - &cnf->lp.act_tamper1_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, 5); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg), + &cnf->lp.act_tamper1_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, 5); + if (err) goto exit; /* Configure AT routing */ - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1), - &cnf->lp.act_tamper_routing_ctl1, - &cnf->lp.act_tamper_routing_ctl2, - NULL, NULL, NULL, 2); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1), + &cnf->lp.act_tamper_routing_ctl1, + &cnf->lp.act_tamper_routing_ctl2, + NULL, NULL, NULL, 2); + if (err) goto exit; /* Configure AT frequency */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl), - &cnf->lp.act_tamper_clk_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl), + &cnf->lp.act_tamper_clk_ctl); + if (err) goto exit; /* Activate the ATs */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl), - &cnf->lp.act_tamper_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl), &cnf->lp.act_tamper_ctl); + if (err) goto exit; /* Activate the detectors */ - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg), - &cnf->lp.tamper_det_cfg, - &cnf->lp.tamper_det_cfg2, NULL, NULL, - NULL, 2); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg), + &cnf->lp.tamper_det_cfg, + &cnf->lp.tamper_det_cfg2, NULL, NULL, NULL, 2); + if (err) goto exit; /* Configure LP secvio */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl), - &cnf->lp.secvio_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl), &cnf->lp.secvio_ctl); + if (err) goto exit; /* Configure HP secvio */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl), - &cnf->hp.secvio_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl), &cnf->hp.secvio_ctl); + if (err) goto exit; /* Lock access */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock); + if (err) goto exit; - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock); + if (err) goto exit; exit: - return (scierr == SC_ERR_NONE) ? 0 : -EIO; + return err; } static int dgo_write(u32 _id, u8 _access, u32 *_pdata) { - int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata); + int err = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata); - if (scierr != SC_ERR_NONE) { + if (err) { printf("Failed to set dgo configuration\n"); debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata); } - return scierr; + return err; } static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf) { - int scierr = 0; + int err; debug("%s\n", __func__); @@ -468,50 +463,50 @@ static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf) cnf->tamper_misc_ctl, cnf->tamper_core_volt_mon_ctl); - dgo_write(0x04, 1, &cnf->tamper_offset_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x04, 1, &cnf->tamper_offset_ctl); + if (err) goto exit; - dgo_write(0x14, 1, &cnf->tamper_pull_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x14, 1, &cnf->tamper_pull_ctl); + if (err) goto exit; - dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl); + if (err) goto exit; - dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl); + if (err) goto exit; - dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl); + if (err) goto exit; /* Last as it could lock the writes */ - dgo_write(0x44, 1, &cnf->tamper_misc_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x44, 1, &cnf->tamper_misc_ctl); + if (err) goto exit; exit: - return (scierr == SC_ERR_NONE) ? 0 : -EIO; + return err; } static int pad_write(u32 _pad, u32 _value) { - int scierr = sc_pad_set(-1, _pad, _value); + int err = sc_pad_set(-1, _pad, _value); - if (scierr != SC_ERR_NONE) { + if (err) { printf("Failed to set pad configuration\n"); debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value); } - return scierr; + return err; } static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) { - int scierr = 0; + int err = 0; u32 idx; debug("%s\n", __func__); @@ -519,13 +514,13 @@ static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) for (idx = 0; idx < size; idx++) { debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad, confs[idx].mux_conf); - pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); - if (scierr != SC_ERR_NONE) + err = pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); + if (err) goto exit; } exit: - return (scierr == SC_ERR_NONE) ? 0 : -EIO; + return err; } int examples(void) @@ -753,7 +748,7 @@ static char snvs_clear_status_help_text[] = static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int scierr = 0; + int err; u32 idx = 0; struct snvs_security_sc_conf conf = {0}; @@ -764,20 +759,18 @@ static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc, conf.lp.status = hextoul(argv[++idx], NULL); conf.lp.tamper_det_status = hextoul(argv[++idx], NULL); - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status), - &conf.lp.status, NULL, NULL, NULL, - NULL, 1); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status), + &conf.lp.status, NULL, NULL, NULL, NULL, 1); + if (err) goto exit; - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status), - &conf.lp.tamper_det_status, NULL, - NULL, NULL, NULL, 1); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status), + &conf.lp.tamper_det_status, NULL, NULL, NULL, NULL, 1); + if (err) goto exit; exit: - return (scierr == SC_ERR_NONE) ? 0 : 1; + return err; } U_BOOT_CMD(snvs_clear_status, @@ -793,7 +786,7 @@ static char snvs_sec_status_help_text[] = static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int scierr; + int err; u32 idx; u32 data[5]; @@ -864,8 +857,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(pads); idx++) { u8 pad_id = pads[idx]; - scierr = sc_pad_get(-1, pad_id, &data[0]); - if (scierr == 0) + err = sc_pad_get(-1, pad_id, &data[0]); + if (!err) printf("\t- Pin %d: %.8x\n", pad_id, data[0]); else printf("Failed to read Pin %d\n", pad_id); @@ -876,8 +869,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) { u32 fuse_id = fuses[idx]; - scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]); - if (scierr == 0) + err = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]); + if (!err) printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]); else printf("Failed to read Fuse %d\n", fuse_id); @@ -888,10 +881,10 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) { struct snvs_reg *reg = &snvs[idx]; - scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0], - &data[1], &data[2], &data[3], - &data[4], reg->nb); - if (scierr == 0) { + err = sc_seco_secvio_config(-1, reg->id, 0, &data[0], + &data[1], &data[2], &data[3], + &data[4], reg->nb); + if (!err) { int subidx; printf("\t- SNVS %.2x(%d):", reg->id, reg->nb); @@ -908,8 +901,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) { u8 dgo_id = dgo[idx]; - scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]); - if (scierr == 0) + err = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]); + if (!err) printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]); else printf("Failed to read DGO %d\n", dgo_id); diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index 37b0f95abac..c8ca2665752 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -89,7 +89,6 @@ static int imx8_power_domain_on(struct power_domain *power_domain) struct udevice *dev = power_domain->dev; struct imx8_power_domain_plat *pdata; struct imx8_power_domain_priv *ppriv; - sc_err_t ret; int err; struct power_domain parent_domain; @@ -117,11 +116,11 @@ static int imx8_power_domain_on(struct power_domain *power_domain) if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) printf("%s [%d] not owned by curr partition\n", dev->name, pdata->resource_id); - ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id, + err = sc_pm_set_resource_power_mode(-1, pdata->resource_id, SC_PM_PW_MODE_ON); - if (ret) { + if (err) { printf("Error: %s Power up failed! (error = %d)\n", - dev->name, ret); + dev->name, err); return -EIO; } } @@ -139,7 +138,7 @@ static int imx8_power_domain_off_node(struct power_domain *power_domain) struct imx8_power_domain_priv *ppriv; struct imx8_power_domain_priv *child_ppriv; struct imx8_power_domain_plat *pdata; - sc_err_t ret; + int ret; ppriv = dev_get_priv(dev); pdata = dev_get_plat(dev); From bfb3409d676f5089ae91d63aa2e9244130477e14 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:08:59 +0800 Subject: [PATCH 056/109] imx: toradex/apalis-imx8: correct SCU API usage The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan --- board/toradex/apalis-imx8/apalis-imx8.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index aa76c486eec..e2bbaba8b8c 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -85,18 +85,18 @@ static void setup_iomux_uart(void) static uint32_t do_get_tdx_user_fuse(int a, int b) { - sc_err_t sciErr; + int sciErr; u32 val_a = 0; u32 val_b = 0; sciErr = sc_misc_otp_fuse_read(-1, a, &val_a); - if (sciErr != SC_ERR_NONE) { + if (sciErr) { printf("Error reading out user fuse %d\n", a); return 0; } sciErr = sc_misc_otp_fuse_read(-1, b, &val_b); - if (sciErr != SC_ERR_NONE) { + if (sciErr) { printf("Error reading out user fuse %d\n", b); return 0; } @@ -131,9 +131,9 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, { u32 is_quadplus = 0, val = 0; struct tdx_user_fuses tdxramfuses; - sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + int scierr = sc_misc_otp_fuse_read(-1, 6, &val); - if (scierr == SC_ERR_NONE) { + if (scierr) { /* QP has one A72 core disabled */ is_quadplus = ((val >> 4) & 0x3) != 0x0; } From aa6e698a7acd4d6db4be26661b1839ce417cbb20 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:00 +0800 Subject: [PATCH 057/109] imx: toradex/colibri-imx8x: correct SCU API usage The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan --- board/toradex/colibri-imx8x/colibri-imx8x.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index afdd24a5f42..f504385aec9 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -43,9 +43,9 @@ static void setup_iomux_uart(void) static int is_imx8dx(void) { u32 val = 0; - sc_err_t sc_err = sc_misc_otp_fuse_read(-1, 6, &val); + int sc_err = sc_misc_otp_fuse_read(-1, 6, &val); - if (sc_err == SC_ERR_NONE) { + if (sc_err) { /* DX has two A35 cores disabled */ return (val & 0xf) != 0x0; } @@ -70,7 +70,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, int board_early_init_f(void) { sc_pm_clock_rate_t rate; - sc_err_t err = 0; + int err; /* * This works around that having only UART3 up the baudrate is 1.2M @@ -78,13 +78,13 @@ int board_early_init_f(void) */ rate = 80000000; err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); - if (err != SC_ERR_NONE) + if (err) return 0; /* Set UART3 clock root to 80 MHz and enable it */ rate = SC_80MHZ; err = sc_pm_setup_uart(SC_R_UART_3, rate); - if (err != SC_ERR_NONE) + if (err) return 0; setup_iomux_uart(); From 0baac09fc93778e83614e68dbea6193ff3dc58df Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:01 +0800 Subject: [PATCH 058/109] imx: siemens/capricorn: correct SCU API usage The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan --- board/siemens/capricorn/board.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index a0c62e0fc4c..924c88e8fab 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -147,7 +147,7 @@ static void enet_device_phy_reset(void) int setup_gpr_fec(void) { sc_ipc_t ipc_handle = -1; - sc_err_t err = 0; + int err = 0; unsigned int test; /* @@ -175,35 +175,35 @@ int setup_gpr_fec(void) */ err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test); From 227c513e70ad6ad266cd2710f8601c47139eca8a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:02 +0800 Subject: [PATCH 059/109] imx: advantech: correct SCU API usage The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan Tested-by: Oliver Graute Reviewed-by: Oliver Graute --- board/advantech/imx8qm_dmsse20_a1/spl.c | 6 +++--- board/advantech/imx8qm_rom7720_a1/spl.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c index 7f2e972425b..f36caece7d7 100644 --- a/board/advantech/imx8qm_dmsse20_a1/spl.c +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -111,7 +111,7 @@ int board_mmc_init(struct bd_info *bis) switch (i) { case 0: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); @@ -120,10 +120,10 @@ int board_mmc_init(struct bd_info *bis) break; case 1: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index b602437c35b..922bb0b7d43 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -112,7 +112,7 @@ int board_mmc_init(struct bd_info *bis) switch (i) { case 0: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); @@ -121,10 +121,10 @@ int board_mmc_init(struct bd_info *bis) break; case 1: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); From c186596ac45e7b5521e6df5a9471793c763eb20b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:03 +0800 Subject: [PATCH 060/109] imx: congatec/cgtqmx8: correct SCU API usage The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan Tested-by: Oliver Graute Reviewed-by: Oliver Graute --- board/congatec/cgtqmx8/cgtqmx8.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index bedd1e03308..26189ff66f5 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -79,7 +79,7 @@ static void setup_iomux_uart(void) int board_early_init_f(void) { /* sc_ipc_t ipcHndl = 0; */ - sc_err_t scierr = 0; + int scierr; /* When start u-boot in XEN VM, directly return */ /* if (IS_ENABLED(CONFIG_XEN)) */ @@ -89,19 +89,19 @@ int board_early_init_f(void) /* Power up UART0, this is very early while power domain is not working */ scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); - if (scierr != SC_ERR_NONE) + if (scierr) return 0; /* Set UART0 clock root to 80 MHz */ sc_pm_clock_rate_t rate = 80000000; scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); - if (scierr != SC_ERR_NONE) + if (scierr) return 0; /* Enable UART0 clock root */ scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); - if (scierr != SC_ERR_NONE) + if (scierr) return 0; setup_iomux_uart(); From 922d4504bcab8aebe159d811cc1e804f2d7bf8f7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:04 +0800 Subject: [PATCH 061/109] imx: scu_api: update to version 1.16 and add more APIs Upgrade SCFW API to 1.16 Add more APIs: sc_misc_get_button_status sc_pm_reboot sc_seco_v2x_build_info Signed-off-by: Peng Fan --- drivers/misc/imx8/scu_api.c | 78 ++++++++++++++++++++ include/firmware/imx/sci/rpc.h | 27 ++++--- include/firmware/imx/sci/sci.h | 24 ++++++ include/firmware/imx/sci/svc/misc/api.h | 42 ++++++++--- include/firmware/imx/sci/svc/pm/api.h | 94 ++++++++++++++++++++++++ include/firmware/imx/sci/svc/rm/api.h | 14 ++-- include/firmware/imx/sci/svc/seco/api.h | 5 +- include/firmware/imx/sci/svc/timer/api.h | 33 +++++++++ 8 files changed, 287 insertions(+), 30 deletions(-) create mode 100644 include/firmware/imx/sci/svc/timer/api.h diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index dfede7f1d5f..3e3002ba6df 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -481,6 +481,22 @@ int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, return 0; } +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ + struct sc_rpc_msg_s msg; + struct udevice *dev = gd->arch.scu_dev; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = (u8)(MISC_FUNC_GET_BUTTON_STATUS); + + misc_call(dev, SC_FALSE, &msg, 1U, &msg, 1U); + + if (status) + *status = (sc_bool_t)(!!(RPC_U8(&msg, 0U))); +} + /* RM */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) { @@ -851,6 +867,21 @@ int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, return ret; } +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = (u8)(PM_FUNC_REBOOT); + RPC_U8(&msg, 0U) = (u8)(type); + RPC_SIZE(&msg) = 2U; + + misc_call(dev, SC_TRUE, &msg, size, &msg, size); +} + int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t *mode) { @@ -877,6 +908,28 @@ int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, return ret; } +int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = (u8)(TIMER_FUNC_SET_WDOG_WINDOW); + + RPC_U32(&msg, 0U) = (u32)(window); + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: window:%u: res:%d\n", + __func__, window, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { @@ -974,6 +1027,31 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) *commit = RPC_U32(&msg, 4U); } +int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = (u8)(SECO_FUNC_V2X_BUILD_INFO); + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + if (version) + *version = RPC_U32(&msg, 0U); + + if (commit) + *commit = RPC_U32(&msg, 4U); + + return ret; +} + int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event) { struct udevice *dev = gd->arch.scu_dev; diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 39de7f0e3e0..85af6f3996e 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -23,12 +23,12 @@ #define RPC_FUNC(MSG) ((MSG)->func) #define RPC_R8(MSG) ((MSG)->func) #define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (s64)(RPC_U32((MSG), (IDX) + 4U)) + (s64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) #define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) #define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) #define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (u64)(RPC_U32((MSG), (IDX) + 4U)) + (u64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) #define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) #define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) @@ -67,7 +67,9 @@ struct sc_rpc_msg_s { #define PM_FUNC_SET_SYS_POWER_MODE 19U #define PM_FUNC_SET_PARTITION_POWER_MODE 1U #define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_PARTITION_WAKE 28U #define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U #define PM_FUNC_GET_RESOURCE_POWER_MODE 4U #define PM_FUNC_REQ_LOW_POWER_MODE 16U #define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U @@ -81,13 +83,16 @@ struct sc_rpc_msg_s { #define PM_FUNC_GET_CLOCK_PARENT 15U #define PM_FUNC_RESET 13U #define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_GET_RESET_PART 26U #define PM_FUNC_BOOT 8U +#define PM_FUNC_SET_BOOT_PARM 27U #define PM_FUNC_REBOOT 9U #define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_REBOOT_CONTINUE 25U #define PM_FUNC_CPU_START 11U #define PM_FUNC_CPU_RESET 23U #define PM_FUNC_RESOURCE_RESET 29U -#define PM_FUNC_IS_PARTITION_STARTED 24U +#define PM_FUNC_IS_PARTITION_STARTED 24U /* MISC RPC */ #define MISC_FUNC_UNKNOWN 0 @@ -95,16 +100,10 @@ struct sc_rpc_msg_s { #define MISC_FUNC_GET_CONTROL 2U #define MISC_FUNC_SET_MAX_DMA_GROUP 4U #define MISC_FUNC_SET_DMA_GROUP 5U -#define MISC_FUNC_SECO_IMAGE_LOAD 8U -#define MISC_FUNC_SECO_AUTHENTICATE 9U -#define MISC_FUNC_SECO_FUSE_WRITE 20U -#define MISC_FUNC_SECO_ENABLE_DEBUG 21U -#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U -#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U -#define MISC_FUNC_SECO_BUILD_INFO 24U #define MISC_FUNC_DEBUG_OUT 10U #define MISC_FUNC_WAVEFORM_CAPTURE 6U #define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_API_VER 35U #define MISC_FUNC_UNIQUE_ID 19U #define MISC_FUNC_SET_ARI 3U #define MISC_FUNC_BOOT_STATUS 7U @@ -114,8 +113,11 @@ struct sc_rpc_msg_s { #define MISC_FUNC_SET_TEMP 12U #define MISC_FUNC_GET_TEMP 13U #define MISC_FUNC_GET_BOOT_DEV 16U +#define MISC_FUNC_GET_BOOT_TYPE 33U +#define MISC_FUNC_GET_BOOT_CONTAINER 36U #define MISC_FUNC_GET_BUTTON_STATUS 18U -#define MISC_FUNC_GET_BOOT_CONTAINER 36U +#define MISC_FUNC_ROMPATCH_CHECKSUM 26U +#define MISC_FUNC_BOARD_IOCTL 34U /* PAD RPC */ #define PAD_FUNC_UNKNOWN 0 @@ -160,6 +162,7 @@ struct sc_rpc_msg_s { #define RM_FUNC_GET_RESOURCE_INFO 16U #define RM_FUNC_MEMREG_ALLOC 17U #define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FRAG 32U #define RM_FUNC_MEMREG_FREE 18U #define RM_FUNC_FIND_MEMREG 30U #define RM_FUNC_ASSIGN_MEMREG 19U @@ -190,6 +193,7 @@ struct sc_rpc_msg_s { #define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */ #define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */ #define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */ +#define SECO_FUNC_V2X_BUILD_INFO 30U /* Index for sc_seco_v2x_build_info() RPC call */ #define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */ #define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */ #define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */ @@ -210,6 +214,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_UNKNOWN 0 /* Unknown function */ #define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */ #define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_WINDOW 19U /* Index for sc_timer_set_wdog_window() RPC call */ #define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */ #define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */ #define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 61c8211b443..f832982b3de 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -73,6 +74,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clk_parent_t parent); int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, sc_faddr_t address); +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); @@ -88,6 +90,7 @@ void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, s16 *celsius, s8 *tenths); +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); /* RM API */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); @@ -117,6 +120,9 @@ int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); /* SMMU API */ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); +/* Timer API */ +int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); + /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr); @@ -124,6 +130,7 @@ int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, u32 *uid_h); void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); +int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, sc_faddr_t export_addr, u16 max_size); @@ -374,6 +381,23 @@ static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *dat return -EOPNOTSUPP; } +static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ +} + +static inline int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ + return -EOPNOTSUPP; +} + +static inline void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ +} + +static inline int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) +{ + return -EOPNOTSUPP; +} #endif #endif diff --git a/include/firmware/imx/sci/svc/misc/api.h b/include/firmware/imx/sci/svc/misc/api.h index 3629eb68d7a..a4b92b86cc6 100644 --- a/include/firmware/imx/sci/svc/misc/api.h +++ b/include/firmware/imx/sci/svc/misc/api.h @@ -5,27 +5,45 @@ #ifndef SC_MISC_API_H #define SC_MISC_API_H +/* Defines for type widths */ +#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */ +/* Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U /* Defines for sc_misc_boot_status_t */ #define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ #define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ - /* Defines for sc_misc_temp_t */ -#define SC_MISC_TEMP 0U /* Temp sensor */ -#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ -#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ -#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ -#define SC_MISC_REL_CONTAINER 2U /* Release container */ +/* Defines for sc_misc_bt_t */ +#define SC_MISC_BT_PRIMARY 0U /* Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /* Serial boot */ +/* Types */ +/* + * This type is used to store a DMA channel priority group. + */ +typedef u8 sc_misc_dma_group_t; + +/* + * This type is used report boot status. + */ typedef u8 sc_misc_boot_status_t; + +/* + * This type is used report boot status. + */ typedef u8 sc_misc_temp_t; +/* + * This type is used report the boot type. + */ +typedef u8 sc_misc_bt_t; #endif /* SC_MISC_API_H */ diff --git a/include/firmware/imx/sci/svc/pm/api.h b/include/firmware/imx/sci/svc/pm/api.h index 9008b85c6f6..d1b085d7f87 100644 --- a/include/firmware/imx/sci/svc/pm/api.h +++ b/include/firmware/imx/sci/svc/pm/api.h @@ -6,6 +6,14 @@ #ifndef SC_PM_API_H #define SC_PM_API_H +#include +/* Defines for type widths */ +#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ +/* Defines for ALL parameters */ +#define SC_PM_CLK_ALL ((sc_pm_clk_t)UINT8_MAX) /* All clocks */ /* Defines for sc_pm_power_mode_t */ #define SC_PM_PW_MODE_OFF 0U /* Power off */ #define SC_PM_PW_MODE_STBY 1U /* Power in standby */ @@ -35,10 +43,96 @@ #define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ #define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ +/* Defines for sc_pm_clk_parent_t */ +#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */ +#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ + +/* Defines for sc_pm_reset_type_t */ +#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ + +/* Defines for sc_pm_reset_reason_t */ +#define SC_PM_RESET_REASON_POR 0U /* Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /* Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ + +/* Defines for sc_pm_sys_if_t */ +#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ +#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /* DDR memory */ + +/* Defines for sc_pm_wake_src_t */ +/* No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_NONE 0U +/* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_SCU 1U +/* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U +/* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U +/* Wakeup from GIC to wake CPU */ +#define SC_PM_WAKE_SRC_GIC 4U +/* Types */ + +/* + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ typedef u8 sc_pm_power_mode_t; + +/* + * This type is used to declare a clock. + */ typedef u8 sc_pm_clk_t; + +/* + * This type is used to declare a clock mode. + */ typedef u8 sc_pm_clk_mode_t; + +/* + * This type is used to declare the clock parent. + */ typedef u8 sc_pm_clk_parent_t; + +/* + * This type is used to declare clock rates. + */ typedef u32 sc_pm_clock_rate_t; +/* + * This type is used to declare a desired reset type. + */ +typedef u8 sc_pm_reset_type_t; + +/* + * This type is used to declare a reason for a reset. + */ +typedef u8 sc_pm_reset_reason_t; + +/* + * This type is used to specify a system-level interface to be power managed. + */ +typedef u8 sc_pm_sys_if_t; + +/* + * This type is used to specify a wake source for CPU resources. + */ +typedef u8 sc_pm_wake_src_t; #endif /* SC_PM_API_H */ diff --git a/include/firmware/imx/sci/svc/rm/api.h b/include/firmware/imx/sci/svc/rm/api.h index 163d81403c5..f4e9abcd9b3 100644 --- a/include/firmware/imx/sci/svc/rm/api.h +++ b/include/firmware/imx/sci/svc/rm/api.h @@ -38,32 +38,36 @@ /* Types */ -/*! +/* * This type is used to declare a resource partition. */ typedef u8 sc_rm_pt_t; -/*! +/* * This type is used to declare a memory region. */ typedef u8 sc_rm_mr_t; -/*! +/* * This type is used to declare a resource domain ID used by the * isolation HW. */ typedef u8 sc_rm_did_t; -/*! +/* * This type is used to declare an SMMU StreamID. */ typedef u16 sc_rm_sid_t; -/*! +/* * This type is a used to declare master transaction attributes. */ typedef u8 sc_rm_spa_t; +/* + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ typedef u8 sc_rm_perm_t; #endif /* SC_RM_API_H */ diff --git a/include/firmware/imx/sci/svc/seco/api.h b/include/firmware/imx/sci/svc/seco/api.h index 6e9c302315b..7d4b6b92e17 100644 --- a/include/firmware/imx/sci/svc/seco/api.h +++ b/include/firmware/imx/sci/svc/seco/api.h @@ -17,6 +17,7 @@ #define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ #define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ #define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ +#define SC_SECO_EVERIFY_IMAGE 6U /* Enhanced verify image */ #define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ #define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ @@ -24,12 +25,12 @@ /* Types */ -/*! +/* * This type is used to issue SECO authenticate commands. */ typedef u8 sc_seco_auth_cmd_t; -/*! +/* * This type is used to return the RNG initialization status. */ typedef u32 sc_seco_rng_stat_t; diff --git a/include/firmware/imx/sci/svc/timer/api.h b/include/firmware/imx/sci/svc/timer/api.h new file mode 100644 index 00000000000..c2fe34aa751 --- /dev/null +++ b/include/firmware/imx/sci/svc/timer/api.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Defines */ + +/* Defines for type widths */ +#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */ + +/* Defines for sc_timer_wdog_action_t */ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */ + +/* Types */ + +/* + * This type is used to configure the watchdog action. + */ +typedef u8 sc_timer_wdog_action_t; + +/* + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef u32 sc_timer_wdog_time_t; + +#endif /* SC_TIMER_API_H */ From d3ee9dbd5984321d4a2932e19a59f455d8d90817 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:05 +0800 Subject: [PATCH 062/109] imx: use generic name ele(EdgeLockSecure Enclave) Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan --- arch/arm/Kconfig | 4 +- arch/arm/include/asm/arch-imx9/ccm_regs.h | 2 +- arch/arm/include/asm/global_data.h | 4 +- .../asm/mach-imx/{s400_api.h => ele_api.h} | 48 +++-- arch/arm/mach-imx/ele_ahab.c | 15 +- arch/arm/mach-imx/imx8ulp/rdc.c | 18 +- arch/arm/mach-imx/imx8ulp/soc.c | 16 +- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 6 +- arch/arm/mach-imx/imx9/clock.c | 8 +- arch/arm/mach-imx/imx9/clock_root.c | 2 +- arch/arm/mach-imx/imx9/soc.c | 16 +- arch/arm/mach-imx/imx9/trdc.c | 14 +- board/freescale/imx8ulp_evk/spl.c | 10 +- board/freescale/imx93_evk/spl.c | 1 - drivers/misc/Kconfig | 4 +- drivers/misc/Makefile | 2 +- drivers/misc/{sentinel => imx_ele}/Makefile | 2 +- .../s400_api.c => imx_ele/ele_api.c} | 200 +++++++++--------- .../{sentinel/s4mu.c => imx_ele/ele_mu.c} | 14 +- drivers/misc/{sentinel => imx_ele}/fuse.c | 40 ++-- 20 files changed, 213 insertions(+), 213 deletions(-) rename arch/arm/include/asm/mach-imx/{s400_api.h => ele_api.h} (78%) rename drivers/misc/{sentinel => imx_ele}/Makefile (71%) rename drivers/misc/{sentinel/s400_api.c => imx_ele/ele_api.c} (63%) rename drivers/misc/{sentinel/s4mu.c => imx_ele/ele_mu.c} (93%) rename drivers/misc/{sentinel => imx_ele}/fuse.c (84%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4604d41410c..17d69d27262 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -882,7 +882,7 @@ config ARCH_IMX8ULP select SUPPORT_SPL select GPIO_EXTRA_HEADER select MISC - select IMX_SENTINEL + select IMX_ELE imply CMD_DM config ARCH_IMX9 @@ -894,7 +894,7 @@ config ARCH_IMX9 select SUPPORT_SPL select GPIO_EXTRA_HEADER select MISC - select IMX_SENTINEL + select IMX_ELE imply CMD_DM config ARCH_IMXRT diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h index d326a6ea516..f6ec8fda3e6 100644 --- a/arch/arm/include/asm/arch-imx9/ccm_regs.h +++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h @@ -12,7 +12,7 @@ #define ARM_A55_MTR_BUS_CLK_ROOT 1 #define ARM_A55_CLK_ROOT 2 #define M33_CLK_ROOT 3 -#define SENTINEL_CLK_ROOT 4 +#define ELE_CLK_ROOT 4 #define BUS_WAKEUP_CLK_ROOT 5 #define BUS_AON_CLK_ROOT 6 #define WAKEUP_AXI_CLK_ROOT 7 diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 0c130757110..2a222c53882 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -92,8 +92,8 @@ struct arch_global_data { struct udevice *scu_dev; #endif -#ifdef CONFIG_IMX_SENTINEL - struct udevice *s400_dev; +#ifdef CONFIG_IMX_ELE + struct udevice *ele_dev; u32 soc_rev; u32 lifecycle; u32 uid[4]; diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/ele_api.h similarity index 78% rename from arch/arm/include/asm/mach-imx/s400_api.h rename to arch/arm/include/asm/mach-imx/ele_api.h index 5582ff1a254..120da0854e4 100644 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -3,12 +3,12 @@ * Copyright 2021 NXP */ -#ifndef __S400_API_H__ -#define __S400_API_H__ +#ifndef __ELE_API_H__ +#define __ELE_API_H__ -#define AHAB_VERSION 0x6 -#define AHAB_CMD_TAG 0x17 -#define AHAB_RESP_TAG 0xe1 +#define ELE_VERSION 0x6 +#define ELE_CMD_TAG 0x17 +#define ELE_RESP_TAG 0xe1 /* ELE commands */ #define ELE_PING_REQ (0x01) @@ -24,6 +24,8 @@ #define ELE_GET_FW_VERSION_REQ (0x9D) #define ELE_RET_LIFECYCLE_UP_REQ (0xA0) #define ELE_GET_EVENTS_REQ (0xA2) +#define ELE_START_RNG (0xA3) +#define ELE_GENERATE_DEK_BLOB (0xAF) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) #define ELE_GET_FW_STATUS_REQ (0xC5) @@ -109,17 +111,17 @@ #define ELE_SUCCESS_IND (0xD6) #define ELE_FAILURE_IND (0x29) -#define S400_MAX_MSG 255U +#define ELE_MAX_MSG 255U -struct sentinel_msg { +struct ele_msg { u8 version; u8 size; u8 command; u8 tag; - u32 data[(S400_MAX_MSG - 1U)]; + u32 data[(ELE_MAX_MSG - 1U)]; }; -struct sentinel_get_info_data { +struct ele_get_info_data { u32 hdr; u32 soc; u32 lc; @@ -130,19 +132,19 @@ struct sentinel_get_info_data { u32 state; }; -int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response); -int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); -int ahab_release_container(u32 *response); -int ahab_verify_image(u32 img_id, u32 *response); -int ahab_forward_lifecycle(u16 life_cycle, u32 *response); -int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); -int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); -int ahab_release_caam(u32 core_did, u32 *response); -int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); -int ahab_dump_buffer(u32 *buffer, u32 buffer_length); -int ahab_get_info(struct sentinel_get_info_data *info, u32 *response); -int ahab_get_fw_status(u32 *status, u32 *response); -int ahab_release_m33_trout(void); -int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); +int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response); +int ele_release_container(u32 *response); +int ele_verify_image(u32 img_id, u32 *response); +int ele_forward_lifecycle(u16 life_cycle, u32 *response); +int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); +int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); +int ele_release_caam(u32 core_did, u32 *response); +int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); +int ele_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ele_dump_buffer(u32 *buffer, u32 buffer_length); +int ele_get_info(struct ele_get_info_data *info, u32 *response); +int ele_get_fw_status(u32 *status, u32 *response); +int ele_release_m33_trout(void); #endif diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 99fc5402719..9bb37919638 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -7,14 +7,13 @@ #include #include #include -#include +#include #include #include #include #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -267,7 +266,7 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) flush_dcache_range(IMG_CONTAINER_BASE, IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1); - err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp); + err = ele_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp); if (err) { printf("Authenticate container hdr failed, return %d, resp 0x%x\n", err, resp); @@ -282,7 +281,7 @@ int ahab_auth_release(void) int err; u32 resp; - err = ahab_release_container(&resp); + err = ele_release_container(&resp); if (err) { printf("Error: release container failed, resp 0x%x!\n", resp); display_ahab_auth_ind(resp); @@ -296,7 +295,7 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) int err; u32 resp; - err = ahab_verify_image(image_index, &resp); + err = ele_verify_image(image_index, &resp); if (err) { printf("Authenticate img %d failed, return %d, resp 0x%x\n", image_index, err, resp); @@ -485,7 +484,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, return -EPERM; } - err = ahab_forward_lifecycle(8, &resp); + err = ele_forward_lifecycle(8, &resp); if (err != 0) { printf("Error in forward lifecycle to OEM closed\n"); return -EIO; @@ -502,7 +501,7 @@ int ahab_dump(void) int ret, i = 0; do { - ret = ahab_dump_buffer(buffer, 32); + ret = ele_dump_buffer(buffer, 32); if (ret < 0) { printf("Error in dump AHAB log\n"); return -EIO; @@ -547,7 +546,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const display_life_cycle(lc); - ret = ahab_get_events(events, &cnt, NULL); + ret = ele_get_events(events, &cnt, NULL); if (ret) { printf("Get ELE EVENTS error %d\n", ret); return CMD_RET_FAILURE; diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index 50b097b035a..cfc09e79cbd 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include @@ -203,12 +203,12 @@ int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm) int release_rdc(enum rdc_type type) { ulong s_mu_base = 0x27020000UL; - struct sentinel_msg msg; + struct ele_msg msg; int ret; u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74; - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; msg.command = ELE_RELEASE_RDC_REQ; msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */ @@ -266,7 +266,7 @@ void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access) mrgd[4] |= ((access & 0xFFF) << 16); } - /* not handle other cases, since S400 only set ACCESS1 and 2 */ + /* not handle other cases, since ELE only set ACCESS1 and 2 */ writel(mrgd[4], xrdc_base + off + 0x10); return; } @@ -295,7 +295,7 @@ void xrdc_init_mda(void) void xrdc_init_mrc(void) { - /* Re-config MRC3 for SRAM0 in case protected by S400 */ + /* Re-config MRC3 for SRAM0 in case protected by ELE */ xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000); xrdc_config_mrc_dx_perm(3, 0, 0, 1); xrdc_config_mrc_dx_perm(3, 0, 1, 1); @@ -320,7 +320,7 @@ void xrdc_init_mrc(void) xrdc_config_mrc_dx_perm(5, 0, 1, 1); xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF); - /* Set MRC6 for DDR access from Sentinel */ + /* Set MRC6 for DDR access from ELE */ xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); xrdc_config_mrc_dx_perm(6, 0, 4, 1); xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF); @@ -404,7 +404,7 @@ int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_acc val &= ~(0xFU << offset); /* MBC0-3 - * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it. * So select MBC0_MEMN_GLBAC0 */ if (sec_access) { @@ -445,7 +445,7 @@ int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_en continue; /* MRC0,1 - * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it. * So select MRCx_MEMN_GLBAC0 */ if (sec_access) { diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 81eae02b6a8..e23cf60d126 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -70,7 +70,7 @@ int mmc_get_env_dev(void) } #endif -static void set_cpu_info(struct sentinel_get_info_data *info) +static void set_cpu_info(struct ele_get_info_data *info) { gd->arch.soc_rev = info->soc; gd->arch.lifecycle = info->lc; @@ -582,9 +582,9 @@ void get_board_serial(struct tag_serialnr *serialnr) u32 res; int ret; - ret = ahab_read_common_fuse(1, uid, 4, &res); + ret = ele_read_common_fuse(1, uid, 4, &res); if (ret) - printf("ahab read fuse failed %d, 0x%x\n", ret, res); + printf("ele read fuse failed %d, 0x%x\n", ret, res); else printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]); @@ -783,7 +783,7 @@ int imx8ulp_dm_post_init(void) struct udevice *devp; int ret; u32 res; - struct sentinel_get_info_data *info = (struct sentinel_get_info_data *)SRAM0_BASE; + struct ele_get_info_data *info = (struct ele_get_info_data *)SRAM0_BASE; ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp); if (ret) { @@ -791,11 +791,11 @@ int imx8ulp_dm_post_init(void) return ret; } - ret = ahab_get_info(info, &res); + ret = ele_get_info(info, &res); if (ret) { - printf("ahab_get_info failed %d\n", ret); + printf("ele_get_info failed %d\n", ret); /* fallback to A0.1 revision */ - memset((void *)info, 0, sizeof(struct sentinel_get_info_data)); + memset((void *)info, 0, sizeof(struct ele_get_info_data)); info->soc = 0xa000084d; } diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c index fcb02ed3af6..b471a75caa1 100644 --- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c @@ -217,8 +217,8 @@ int upower_init(void) * CM33 Cache * PowerQuad RAM * ETF RAM - * Sentinel PKC, Data RAM1, Inst RAM0/1 - * Sentinel ROM + * ELE PKC, Data RAM1, Inst RAM0/1 + * ELE ROM * uPower IRAM/DRAM * uPower ROM * CM33 ROM @@ -230,7 +230,7 @@ int upower_init(void) * SSRAM Partition 7_a(128KB) * SSRAM Partition 7_b(64KB) * SSRAM Partition 7_c(64KB) - * Sentinel Data RAM0, Inst RAM2 + * ELE Data RAM0, Inst RAM2 */ /* MIPI-CSI FIFO BIT28 not set */ memon = 0x3FFFFFEFFFFFFCUL; diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index a7ecccaf879..766a8811c1f 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -709,8 +709,8 @@ struct imx_clk_setting imx_clk_settings[] = { /* Set A55 mtr bus to 133M */ {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, - /* Sentinel to 133M */ - {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, + /* ELE to 133M */ + {ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* Bus_wakeup to 133M */ {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* Bus_AON to 133M */ @@ -740,8 +740,8 @@ struct imx_clk_setting imx_clk_settings[] = { {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3}, /* Set A55 mtr bus to 133M */ {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, - /* Sentinel to 200M */ - {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2}, + /* ELE to 200M */ + {ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2}, /* Bus_wakeup to 133M */ {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* Bus_AON to 133M */ diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 06b93f60996..7d7ae865946 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -34,7 +34,7 @@ static struct clk_root_map clk_root_array[] = { { ARM_A55_MTR_BUS_CLK_ROOT, 2 }, { ARM_A55_CLK_ROOT, 0 }, { M33_CLK_ROOT, 2 }, - { SENTINEL_CLK_ROOT, 2 }, + { ELE_CLK_ROOT, 2 }, { BUS_WAKEUP_CLK_ROOT, 2 }, { BUS_AON_CLK_ROOT, 2 }, { WAKEUP_AXI_CLK_ROOT, 0 }, diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index a0565f3aea0..f43b73a6c21 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include @@ -151,7 +151,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) return val; } -static void set_cpu_info(struct sentinel_get_info_data *info) +static void set_cpu_info(struct ele_get_info_data *info) { gd->arch.soc_rev = info->soc; gd->arch.lifecycle = info->lc; @@ -557,7 +557,7 @@ int imx9_probe_mu(void *ctx, struct event *event) struct udevice *devp; int node, ret; u32 res; - struct sentinel_get_info_data info; + struct ele_get_info_data info; node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); @@ -568,7 +568,7 @@ int imx9_probe_mu(void *ctx, struct event *event) if (gd->flags & GD_FLG_RELOC) return 0; - ret = ahab_get_info(&info, &res); + ret = ele_get_info(&info, &res); if (ret) return ret; @@ -642,7 +642,7 @@ static int mix_power_init(enum mix_power_domain pd) mem_id = SRC_MEM_MEDIA; scr = BIT(5); - /* Enable S400 handshake */ + /* Enable ELE handshake */ struct blk_ctrl_s_aonmix_regs *s_regs = (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; @@ -759,8 +759,8 @@ int m33_prepare(void) while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT)) val = readl(&mix_regs->func_stat); - /* Release Sentinel TROUT */ - ahab_release_m33_trout(); + /* Release ELE TROUT */ + ele_release_m33_trout(); /* Mask WDOG1 IRQ from A55, we use it for M33 reset */ setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6)); @@ -768,7 +768,7 @@ int m33_prepare(void) /* Turn on WDOG1 clock */ ccm_lpcg_on(CCGR_WDG1, 1); - /* Set sentinel LP handshake for M33 reset */ + /* Set ELE LP handshake for M33 reset */ setbits_le32(&s_regs->lp_handshake[0], BIT(6)); /* Clear M33 TCM for ECC */ diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c index e05c7048106..d0f855bb1bc 100644 --- a/arch/arm/mach-imx/imx9/trdc.c +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #define DID_NUM 16 @@ -196,7 +196,7 @@ int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, val &= ~(0xFU << offset); /* MBC0-3 - * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it. * So select MBC0_MEMN_GLBAC0 */ if (sec_access) { @@ -266,7 +266,7 @@ int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start, continue; /* MRC0,1 - * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it. * So select MRCx_MEMN_GLBAC0 */ if (sec_access) { @@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base) int release_rdc(u8 xrdc) { ulong s_mu_base = 0x47520000UL; - struct sentinel_msg msg; + struct ele_msg msg; int ret; u32 rdc_id; @@ -336,8 +336,8 @@ int release_rdc(u8 xrdc) return -EINVAL; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; msg.command = ELE_RELEASE_RDC_REQ; msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */ @@ -394,7 +394,7 @@ void trdc_init(void) /* DDR */ trdc_mrc_set_control(0x49010000, 0, 0, 0x7777); - /* S400*/ + /* ELE */ trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0); /* MTR */ diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index a0dad5f9831..b7c6ff092b1 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -63,9 +63,9 @@ void display_ele_fw_version(void) u32 fw_version, sha1, res; int ret; - ret = ahab_get_fw_version(&fw_version, &sha1, &res); + ret = ele_get_fw_version(&fw_version, &sha1, &res); if (ret) { - printf("ahab get firmware version failed %d, 0x%x\n", ret, res); + printf("ele get firmware version failed %d, 0x%x\n", ret, res); } else { printf("ELE firmware version %u.%u.%u-%x", (fw_version & (0x00ff0000)) >> 16, @@ -120,9 +120,9 @@ void spl_board_init(void) set_lpav_qos(); /* Enable A35 access to the CAAM */ - ret = ahab_release_caam(0x7, &res); + ret = ele_release_caam(0x7, &res); if (ret) - printf("ahab release caam failed %d, 0x%x\n", ret, res); + printf("ele release caam failed %d, 0x%x\n", ret, res); } void board_init_f(ulong dummy) diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 352ad79cb67..63883b30dd7 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 04460f1acb2..b9f5c7a37ae 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -364,8 +364,8 @@ config NPCM_OTP To compile this driver as a module, choose M here: the module will be called npcm_otp. -config IMX_SENTINEL - bool "Enable i.MX Sentinel MU driver and API" +config IMX_ELE + bool "Enable i.MX EdgeLock Enclave MU driver and API" depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP) help If you say Y here to enable Message Unit driver to work with diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 52aed096021..fd8805f34bd 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -47,7 +47,7 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ -obj-$(CONFIG_IMX_SENTINEL) += sentinel/ +obj-$(CONFIG_IMX_ELE) += imx_ele/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/imx_ele/Makefile similarity index 71% rename from drivers/misc/sentinel/Makefile rename to drivers/misc/imx_ele/Makefile index 446154cb201..f8d8c55f983 100644 --- a/drivers/misc/sentinel/Makefile +++ b/drivers/misc/imx_ele/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += s400_api.o s4mu.o +obj-y += ele_api.o ele_mu.o obj-$(CONFIG_CMD_FUSE) += fuse.o diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/imx_ele/ele_api.c similarity index 63% rename from drivers/misc/sentinel/s400_api.c rename to drivers/misc/imx_ele/ele_api.c index 6c0d0b3f18a..56605714f44 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -9,25 +9,25 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; -int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) +int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; msg.command = ELE_RELEASE_RDC_REQ; switch (xrdc) { @@ -59,20 +59,20 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) return ret; } -int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) +int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 3; msg.command = ELE_OEM_CNTN_AUTH_REQ; msg.data[0] = upper_32_bits(ctnr_addr); @@ -89,20 +89,20 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) return ret; } -int ahab_release_container(u32 *response) +int ele_release_container(u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; msg.command = ELE_RELEASE_CONTAINER_REQ; @@ -117,20 +117,20 @@ int ahab_release_container(u32 *response) return ret; } -int ahab_verify_image(u32 img_id, u32 *response) +int ele_verify_image(u32 img_id, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; msg.command = ELE_VERIFY_IMAGE_REQ; msg.data[0] = 1 << img_id; @@ -146,20 +146,20 @@ int ahab_verify_image(u32 img_id, u32 *response) return ret; } -int ahab_forward_lifecycle(u16 life_cycle, u32 *response) +int ele_forward_lifecycle(u16 life_cycle, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; msg.command = ELE_FWD_LIFECYCLE_UP_REQ; msg.data[0] = life_cycle; @@ -175,15 +175,15 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response) return ret; } -int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) +int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } @@ -198,8 +198,8 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo return -EINVAL; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; msg.command = ELE_READ_FUSE_REQ; msg.data[0] = fuse_id; @@ -223,20 +223,20 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo return ret; } -int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) +int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 3; msg.command = ELE_WRITE_FUSE_REQ; msg.data[0] = (32 << 16) | (fuse_id << 5); @@ -256,20 +256,20 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) return ret; } -int ahab_release_caam(u32 core_did, u32 *response) +int ele_release_caam(u32 core_did, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; msg.command = ELE_RELEASE_CAAM_REQ; msg.data[0] = core_did; @@ -285,15 +285,15 @@ int ahab_release_caam(u32 core_did, u32 *response) return ret; } -int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) +int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } @@ -307,8 +307,8 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) return -EINVAL; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; msg.command = ELE_GET_FW_VERSION_REQ; @@ -326,20 +326,20 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) return ret; } -int ahab_dump_buffer(u32 *buffer, u32 buffer_length) +int ele_dump_buffer(u32 *buffer, u32 buffer_length) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret, i = 0; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; msg.command = ELE_DUMP_DEBUG_BUFFER_REQ; @@ -360,25 +360,25 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length) return i; } -int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) +int ele_get_info(struct ele_get_info_data *info, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 4; msg.command = ELE_GET_INFO_REQ; msg.data[0] = upper_32_bits((ulong)info); msg.data[1] = lower_32_bits((ulong)info); - msg.data[2] = sizeof(struct sentinel_get_info_data); + msg.data[2] = sizeof(struct ele_get_info_data); ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -391,20 +391,20 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) return ret; } -int ahab_get_fw_status(u32 *status, u32 *response) +int ele_get_fw_status(u32 *status, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; msg.command = ELE_GET_FW_STATUS_REQ; @@ -421,20 +421,20 @@ int ahab_get_fw_status(u32 *status, u32 *response) return ret; } -int ahab_release_m33_trout(void) +int ele_release_m33_trout(void) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; msg.command = ELE_ENABLE_RTC_REQ; @@ -446,16 +446,16 @@ int ahab_release_m33_trout(void) return ret; } -int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response) +int ele_get_events(u32 *events, u32 *events_cnt, u32 *response) { - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret, i = 0; u32 actual_events; if (!dev) { - printf("s400 dev is not initialized\n"); + printf("ele dev is not initialized\n"); return -ENODEV; } @@ -464,8 +464,8 @@ int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response) return -EINVAL; } - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; msg.command = ELE_GET_EVENTS_REQ; diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/imx_ele/ele_mu.c similarity index 93% rename from drivers/misc/sentinel/s4mu.c rename to drivers/misc/imx_ele/ele_mu.c index 794fc40c620..0d34b8c9010 100644 --- a/drivers/misc/sentinel/s4mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include @@ -85,7 +85,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) static int imx8ulp_mu_read(struct mu_type *base, void *data) { - struct sentinel_msg *msg = (struct sentinel_msg *)data; + struct ele_msg *msg = (struct ele_msg *)data; int ret; u8 count = 0; @@ -99,7 +99,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data) count++; /* Check size */ - if (msg->size > S400_MAX_MSG) { + if (msg->size > ELE_MAX_MSG) { *((u32 *)msg) = 0; return -EINVAL; } @@ -118,7 +118,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data) static int imx8ulp_mu_write(struct mu_type *base, void *data) { - struct sentinel_msg *msg = (struct sentinel_msg *)data; + struct ele_msg *msg = (struct ele_msg *)data; int ret; u8 count = 0; @@ -126,7 +126,7 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data) return -EINVAL; /* Check size */ - if (msg->size > S400_MAX_MSG) + if (msg->size > ELE_MAX_MSG) return -EINVAL; /* Write first word */ @@ -171,7 +171,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, return ret; } - result = ((struct sentinel_msg *)rx_msg)->data[0]; + result = ((struct ele_msg *)rx_msg)->data[0]; if ((result & 0xff) == 0xd6) return 0; @@ -196,7 +196,7 @@ static int imx8ulp_mu_probe(struct udevice *dev) /* U-Boot not enable interrupts, so need to enable RX interrupts */ mu_hal_init((ulong)priv->base); - gd->arch.s400_dev = dev; + gd->arch.ele_dev = dev; return 0; } diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/imx_ele/fuse.c similarity index 84% rename from drivers/misc/sentinel/fuse.c rename to drivers/misc/imx_ele/fuse.c index 99342d33c06..4e4dcb42cdd 100644 --- a/drivers/misc/sentinel/fuse.c +++ b/drivers/misc/imx_ele/fuse.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -24,11 +24,11 @@ struct fsb_map_entry { bool redundancy; }; -struct s400_map_entry { +struct ele_map_entry { s32 fuse_bank; u32 fuse_words; u32 fuse_offset; - u32 s400_index; + u32 ele_index; }; #if defined(CONFIG_IMX8ULP) @@ -65,7 +65,7 @@ u32 nonecc_fuse_banks[] = { 0, 1, 8, 12, 16, 22, 24, 25, 26, 27, 36, 41, 51, 56 }; -struct s400_map_entry s400_api_mapping_table[] = { +struct ele_map_entry ele_api_mapping_table[] = { { 1, 8 }, /* LOCK */ { 2, 8 }, /* ECID */ { 7, 4, 0, 1 }, /* OTP_UNIQ_ID */ @@ -122,7 +122,7 @@ struct fsb_map_entry fsb_mapping_table[] = { { 63, 8 }, }; -struct s400_map_entry s400_api_mapping_table[] = { +struct ele_map_entry ele_api_mapping_table[] = { { 7, 1, 7, 63 }, { 16, 8, }, { 17, 8, }, @@ -159,18 +159,18 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy) return word + word_pos; } -static s32 map_s400_fuse_index(u32 bank, u32 word) +static s32 map_ele_fuse_index(u32 bank, u32 word) { - s32 size = ARRAY_SIZE(s400_api_mapping_table); + s32 size = ARRAY_SIZE(ele_api_mapping_table); s32 i; /* map the fuse from ocotp fuse map to FSB*/ for (i = 0; i < size; i++) { - if (s400_api_mapping_table[i].fuse_bank != -1 && - s400_api_mapping_table[i].fuse_bank == bank) { - if (word >= s400_api_mapping_table[i].fuse_offset && - word < (s400_api_mapping_table[i].fuse_offset + - s400_api_mapping_table[i].fuse_words)) + if (ele_api_mapping_table[i].fuse_bank != -1 && + ele_api_mapping_table[i].fuse_bank == bank) { + if (word >= ele_api_mapping_table[i].fuse_offset && + word < (ele_api_mapping_table[i].fuse_offset + + ele_api_mapping_table[i].fuse_words)) break; } } @@ -178,10 +178,10 @@ static s32 map_s400_fuse_index(u32 bank, u32 word) if (i == size) return -1; /* Failed to find */ - if (s400_api_mapping_table[i].s400_index != 0) - return s400_api_mapping_table[i].s400_index; + if (ele_api_mapping_table[i].ele_index != 0) + return ele_api_mapping_table[i].ele_index; - return s400_api_mapping_table[i].fuse_bank * 8 + word; + return ele_api_mapping_table[i].fuse_bank * 8 + word; } #if defined(CONFIG_IMX8ULP) @@ -202,7 +202,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val) return 0; } - word_index = map_s400_fuse_index(bank, word); + word_index = map_ele_fuse_index(bank, word); if (word_index >= 0) { u32 data[4]; u32 res, size = 4; @@ -212,7 +212,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val) if (word_index != 1) size = 1; - ret = ahab_read_common_fuse(word_index, data, size, &res); + ret = ele_read_common_fuse(word_index, data, size, &res); if (ret) { printf("ahab read fuse failed %d, 0x%x\n", ret, res); return ret; @@ -255,13 +255,13 @@ int fuse_sense(u32 bank, u32 word, u32 *val) return 0; } - word_index = map_s400_fuse_index(bank, word); + word_index = map_ele_fuse_index(bank, word); if (word_index >= 0) { u32 data; u32 res, size = 1; int ret; - ret = ahab_read_common_fuse(word_index, &data, size, &res); + ret = ele_read_common_fuse(word_index, &data, size, &res); if (ret) { printf("ahab read fuse failed %d, 0x%x\n", ret, res); return ret; @@ -304,7 +304,7 @@ int fuse_prog(u32 bank, u32 word, u32 val) lock = true; #endif - ret = ahab_write_fuse((bank * 8 + word), val, lock, &res); + ret = ele_write_fuse((bank * 8 + word), val, lock, &res); if (ret) { printf("ahab write fuse failed %d, 0x%x\n", ret, res); return ret; From 914ede697876295e5554133e74e03d68e11ed7c9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:06 +0800 Subject: [PATCH 063/109] imx: parse-container: fix build warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix build warning: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3 has type ‘u64’ {aka ‘long long unsigned int’} [-Wformat=] printf("can't find memreg for image %d load address 0x%x, error %d\n", warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘sc_faddr_t’ {aka ‘long long unsigned int’} [-Wformat=] debug("memreg %u 0x%lx -- 0x%lx\n", mr, start, end); Signed-off-by: Peng Fan --- arch/arm/mach-imx/parse-container.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index f7582825d6d..a0d1eb3831c 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -35,14 +35,14 @@ static int authenticate_image(struct boot_img_t *img, int image_index) ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1); if (err) { - printf("can't find memreg for image %d load address 0x%x, error %d\n", + printf("can't find memreg for image %d load address 0x%llx, error %d\n", image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err); return -ENOMEM; } err = sc_rm_get_memreg_info(-1, mr, &start, &end); if (!err) - debug("memreg %u 0x%x -- 0x%x\n", mr, start, end); + debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, SC_RM_PERM_FULL); From ef5bdfc273c8562da80091a6f63910b6cabf8f4a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:07 +0800 Subject: [PATCH 064/109] imx: ele_ahab: use hextoul Use hextoul which looks a bit simpler. Signed-off-by: Peng Fan --- arch/arm/mach-imx/ele_ahab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 9bb37919638..5f23486304c 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -402,7 +402,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 2) return CMD_RET_USAGE; - addr = simple_strtoul(argv[1], NULL, 16); + addr = hextoul(argv[1], NULL); printf("Authenticate OS container at 0x%lx\n", addr); From 31e5ec23238b884109dbfde9390b7f7b3bba1520 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:08 +0800 Subject: [PATCH 065/109] imx: ele_api: support program secure fuse and return lifecycle Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/ele_api.h | 2 + arch/arm/mach-imx/ele_ahab.c | 74 +++++++++++++++++++++++++ drivers/misc/imx_ele/ele_api.c | 64 ++++++++++++++++++++- 3 files changed, 139 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 120da0854e4..477cfe73ab0 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -146,5 +146,7 @@ int ele_dump_buffer(u32 *buffer, u32 buffer_length); int ele_get_info(struct ele_get_info_data *info, u32 *response); int ele_get_fw_status(u32 *status, u32 *response); int ele_release_m33_trout(void); +int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); +int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); #endif diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 5f23486304c..785b0d6ec3c 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -563,6 +563,68 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const return 0; } +static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + ulong addr; + u32 header, response; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = hextoul(argv[1], NULL); + header = *(u32 *)addr; + + if ((header & 0xff0000ff) != 0x89000000) { + printf("Wrong Signed message block format, header 0x%x\n", header); + return CMD_RET_FAILURE; + } + + header = (header & 0xffff00) >> 8; + + printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header); + flush_dcache_range(addr, addr + header - 1); + + if (ele_write_secure_fuse(addr, &response)) { + printf("Program secure fuse failed, response 0x%x\n", response); + return CMD_RET_FAILURE; + } + + printf("Program secure fuse completed, response 0x%x\n", response); + + return CMD_RET_SUCCESS; +} + +static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + ulong addr; + u32 header, response; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = hextoul(argv[1], NULL); + header = *(u32 *)addr; + + if ((header & 0xff0000ff) != 0x89000000) { + printf("Wrong Signed message block format, header 0x%x\n", header); + return CMD_RET_FAILURE; + } + + header = (header & 0xffff00) >> 8; + + printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header); + flush_dcache_range(addr, addr + header - 1); + + if (ele_return_lifecycle_update(addr, &response)) { + printf("Return lifecycle failed, response 0x%x\n", response); + return CMD_RET_FAILURE; + } + + printf("Return lifecycle completed, response 0x%x\n", response); + + return CMD_RET_SUCCESS; +} + U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, "autenticate OS container via AHAB", "addr\n" @@ -583,3 +645,15 @@ U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, "display AHAB lifecycle only", "" ); + +U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog, + "Program secure fuse via signed message block", + "addr\n" + "addr - Signed message block for secure fuse\n" +); + +U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycle, + "Return lifecycle to OEM field return via signed message block", + "addr\n" + "addr - Return lifecycle message block signed by OEM SRK\n" +); diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 56605714f44..0ca0a94f08c 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2020 NXP + * Copyright 2020, 2023 NXP * */ @@ -490,3 +490,65 @@ int ele_get_events(u32 *events, u32 *events_cnt, u32 *response) return ret; } + +int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_SECURE_FUSE_REQ; + + msg.data[0] = upper_32_bits(signed_msg_blk); + msg.data[1] = lower_32_bits(signed_msg_blk); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n", + __func__, ret, msg.data[0], msg.data[1]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_RET_LIFECYCLE_UP_REQ; + + msg.data[0] = upper_32_bits(signed_msg_blk); + msg.data[1] = lower_32_bits(signed_msg_blk); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n", + __func__, ret, msg.data[0], msg.data[1]); + + if (response) + *response = msg.data[0]; + + return ret; +} From d0e2a012a3832573a510b7323840d2d6f74dd0a7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:09 +0800 Subject: [PATCH 066/109] imx: ele_api: add DEK Blob generation - Add crc computation. - Add ele_generate_dek_blob API for encrypted boot support. Signed-off-by: Clement Faure Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/ele_api.h | 2 +- drivers/misc/imx_ele/ele_api.c | 44 +++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 477cfe73ab0..053a23f030b 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -142,11 +142,11 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon int ele_release_caam(u32 core_did, u32 *response); int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); int ele_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size); int ele_dump_buffer(u32 *buffer, u32 buffer_length); int ele_get_info(struct ele_get_info_data *info, u32 *response); int ele_get_fw_status(u32 *status, u32 *response); int ele_release_m33_trout(void); int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); - #endif diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 0ca0a94f08c..8a14cf6aa92 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR; +static u32 compute_crc(const struct ele_msg *msg) +{ + u32 crc = 0; + size_t i = 0; + u32 *data = (u32 *)msg; + + for (i = 0; i < (msg->size - 1); i++) + crc ^= data[i]; + + return crc; +} + int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response) { struct udevice *dev = gd->arch.ele_dev; @@ -552,3 +564,35 @@ int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response) return ret; } + +int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 8; + msg.command = ELE_GENERATE_DEK_BLOB; + msg.data[0] = key_id; + msg.data[1] = 0x0; + msg.data[2] = src_paddr; + msg.data[3] = 0x0; + msg.data[4] = dst_paddr; + msg.data[5] = max_output_size; + msg.data[6] = compute_crc(&msg); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret 0x%x, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +} From f0e974e1e4f2c88ec4c09c7ab0fc9df6b7306d21 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:10 +0800 Subject: [PATCH 067/109] imx: cmd_dek: Fix Uninitialized pointer read Fix Coverity (CID 21143558). When tee_shm_register returns failure, the shm_input pointer is invalid, should not free it. Same issue also exists on registering shm_output. Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/cmd_dek.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index d77a49df860..0be9df521a5 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -101,6 +101,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) 0x0, &shm_output); if (ret < 0) { printf("Cannot register output shared memory 0x%X\n", ret); + tee_shm_free(shm_input); goto error; } @@ -122,11 +123,11 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) if (ret < 0) printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret); -error: /* Free shared memory */ tee_shm_free(shm_input); tee_shm_free(shm_output); +error: /* Close session */ ret = tee_close_session(dev, arg.session); if (ret < 0) From 859f4e02a8fa9be522a5aefcc56a5dd8f702e5be Mon Sep 17 00:00:00 2001 From: Clement Faure Date: Thu, 15 Jun 2023 18:09:11 +0800 Subject: [PATCH 068/109] imx: cmd_dek: add ELE DEK Blob generation support Add ELE DEK Blob generation for the cmd_dek command. Signed-off-by: Clement Faure Signed-off-by: Peng Fan --- arch/arm/mach-imx/Kconfig | 7 ++++ arch/arm/mach-imx/cmd_dek.c | 84 +++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3266545c266..2cca89d4bb1 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -86,6 +86,7 @@ config CMD_DEKBLOB select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M select IMX_SECO_DEK_ENCAP if ARCH_IMX8 + select IMX_ELE_DEK_ENCAP if ARCH_IMX8ULP || ARCH_IMX9 help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and @@ -113,6 +114,12 @@ config IMX_SECO_DEK_ENCAP This enabled the DEK blob encapsulation with the SECO API. This option is only available on imx8. +config IMX_ELE_DEK_ENCAP + bool "Support the DEK blob encapsulation with ELE" + help + This enabled the DEK blob encapsulation with the ELE API. This option + is only available on imx8ulp and imx9. + config CMD_PRIBLOB bool "Support the set_priblob_bitfield command" depends on HAS_CAAM && IMX_HAB diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 0be9df521a5..6fa5b41fcd3 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2022 NXP * * Command for encapsulating DEK blob */ @@ -20,6 +21,11 @@ #include #include #endif +#ifdef CONFIG_IMX_ELE_DEK_ENCAP +#include +#include +#endif + #include /** @@ -284,6 +290,84 @@ error: } #endif /* CONFIG_IMX_SECO_DEK_ENCAP */ +#ifdef CONFIG_IMX_ELE_DEK_ENCAP + +#define DEK_BLOB_HDR_SIZE 8 +#define AHAB_PRIVATE_KEY 0x81 +#define AHAB_DEK_BLOB 0x01 +#define AHAB_ALG_AES 0x03 +#define AHAB_128_AES_KEY 0x10 +#define AHAB_192_AES_KEY 0x18 +#define AHAB_256_AES_KEY 0x20 + +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) +{ + u8 in_size, out_size; + u8 *src_ptr, *dst_ptr; + struct generate_key_blob_hdr hdr; + + /* Set sizes */ + in_size = sizeof(struct generate_key_blob_hdr) + len / 8; + out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE; + + /* Get src and dst virtual addresses */ + src_ptr = map_sysmem(src_addr, in_size); + dst_ptr = map_sysmem(dst_addr, out_size); + + /* Check addr input */ + if (!(src_ptr && dst_ptr)) { + debug("src_addr or dst_addr invalid\n"); + return -1; + } + + /* Build key header */ + hdr.version = 0x0; + hdr.length_lsb = in_size; + hdr.length_msb = 0x00; + hdr.tag = AHAB_PRIVATE_KEY; + hdr.flags = AHAB_DEK_BLOB; + hdr.algorithm = AHAB_ALG_AES; + hdr.mode = 0x0; /* Not used by the ELE */ + + switch (len) { + case 128: + hdr.size = AHAB_128_AES_KEY; + break; + case 192: + hdr.size = AHAB_192_AES_KEY; + break; + case 256: + hdr.size = AHAB_256_AES_KEY; + break; + default: + /* Not supported */ + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + /* Move input key and append blob header */ + memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)), + (void *)src_ptr, len / 8); + memcpy((void *)src_ptr, (void *)&hdr, + sizeof(struct generate_key_blob_hdr)); + + /* Flush the cache */ + flush_dcache_range(src_addr, src_addr + in_size); + flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + /* Call ELE */ + if (ele_generate_dek_blob(0x00, src_addr, dst_addr, out_size)) + return -1; + + /* Invalidate output buffer */ + invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + return 0; +} +#endif /* CONFIG_IMX_ELE_DEK_ENCAP */ + /** * do_dek_blob() - Handle the "dek_blob" command-line command * @cmdtp: Command data struct pointer From 71a21425d278a07ba263109fff0cba09ff30a157 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:12 +0800 Subject: [PATCH 069/109] imx: misc: ele_mu: Update MU TR registers count According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All of them are used for ELE message. So update TR count to 8 and fix a typo in receive msg Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/misc/imx_ele/ele_mu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 0d34b8c9010..956f8a1eb2f 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -22,7 +22,7 @@ struct imx8ulp_mu { #define MU_SR_TE0_MASK BIT(0) #define MU_SR_RF0_MASK BIT(0) -#define MU_TR_COUNT 4 +#define MU_TR_COUNT 8 #define MU_RR_COUNT 4 void mu_hal_init(ulong base) @@ -65,7 +65,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) u32 val; int ret; - assert(reg_index < MU_TR_COUNT); + assert(reg_index < MU_RR_COUNT); debug("receivemsg sr 0x%x\n", readl(&mu_base->sr)); From 78b4cf75307f4704881b7b7501721f27f2691f9f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:13 +0800 Subject: [PATCH 070/109] imx: misc: ele_mu: Update ELE MU driver Extend the RX timeout value to 10s, because when authentication is failed the ELE needs long time (>2s for 28M image) to return the result. Print rx wait info per 1s. Also correct TX and RX status registers in debug. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/misc/imx_ele/ele_mu.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 956f8a1eb2f..053cdcf0fe0 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -42,7 +42,7 @@ int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg) assert(reg_index < MU_TR_COUNT); - debug("sendmsg sr 0x%x\n", readl(&mu_base->sr)); + debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr)); /* Wait TX register to be empty. */ ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000); @@ -64,14 +64,24 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) u32 mask = MU_SR_RF0_MASK << reg_index; u32 val; int ret; + u32 count = 10; assert(reg_index < MU_RR_COUNT); - debug("receivemsg sr 0x%x\n", readl(&mu_base->sr)); + debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr)); - /* Wait RX register to be full. */ - ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000); - if (ret < 0) { + do { + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 1000000); + if (ret < 0) { + count--; + printf("mu receive msg wait %us\n", 10 - count); + } else { + break; + } + } while (count > 0); + + if (count == 0) { debug("%s timeout\n", __func__); return -ETIMEDOUT; } From 1c3f5df2597b80d4dac635152fc5dd1a9c4150b9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:14 +0800 Subject: [PATCH 071/109] imx: imx8ulp: start the ELE RNG at boot On the imx8ulp A1 SoC, the ELE RNG needs to be manually started. Signed-off-by: Clement Faure Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/ele_api.h | 1 + board/freescale/imx8ulp_evk/spl.c | 10 ++++++++++ drivers/misc/imx_ele/ele_api.c | 25 +++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 053a23f030b..cfd4ecebb62 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -149,4 +149,5 @@ int ele_get_fw_status(u32 *status, u32 *response); int ele_release_m33_trout(void); int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); +int ele_start_rng(void); #endif diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index b7c6ff092b1..66d0f68cc62 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -123,6 +123,16 @@ void spl_board_init(void) ret = ele_release_caam(0x7, &res); if (ret) printf("ele release caam failed %d, 0x%x\n", ret, res); + + /* + * RNG start only available on the A1 soc revision. + * Check some JTAG register for the SoC revision. + */ + if (!is_soc_rev(CHIP_REV_1_0)) { + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + } } void board_init_f(ulong dummy) diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 8a14cf6aa92..0c017734a49 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -503,6 +503,31 @@ int ele_get_events(u32 *events, u32 *events_cnt, u32 *response) return ret; } +int ele_start_rng(void) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_START_RNG; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +} + int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response) { struct udevice *dev = gd->arch.ele_dev; From b645f95da97b1d7e11af34c2c3f7a01843aac94c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:15 +0800 Subject: [PATCH 072/109] imx: hab: Fix coverity issue in HAB event decoding Fix below coverity issues caused by get_idx function where "-1" is compared with uint8_t "element" 343336 Unsigned compared with neg 343337 Operands don't affect result Additional, this function returns "-1" will cause overflow to event string array. Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/hab.c | 41 ++++++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 439cdaf07a7..b3ef36c7973 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -289,9 +289,10 @@ static char *rsn_str[] = { }; static char *sts_str[] = { - "STS = HAB_SUCCESS (0xF0)\n", + "STS = HAB_STS_ANY (0x00)\n", "STS = HAB_FAILURE (0x33)\n", "STS = HAB_WARNING (0x69)\n", + "STS = HAB_SUCCESS (0xF0)\n", "STS = INVALID\n", NULL }; @@ -336,8 +337,7 @@ static uint8_t hab_statuses[5] = { HAB_STS_ANY, HAB_FAILURE, HAB_WARNING, - HAB_SUCCESS, - -1 + HAB_SUCCESS }; static uint8_t hab_reasons[26] = { @@ -365,8 +365,7 @@ static uint8_t hab_reasons[26] = { HAB_UNS_ITEM, HAB_UNS_KEY, HAB_UNS_PROTOCOL, - HAB_UNS_STATE, - -1 + HAB_UNS_STATE }; static uint8_t hab_contexts[12] = { @@ -380,8 +379,7 @@ static uint8_t hab_contexts[12] = { HAB_CTX_COMMAND, HAB_CTX_AUT_DAT, HAB_CTX_ASSERT, - HAB_CTX_EXIT, - -1 + HAB_CTX_EXIT }; static uint8_t hab_engines[16] = { @@ -399,30 +397,35 @@ static uint8_t hab_engines[16] = { HAB_ENG_ROM, HAB_ENG_HDCP, HAB_ENG_RTL, - HAB_ENG_SW, - -1 + HAB_ENG_SW }; -static inline uint8_t get_idx(uint8_t *list, uint8_t tgt) +static inline u32 get_idx(u8 *list, u8 tgt, u32 size) { - uint8_t idx = 0; - uint8_t element = list[idx]; - while (element != -1) { + u32 idx = 0; + u8 element; + + while (idx < size) { + element = list[idx]; if (element == tgt) return idx; - element = list[++idx]; + ++idx; } - return -1; + return idx; } static void process_event_record(uint8_t *event_data, size_t bytes) { struct record *rec = (struct record *)event_data; - printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]); - printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]); - printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]); - printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]); + printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0], + ARRAY_SIZE(hab_statuses))]); + printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1], + ARRAY_SIZE(hab_reasons))]); + printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2], + ARRAY_SIZE(hab_contexts))]); + printf("%s", eng_str[get_idx(hab_engines, rec->contents[3], + ARRAY_SIZE(hab_engines))]); } static void display_event(uint8_t *event_data, size_t bytes) From 3b5c1d0ea100933d3fadda82051ede62b5209c89 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:16 +0800 Subject: [PATCH 073/109] imx: image-container: Fix container header checking Checking container header tag and version is wrong, it causes to fail to bypass invalid container Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/image-container.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 5b059a64292..745de130630 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -31,7 +31,7 @@ int get_container_size(ulong addr, u16 *header_length) u32 max_offset = 0, img_end; phdr = (struct container_hdr *)addr; - if (phdr->tag != 0x87 && phdr->version != 0x0) { + if (phdr->tag != 0x87 || phdr->version != 0x0) { debug("Wrong container header\n"); return -EFAULT; } From 455ebf8f455d4bd78237884aaf948c54fb6639b6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:17 +0800 Subject: [PATCH 074/109] imx: iamge-container: support secondary container Add the support for loading image from secondary container set on iMX8QM B0, iMX8QXP C0. Using the SCFW API to get container set index, if it is the secondary boot, get the offset from fuse and apply to offset of current container set beginning for loading. Also override the emmc boot partition to check secondary boot and switch to the other boot part. This patch is modified from NXP downstream: imx8: Fix the fuse used by secondary container offset imx: container: Skip container set check for ROM API imx8: spl: Support booting from secondary container set Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/image-container.c | 94 ++++++++++++++++++++++++++--- 1 file changed, 87 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 745de130630..5f188ab32d1 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -22,6 +22,25 @@ #define QSPI_NOR_DEV 3 #define ROM_API_DEV 4 +/* The unit of second image offset number which provision by the fuse bits */ +#define SND_IMG_OFF_UNIT (0x100000UL) + +/* + * If num = 0, off = (2 ^ 2) * 1MB + * else If num = 2, off = (2 ^ 0) * 1MB + * else off = (2 ^ num) * 1MB + */ +#define SND_IMG_NUM_TO_OFF(num) \ + ((1UL << ((0 == (num)) ? 2 : (2 == (num)) ? 0 : (num))) * SND_IMG_OFF_UNIT) + +#define GET_SND_IMG_NUM(fuse) (((fuse) >> 24) & 0x1F) + +#if defined(CONFIG_IMX8QM) +#define FUSE_IMG_SET_OFF_WORD 464 +#elif defined(CONFIG_IMX8QXP) +#define FUSE_IMG_SET_OFF_WORD 720 +#endif + int get_container_size(ulong addr, u16 *header_length) { struct container_hdr *phdr; @@ -136,15 +155,53 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, return ret; } +static bool check_secondary_cnt_set(unsigned long *set_off) +{ +#if IS_ENABLED(CONFIG_ARCH_IMX8) + int ret; + u8 set_id = 1; + u32 fuse_val = 0; + + if (!(is_imx8qxp() && is_soc_rev(CHIP_REV_B))) { + ret = sc_misc_get_boot_container(-1, &set_id); + if (ret) + return false; + /* Secondary boot */ + if (set_id == 2) { + ret = sc_misc_otp_fuse_read(-1, FUSE_IMG_SET_OFF_WORD, &fuse_val); + if (!ret) { + if (set_off) + *set_off = SND_IMG_NUM_TO_OFF(GET_SND_IMG_NUM(fuse_val)); + return true; + } + } + } +#endif + + return false; +} + static unsigned long get_boot_device_offset(void *dev, int dev_type) { - unsigned long offset = 0; + unsigned long offset = 0, sec_set_off = 0; + bool sec_boot = false; + + if (dev_type == ROM_API_DEV) { + offset = (unsigned long)dev; + return offset; + } + + sec_boot = check_secondary_cnt_set(&sec_set_off); + if (sec_boot) + printf("Secondary set selected\n"); + else + printf("Primary set selected\n"); if (dev_type == MMC_DEV) { struct mmc *mmc = (struct mmc *)dev; if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { - offset = CONTAINER_HDR_MMCSD_OFFSET; + offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; } else { u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); @@ -154,19 +211,23 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) else offset = CONTAINER_HDR_EMMC_OFFSET; } else { - offset = CONTAINER_HDR_MMCSD_OFFSET; + offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; } } } else if (dev_type == QSPI_DEV) { - offset = CONTAINER_HDR_QSPI_OFFSET; + offset = sec_boot ? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : + CONTAINER_HDR_QSPI_OFFSET; } else if (dev_type == NAND_DEV) { - offset = CONTAINER_HDR_NAND_OFFSET; + offset = sec_boot ? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : + CONTAINER_HDR_NAND_OFFSET; } else if (dev_type == QSPI_NOR_DEV) { offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; - } else if (dev_type == ROM_API_DEV) { - offset = (unsigned long)dev; + } else { + printf("Not supported dev_type: %d\n", dev_type); } + debug("container set offset 0x%lx\n", offset); + return offset; } @@ -227,6 +288,25 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return end / mmc->read_bl_len; } + +int spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int part; + + part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + if (part == 1 || part == 2) { + unsigned long sec_set_off = 0; + bool sec_boot = false; + + sec_boot = check_secondary_cnt_set(&sec_set_off); + if (sec_boot) + part = (part == 1) ? 2 : 1; + } else if (part == 7) { + part = 0; + } + + return part; +} #endif #ifdef CONFIG_SPL_NAND_SUPPORT From 9395eb05ee816fd8e5082e10e84391e5a621d9f0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:18 +0800 Subject: [PATCH 075/109] imx: bootaux: change names of MACROs used to boot MCU on iMX devices The current bootaux supports i.MX8M and i.MX93, but the name "_M4_" implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4, i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place of "_M4_" to simplify the naming. Signed-off-by: faqiang.zhu Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +- arch/arm/include/asm/arch-mx7/imx-regs.h | 2 +- arch/arm/mach-imx/imx9/imx_bootaux.c | 6 +++--- arch/arm/mach-imx/imx_bootaux.c | 24 +++++++++++----------- board/kontron/sl-mx8mm/sl-mx8mm.c | 2 +- board/kontron/sl-mx8mm/spl.c | 2 +- board/technexion/pico-imx8mq/pico-imx8mq.c | 2 +- board/technexion/pico-imx8mq/spl.c | 2 +- include/imx_sip.h | 6 +++--- 10 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 6e2fc82a0e4..8632eddb530 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -13,7 +13,7 @@ #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 -#define M4_BOOTROM_BASE_ADDR 0x007E0000 +#define MCU_BOOTROM_BASE_ADDR 0x007E0000 #define GPIO1_BASE_ADDR 0X30200000 #define GPIO2_BASE_ADDR 0x30210000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 72944af18a4..8fd3dd2df3a 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -23,7 +23,7 @@ #define GPU_ARB_END_ADDR 0x01803FFF #define APBH_DMA_ARB_BASE_ADDR 0x01804000 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF -#define M4_BOOTROM_BASE_ADDR 0x007F8000 +#define MCU_BOOTROM_BASE_ADDR 0x007F8000 #elif !defined(CONFIG_MX6SLL) #define CAAM_ARB_BASE_ADDR 0x00100000 diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index c863cd9da36..6f5ae5173c0 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -18,7 +18,7 @@ #define GIC400_ARB_END_ADDR 0x31007FFF #define APBH_DMA_ARB_BASE_ADDR 0x33000000 #define APBH_DMA_ARB_END_ADDR 0x33007FFF -#define M4_BOOTROM_BASE_ADDR 0x00180000 +#define MCU_BOOTROM_BASE_ADDR 0x00180000 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c index 256e6fa1c54..6afb59e0515 100644 --- a/arch/arm/mach-imx/imx9/imx_bootaux.c +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -13,7 +13,7 @@ int arch_auxiliary_core_check_up(u32 core_id) { struct arm_smccc_res res; - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res); return res.a0; @@ -25,7 +25,7 @@ int arch_auxiliary_core_down(u32 core_id) printf("## Stopping auxiliary core\n"); - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0, 0, 0, 0, 0, &res); return 0; @@ -40,7 +40,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) printf("## Starting auxiliary core addr = 0x%08lX...\n", addr); - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0, 0, 0, 0, 0, &res); return 0; diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 888c53d6901..2b97aae3a23 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -124,15 +124,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", stack, pc); - /* Set the stack and pc to M4 bootROM */ - writel(stack, M4_BOOTROM_BASE_ADDR); - writel(pc, M4_BOOTROM_BASE_ADDR + 4); + /* Set the stack and pc to MCU bootROM */ + writel(stack, MCU_BOOTROM_BASE_ADDR); + writel(pc, MCU_BOOTROM_BASE_ADDR + 4); flush_dcache_all(); - /* Enable M4 */ + /* Enable MCU */ if (IS_ENABLED(CONFIG_IMX8M)) { - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL); + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0, 0, 0, NULL); } else { clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); @@ -147,7 +147,7 @@ int arch_auxiliary_core_check_up(u32 core_id) unsigned int val; if (IS_ENABLED(CONFIG_IMX8M)) { - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res); return res.a0; } @@ -164,13 +164,13 @@ int arch_auxiliary_core_check_up(u32 core_id) * the reset vector at the head for the image, with SP and PC * as the first two words. * - * Per the cortex-M reference manual, the reset vector of M4 needs - * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses - * of that vector. So to boot M4, the A core must build the M4's reset + * Per the cortex-M reference manual, the reset vector of M4/M7 needs + * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses + * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset * vector with getting the PC and SP from image and filling them to - * TCMUL. When M4 is kicked, it will load the PC and SP by itself. - * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for - * accessing the M4 TCMUL. + * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself. + * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for + * accessing the M4/M7 TCMUL/IDTCM. */ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index ddb509eb66b..8dcc2ea54f6 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -37,7 +37,7 @@ struct efi_capsule_update_info update_info = { int board_phys_sdram_size(phys_size_t *size) { - u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR); + u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR); if (ddr_size == 4) { *size = 0x100000000; diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 3a919d0a9c3..b49373442a2 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -106,7 +106,7 @@ static void spl_dram_init(void) } gd->ram_size = size; - writel(size, M4_BOOTROM_BASE_ADDR); + writel(size, MCU_BOOTROM_BASE_ADDR); } int do_board_detect(void) diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 951e3e1985b..2be3206f78a 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -54,7 +54,7 @@ int board_early_init_f(void) int board_phys_sdram_size(phys_size_t *size) { - int ddr_size = readl(M4_BOOTROM_BASE_ADDR); + int ddr_size = readl(MCU_BOOTROM_BASE_ADDR); if (ddr_size == 0x4) { *size = 0x100000000; diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index 8b853a914e8..2afb4d37608 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -89,7 +89,7 @@ static void spl_dram_init(void) printf("%s: LPDDR4 %d GiB\n", __func__, size); ddr_init(dram_timing); - writel(size, M4_BOOTROM_BASE_ADDR); + writel(size, MCU_BOOTROM_BASE_ADDR); } #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) diff --git a/include/imx_sip.h b/include/imx_sip.h index ebbb3a16d7e..8a5ca34f393 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -13,8 +13,8 @@ #define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 #define IMX_SIP_SRC 0xC2000005 -#define IMX_SIP_SRC_M4_START 0x00 -#define IMX_SIP_SRC_M4_STARTED 0x01 -#define IMX_SIP_SRC_M4_STOP 0x02 +#define IMX_SIP_SRC_MCU_START 0x00 +#define IMX_SIP_SRC_MCU_STARTED 0x01 +#define IMX_SIP_SRC_MCU_STOP 0x02 #endif From 8d84a8f48702861b6bb99944c34cab76e0dd1cf3 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:19 +0800 Subject: [PATCH 076/109] imx: bootaux: Fix bootaux issue when running on ARM64 The bootaux uses ulong to read private data and write to M4 TCM, this cause problem on ARM64 platform where the ulong is 8bytes. Fix it by using u32 to replace ulong. Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx_bootaux.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 2b97aae3a23..ab7a41fd11d 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -45,7 +45,7 @@ static const struct rproc_att *get_host_mapping(unsigned long auxcore) * is valid, returns the entry point address. * Translates load addresses in the elf file to the U-Boot address space. */ -static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack) +static u32 load_elf_image_m_core_phdr(unsigned long addr, u32 *stack) { Elf32_Ehdr *ehdr; /* ELF header structure pointer */ Elf32_Phdr *phdr; /* Program header structure pointer */ @@ -95,7 +95,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack int arch_auxiliary_core_up(u32 core_id, ulong addr) { - ulong stack, pc; + u32 stack, pc; if (!addr) return -EINVAL; @@ -121,7 +121,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) pc = *(u32 *)(addr + 4); } - printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", + printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc); /* Set the stack and pc to MCU bootROM */ From e8cd1f60d9642d6e5bf346749481dcd1986d4fc2 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:20 +0800 Subject: [PATCH 077/109] imx: imx8: bootaux: Add i.MX8 M4 boot support 1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download M4 image to any DDR address first. Then use the "bootaux [M4 core id]" to boot CM4_0 or CM4_1, the default core id is 0 for CM4_0. Since current M4 only supports running in TCM. The bootaux will copy the M4 image from DDR to its TCML. 2. Implment bootaux for HIFI on QXP command: bootaux 0x81000000 1 Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/Makefile | 5 + arch/arm/mach-imx/imx8/cpu.c | 174 ++++++++++++++++++++++ arch/arm/mach-imx/imx_bootaux.c | 15 +- 5 files changed, 192 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 85d9ca60b14..31ae179b211 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -236,6 +236,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, u64 *phys_sdram_2_start, u64 *phys_sdram_2_size); +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data); int arch_auxiliary_core_check_up(u32 core_id); int board_mmc_get_env_dev(int devno); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 2cca89d4bb1..d94b5828d0d 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -31,7 +31,7 @@ config IMX_RDC config IMX_BOOTAUX bool "Support boot auxiliary core" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M + depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8 || ARCH_IMX8M help bootaux [addr] to boot auxiliary core. diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 00d6ad85c56..aebfa6517bd 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -66,6 +66,11 @@ ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o endif +ifeq ($(SOC),$(filter $(SOC),imx8)) +ifneq ($(CONFIG_SPL_BUILD),y) +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o +endif +endif ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 2b34077438f..c62357044e0 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -107,6 +109,178 @@ int arch_misc_init(void) } #endif +#ifdef CONFIG_IMX_BOOTAUX + +#ifdef CONFIG_IMX8QM +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + sc_rsrc_t core_rsrc, mu_rsrc; + sc_faddr_t tcml_addr; + u32 tcml_size = SZ_128K; + ulong addr; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + tcml_addr = 0x34FE0000; + mu_rsrc = SC_R_M4_0_MU_1A; + break; + case 1: + core_rsrc = SC_R_M4_1_PID0; + tcml_addr = 0x38FE0000; + mu_rsrc = SC_R_M4_1_MU_1A; + break; + default: + printf("Not support this core boot up, ID:%u\n", core_id); + return -EINVAL; + } + + addr = (sc_faddr_t)boot_private_data; + + if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) { + printf("Wrong image address 0x%lx, should not in TCML\n", + addr); + return -EINVAL; + } + + printf("Power on M4 and MU\n"); + + if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); + + if (addr != tcml_addr) + memcpy((void *)tcml_addr, (void *)addr, tcml_size); + + printf("Start M4 %u\n", core_id); + if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE) + return -EIO; + + printf("bootaux complete\n"); + return 0; +} +#endif + +#ifdef CONFIG_IMX8QXP +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + sc_rsrc_t core_rsrc, mu_rsrc = SC_R_NONE; + sc_faddr_t aux_core_ram; + u32 size; + ulong addr; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + aux_core_ram = 0x34FE0000; + mu_rsrc = SC_R_M4_0_MU_1A; + size = SZ_128K; + break; + case 1: + core_rsrc = SC_R_DSP; + aux_core_ram = 0x596f8000; + size = SZ_2K; + break; + default: + printf("Not support this core boot up, ID:%u\n", core_id); + return -EINVAL; + } + + addr = (sc_faddr_t)boot_private_data; + + if (addr >= aux_core_ram && addr <= aux_core_ram + size) { + printf("Wrong image address 0x%lx, should not in aux core ram\n", + addr); + return -EINVAL; + } + + printf("Power on aux core %d\n", core_id); + + if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (mu_rsrc != SC_R_NONE) { + if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + } + + if (core_id == 1) { + struct power_domain pd; + + if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { + printf("Error enable clock\n"); + return -EIO; + } + + if (!power_domain_lookup_name("audio_sai0", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on SAI0\n"); + return -EIO; + } + } + + if (!power_domain_lookup_name("audio_ocram", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on HIFI RAM\n"); + return -EIO; + } + } + } + + printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram); + if (core_id == 0) { + /* M4 use bin file */ + memcpy((void *)aux_core_ram, (void *)addr, size); + } else { + /* HIFI use elf file */ + if (!valid_elf_image(addr)) + return -1; + addr = load_elf_image_shdr(addr); + } + + printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); + + if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) + return -EIO; + + printf("bootaux complete\n"); + return 0; +} +#endif + +int arch_auxiliary_core_check_up(u32 core_id) +{ + sc_rsrc_t core_rsrc; + sc_pm_power_mode_t power_mode; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + break; +#ifdef CONFIG_IMX8QM + case 1: + core_rsrc = SC_R_M4_1_PID0; + break; +#endif + default: + printf("Not support this core, ID:%u\n", core_id); + return 0; + } + + if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE) + return 0; + + if (power_mode != SC_PM_PW_MODE_OFF) + return 1; + + return 0; +} +#endif + int print_bootinfo(void) { enum boot_device bt_dev = get_boot_device(); diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index ab7a41fd11d..f7b14ca38d9 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -14,6 +14,7 @@ #include #include +#ifndef CONFIG_IMX8 /* Just to avoid build error */ #if IS_ENABLED(CONFIG_IMX8M) #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) @@ -158,7 +159,7 @@ int arch_auxiliary_core_check_up(u32 core_id) return 1; } - +#endif /* * To i.MX6SX and i.MX7D, the image supported by bootaux needs * the reset vector at the head for the image, with SP and PC @@ -177,11 +178,15 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, { ulong addr; int ret, up; + u32 core = 0; if (argc < 2) return CMD_RET_USAGE; - up = arch_auxiliary_core_check_up(0); + if (argc > 2) + core = simple_strtoul(argv[2], NULL, 10); + + up = arch_auxiliary_core_check_up(core); if (up) { printf("## Auxiliary core is already up\n"); return CMD_RET_SUCCESS; @@ -192,7 +197,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, if (!addr) return CMD_RET_FAILURE; - ret = arch_auxiliary_core_up(0, addr); + ret = arch_auxiliary_core_up(core, addr); if (ret) return CMD_RET_FAILURE; @@ -202,5 +207,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD( bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux, "Start auxiliary core", - "" + "
[]\n" + " - start auxiliary core [] (default 0),\n" + " at address
\n" ); From dc2d49209ea43a9b253bcf1f0dfcff6ea3d72405 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:21 +0800 Subject: [PATCH 078/109] imx: imx8m: clock: not configure reserved SRC register i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 31c34b6031f..986870799d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = &ana_pll->dram_pll_gnrl_ctl; break; From 6e81ca220e03b241ad7a3f5ddf4cba666b4f7446 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Thu, 15 Jun 2023 18:09:22 +0800 Subject: [PATCH 079/109] imx: parse-container: Use malloc for container processing If the container has image which conflicts with spl_get_load_buffer address, there are processing failures. Use malloc instead of spl_get_load_buffer. Reviewed-by: Ye Li Signed-off-by: Nitin Garg Signed-off-by: Peng Fan --- arch/arm/mach-imx/parse-container.c | 38 ++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index a0d1eb3831c..c5b3abc4f29 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -134,21 +135,27 @@ static int read_auth_container(struct spl_image_info *spl_image, * It will not override the ATF code, so safe to use it here, * no need malloc */ - container = (struct container_hdr *)spl_get_load_buffer(-size, size); + container = malloc(size); + if (!container) + return -ENOMEM; debug("%s: container: %p sector: %lu sectors: %u\n", __func__, container, sector, sectors); - if (info->read(info, sector, sectors, container) != sectors) - return -EIO; + if (info->read(info, sector, sectors, container) != sectors) { + ret = -EIO; + goto end; + } if (container->tag != 0x87 && container->version != 0x0) { - printf("Wrong container header\n"); - return -ENOENT; + printf("Wrong container header"); + ret = -ENOENT; + goto end; } if (!container->num_images) { - printf("Wrong container, no image found\n"); - return -ENOENT; + printf("Wrong container, no image found"); + ret = -ENOENT; + goto end; } length = container->length_lsb + (container->length_msb << 8); @@ -158,13 +165,18 @@ static int read_auth_container(struct spl_image_info *spl_image, size = roundup(length, info->bl_len); sectors = size / info->bl_len; - container = (struct container_hdr *)spl_get_load_buffer(-size, size); + free(container); + container = malloc(size); + if (!container) + return -ENOMEM; debug("%s: container: %p sector: %lu sectors: %u\n", __func__, container, sector, sectors); if (info->read(info, sector, sectors, container) != - sectors) - return -EIO; + sectors) { + ret = -EIO; + goto end; + } } #ifdef CONFIG_AHAB_BOOT @@ -175,7 +187,7 @@ static int read_auth_container(struct spl_image_info *spl_image, SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); if (ret) { printf("authenticate container hdr failed, return %d\n", ret); - return ret; + goto end_auth; } #endif @@ -200,6 +212,10 @@ end_auth: if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) printf("Error: release container failed!\n"); #endif + +end: + free(container); + return ret; } From 00ce4153fbd01aa78b734d87f16772480c42166e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 15 Jun 2023 18:09:23 +0800 Subject: [PATCH 080/109] imx: ahab: Update AHAB for iMX8 and iMX8ULP Abstract common interfaces for AHAB authentication operations. Then share some common codes for AHAB and SPL container authentication Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/ahab.h | 15 ++++ arch/arm/mach-imx/imx8/ahab.c | 129 +++++++++++++++++---------- arch/arm/mach-imx/imx8ulp/Makefile | 1 - arch/arm/mach-imx/parse-container.c | 81 ++--------------- 4 files changed, 103 insertions(+), 123 deletions(-) create mode 100644 arch/arm/include/asm/mach-imx/ahab.h diff --git a/arch/arm/include/asm/mach-imx/ahab.h b/arch/arm/include/asm/mach-imx/ahab.h new file mode 100644 index 00000000000..4222e3db278 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/ahab.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX_AHAB_H__ +#define __IMX_AHAB_H__ + +#include + +int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length); +int ahab_auth_release(void); +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index); + +#endif diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 86b0e0b755f..c878743feeb 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -16,6 +16,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +26,84 @@ DECLARE_GLOBAL_DATA_PTR; #define SECO_PT 2U +int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +{ + int err; + + memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container, + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, + SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); + if (err) + printf("Authenticate container hdr failed, return %d\n", err); + + return err; +} + +int ahab_auth_release(void) +{ + int err; + + err = sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0); + if (err) + printf("Error: release container failed!\n"); + + return err; +} + +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) +{ + sc_faddr_t start, end; + sc_rm_mr_t mr; + int err; + int ret = 0; + + debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n", + image_index, img->dst, img->offset, img->size); + + /* Find the memreg and set permission for seco pt */ + err = sc_rm_find_memreg(-1, &mr, + img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1); + + if (err) { + printf("Error: can't find memreg for image load address 0x%llx, error %d\n", + img->dst, err); + return -ENOMEM; + } + + err = sc_rm_get_memreg_info(-1, mr, &start, &end); + if (!err) + debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); + + err = sc_rm_set_memreg_permissions(-1, mr, + SECO_PT, SC_RM_PERM_FULL); + if (err) { + printf("Set permission failed for img %d, error %d\n", + image_index, err); + return -EPERM; + } + + err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, + 1 << image_index); + if (err) { + printf("Authenticate img %d failed, return %d\n", + image_index, err); + ret = -EIO; + } + + err = sc_rm_set_memreg_permissions(-1, mr, + SECO_PT, SC_RM_PERM_NONE); + if (err) { + printf("Remove permission failed for img %d, error %d\n", + image_index, err); + ret = -EPERM; + } + + return ret; +} + static inline bool check_in_dram(ulong addr) { int i; @@ -46,8 +125,6 @@ int authenticate_os_container(ulong addr) struct container_hdr *phdr; int i, ret = 0; int err; - sc_rm_mr_t mr; - sc_faddr_t start, end; u16 length; struct boot_img_t *img; unsigned long s, e; @@ -76,14 +153,9 @@ int authenticate_os_container(ulong addr) length = phdr->length_lsb + (phdr->length_msb << 8); debug("container length %u\n", length); - memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr, - ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); - err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, - SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); + err = ahab_auth_cntr_hdr(phdr, length); if (err) { - printf("Authenticate container hdr failed, return %d\n", - err); ret = -EIO; goto exit; } @@ -105,50 +177,13 @@ int authenticate_os_container(ulong addr) flush_dcache_range(s, e); - /* Find the memreg and set permission for seco pt */ - err = sc_rm_find_memreg(-1, &mr, s, e); - if (err) { - printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err); - ret = -ENOMEM; - goto exit; - } - - err = sc_rm_get_memreg_info(-1, mr, &start, &end); - if (!err) - debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); - - err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, - SC_RM_PERM_FULL); - if (err) { - printf("Set permission failed for img %d, error %d\n", - i, err); - ret = -EPERM; - goto exit; - } - - err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, - (1 << i)); - if (err) { - printf("Authenticate img %d failed, return %d\n", - i, err); - ret = -EIO; - } - - err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, - SC_RM_PERM_NONE); - if (err) { - printf("Remove permission failed for img %d, err %d\n", - i, err); - ret = -EPERM; - } - + ret = ahab_verify_cntr_image(img, i); if (ret) goto exit; } exit: - if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) - printf("Error: release container failed!\n"); + ahab_auth_release(); return ret; } diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index f7692cf3a78..2c9938fcdf0 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,7 +5,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o -obj-$(CONFIG_AHAB_BOOT) += ahab.o ifeq ($(CONFIG_SPL_BUILD),y) obj-y += upower/ diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index c5b3abc4f29..e2a9e2b2732 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2021 NXP */ #include @@ -10,67 +10,7 @@ #include #include #ifdef CONFIG_AHAB_BOOT -#include -#endif - -#define SEC_SECURE_RAM_BASE 0x31800000UL -#define SEC_SECURE_RAM_END_BASE (SEC_SECURE_RAM_BASE + 0xFFFFUL) -#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE 0x60000000UL - -#define SECO_PT 2U - -#ifdef CONFIG_AHAB_BOOT -static int authenticate_image(struct boot_img_t *img, int image_index) -{ - sc_faddr_t start, end; - sc_rm_mr_t mr; - int err; - int ret = 0; - - debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n", - image_index, (uint32_t)img->dst, img->offset, img->size); - - /* Find the memreg and set permission for seco pt */ - err = sc_rm_find_memreg(-1, &mr, - img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), - ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1); - - if (err) { - printf("can't find memreg for image %d load address 0x%llx, error %d\n", - image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err); - return -ENOMEM; - } - - err = sc_rm_get_memreg_info(-1, mr, &start, &end); - if (!err) - debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); - - err = sc_rm_set_memreg_permissions(-1, mr, - SECO_PT, SC_RM_PERM_FULL); - if (err) { - printf("set permission failed for img %d, error %d\n", - image_index, err); - return -EPERM; - } - - err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, - 1 << image_index); - if (err) { - printf("authenticate img %d failed, return %d\n", - image_index, err); - ret = -EIO; - } - - err = sc_rm_set_memreg_permissions(-1, mr, - SECO_PT, SC_RM_PERM_NONE); - if (err) { - printf("remove permission failed for img %d, error %d\n", - image_index, err); - ret = -EPERM; - } - - return ret; -} +#include #endif static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, @@ -111,10 +51,8 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, } #ifdef CONFIG_AHAB_BOOT - if (authenticate_image(&images[image_index], image_index)) { - printf("Failed to authenticate image %d\n", image_index); + if (ahab_verify_cntr_image(&images[image_index], image_index)) return NULL; - } #endif return &images[image_index]; @@ -180,15 +118,9 @@ static int read_auth_container(struct spl_image_info *spl_image, } #ifdef CONFIG_AHAB_BOOT - memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container, - ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); - - ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, - SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); - if (ret) { - printf("authenticate container hdr failed, return %d\n", ret); + ret = ahab_auth_cntr_hdr(container, length); + if (ret) goto end_auth; - } #endif for (i = 0; i < container->num_images; i++) { @@ -209,8 +141,7 @@ static int read_auth_container(struct spl_image_info *spl_image, end_auth: #ifdef CONFIG_AHAB_BOOT - if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) - printf("Error: release container failed!\n"); + ahab_auth_release(); #endif end: From d7b5fba9a5450bb3d76f70b85d633619253bc622 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Thu, 15 Jun 2023 18:09:24 +0800 Subject: [PATCH 081/109] imx: imx8: ahab: sha256: enable image verification using ARMv8 crypto extension add support for SHA-256 secure hash algorithm using the ARM v8 SHA-256 instructions for verifying image hash. Signed-off-by: Gaurav Jain Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/ahab.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index c878743feeb..b58b14ca9b4 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2022 NXP */ #include @@ -16,6 +16,7 @@ #include #include #include +#include "u-boot/sha256.h" #include DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x60000000UL) #define SECO_PT 2U +#define AHAB_HASH_TYPE_MASK 0x00000700 +#define AHAB_HASH_TYPE_SHA256 0 int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { @@ -128,6 +131,9 @@ int authenticate_os_container(ulong addr) u16 length; struct boot_img_t *img; unsigned long s, e; +#ifdef CONFIG_ARMV8_CE_SHA256 + u8 hash_value[SHA256_SUM_LEN]; +#endif if (addr % 4) { puts("Error: Image's address is not 4 byte aligned\n"); @@ -177,9 +183,23 @@ int authenticate_os_container(ulong addr) flush_dcache_range(s, e); - ret = ahab_verify_cntr_image(img, i); - if (ret) - goto exit; +#ifdef CONFIG_ARMV8_CE_SHA256 + if (((img->hab_flags & AHAB_HASH_TYPE_MASK) >> 8) == AHAB_HASH_TYPE_SHA256) { + sha256_csum_wd((void *)img->dst, img->size, hash_value, CHUNKSZ_SHA256); + err = memcmp(&img->hash, &hash_value, SHA256_SUM_LEN); + if (err) { + printf("img %d hash comparison failed, error %d\n", i, err); + ret = -EIO; + goto exit; + } + } else { +#endif + ret = ahab_verify_cntr_image(img, i); + if (ret) + goto exit; +#ifdef CONFIG_ARMV8_CE_SHA256 + } +#endif } exit: From 14d7eedf77ba034ce329009fc1b8a5221ce61eb8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Jun 2023 18:09:25 +0800 Subject: [PATCH 082/109] imx: imx8m: add CAAM_BASE_ADDR Add CAAM_BASE_ADDR which will be used by priblob.c Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 8632eddb530..f1b7526ac77 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -40,6 +40,7 @@ #define UART1_BASE_ADDR 0x30860000 #define UART3_BASE_ADDR 0x30880000 #define UART2_BASE_ADDR 0x30890000 +#define CAAM_BASE_ADDR 0x30900000 #define I2C1_BASE_ADDR 0x30A20000 #define I2C2_BASE_ADDR 0x30A30000 #define I2C3_BASE_ADDR 0x30A40000 From 2159f7d9b6f191e74c3d2004867e138bb5a0533c Mon Sep 17 00:00:00 2001 From: Maximus Sun Date: Thu, 15 Jun 2023 18:09:26 +0800 Subject: [PATCH 083/109] imx: priblob: Update to use structure Use structure to avoid define CAAM_SCFGR for each platform Signed-off-by: Maximus Sun Signed-off-by: Peng Fan --- arch/arm/mach-imx/priblob.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c index 9b92eae7818..5b022d5c820 100644 --- a/arch/arm/mach-imx/priblob.c +++ b/arch/arm/mach-imx/priblob.c @@ -13,12 +13,16 @@ #include #include #include -#include "../drivers/crypto/fsl_caam_internal.h" +#include int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { - writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR); - printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3); + ccsr_sec_t *sec_regs = (ccsr_sec_t *)CAAM_BASE_ADDR; + u32 scfgr = sec_in32(&sec_regs->scfgr); + + scfgr |= 0x3; + sec_out32(&sec_regs->scfgr, scfgr); + printf("New priblob setting = 0x%x\n", sec_in32(&sec_regs->scfgr) & 0x3); return 0; } From 77b5ad0ea3d132412f21daaa997b6249266ff71c Mon Sep 17 00:00:00 2001 From: Utkarsh Gupta Date: Thu, 15 Jun 2023 18:09:27 +0800 Subject: [PATCH 084/109] imx: fsl_sec: preprocessor casting issue with addresses involving math The sec_in32 preprocessor is defined as follows in include/fsl_sec.h file: When address "a" is calculated using math for ex: addition of base address and an offset, then casting is applied only to the first address which in this example is base address. caam_ccbvid_reg = sec_in32(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET) resolves to: caam_ccbvid_reg = in_le32((ulong *)(ulong)CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET) instead it should resolve to: caam_ccbvid_reg = in_le32((ulong *)(ulong)(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET)) Thus add parenthesis around the address "a" so that however the address is calculated, the casting is applied to the final calculated address. Reviewed-by: Horia Geanta Reviewed-by: Ye Li Signed-off-by: Utkarsh Gupta Signed-off-by: Peng Fan --- include/fsl_sec.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/fsl_sec.h b/include/fsl_sec.h index d8861d1d0b7..9dad1d1ec47 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -13,8 +13,8 @@ #include #ifdef CONFIG_SYS_FSL_SEC_LE -#define sec_in32(a) in_le32((ulong *)(ulong)a) -#define sec_out32(a, v) out_le32((ulong *)(ulong)a, v) +#define sec_in32(a) in_le32((ulong *)(ulong)(a)) +#define sec_out32(a, v) out_le32((ulong *)(ulong)(a), v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32 From ff1dd520243320259b654065821b0f5cdea9f551 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 15 Jun 2023 08:21:08 -0700 Subject: [PATCH 085/109] mx8m: csf.sh: use vars for keys to avoid file edits when signing The csf_spl.txt and csf_fit.txt templates contain file paths which must be edited for the location of your NXP CST generated key files. Streamline the process of signing an image by assigning unique var names to these which can be expended from env variables in the csf.sh script. The following vars are used: SRK_TABLE - full path to SRK_1_2_3_4_table.bin CSF_KEY - full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem IMG_KEY - full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem Additionally provide an example of running the csf.sh script. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan --- doc/imx/habv4/csf_examples/mx8m/csf.sh | 21 +++++++++++++++++++ doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 12 +++++------ doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 12 +++++------ doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 10 +++++++++ 4 files changed, 43 insertions(+), 12 deletions(-) diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh index 5b383fa982f..d87015f6c4e 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -22,6 +22,27 @@ cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp +# update File Paths from env vars +if ! [ -r $CSF_KEY ]; then + echo "Error: \$CSF_KEY not found" + exit 1 +fi +if ! [ -r $IMG_KEY ]; then + echo "Error: \$IMG_KEY not found" + exit 1 +fi +if ! [ -r $SRK_TABLE ]; then + echo "Error: \$SRK_TABLE not found" + exit 1 +fi +sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp +sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp +sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp +sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp +sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp +sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp + +# update SPL Blocks spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) ) spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin)) sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.tmp diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt index bbb82f69448..3d79edf2813 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt @@ -7,21 +7,21 @@ Signature Format = CMS [Install SRK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin" + # SRK_TABLE is full path to SRK_1_2_3_4_table.bin + File = "$SRK_TABLE" Source index = 0 [Install CSFK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$CSF_KEY" [Authenticate CSF] [Install Key] Verification index = 0 Target Index = 2 - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$IMG_KEY" [Authenticate Data] Verification index = 2 diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt index 00e34f6b1b9..88fa420a5fa 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt @@ -7,13 +7,13 @@ Signature Format = CMS [Install SRK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin" + # SRK_TABLE is full path to SRK_1_2_3_4_table.bin + File = "$SRK_TABLE" Source index = 0 [Install CSFK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$CSF_KEY" [Authenticate CSF] @@ -24,8 +24,8 @@ [Install Key] Verification index = 0 Target Index = 2 - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$IMG_KEY" [Authenticate Data] Verification index = 2 diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt index e79726bf2c5..e16e5410bd9 100644 --- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt +++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt @@ -207,6 +207,16 @@ dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc ``` The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh +and can be used as follows to modify flash.bin to be signed +(adjust paths as needed): +``` +export CST_DIR=/usr/src/cst-3.3.1/ +export CSF_KEY=$CST_DIR/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem +export IMG_KEY=$CST_DIR/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem +export SRK_TABLE=$CST_DIR/crts/SRK_1_2_3_4_table.bin +export PATH=$CST_DIR/linux64/bin:$PATH +/bin/sh doc/imx/habv4/csf_examples/mx8m/csf.sh +``` 1.4 Closing the device ----------------------- From 7a478c836a243d1682b50dd82576432fc6e11825 Mon Sep 17 00:00:00 2001 From: Cem Tenruh Date: Fri, 16 Jun 2023 10:28:13 +0200 Subject: [PATCH 086/109] board: phytec: phycore_imx8mm: Update lpddr4_timing Update RAM Timings for 2GB RAM based on DDR Controller Configuration Spreadsheet revision 22. Including the update of the refresh rate to workaround errata ERR050805. Signed-off-by: Cem Tenruh --- board/phytec/phycore_imx8mm/lpddr4_timing.c | 1486 +++++++++---------- 1 file changed, 742 insertions(+), 744 deletions(-) diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.c b/board/phytec/phycore_imx8mm/lpddr4_timing.c index 811ac26415a..f5a2f3268b3 100644 --- a/board/phytec/phycore_imx8mm/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mm/lpddr4_timing.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Copyright 2019 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH * * Generated code from MX8M_DDR_tool */ @@ -13,22 +14,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400304, 0x1}, {0x3d400030, 0x1}, {0x3d400000, 0xa1080020}, - {0x3d400020, 0x223}, + {0x3d400020, 0x222}, {0x3d400024, 0x3a980}, - {0x3d400064, 0x5b00d2}, + {0x3d400064, 0x2d00d2}, {0x3d4000d0, 0xc00305ba}, {0x3d4000d4, 0x940000}, {0x3d4000dc, 0xd4002d}, {0x3d4000e0, 0x310000}, {0x3d4000e8, 0x66004d}, {0x3d4000ec, 0x16004d}, - {0x3d400100, 0x191e1920}, + {0x3d400100, 0x191e0c20}, {0x3d400104, 0x60630}, {0x3d40010c, 0xb0b000}, {0x3d400110, 0xe04080e}, {0x3d400114, 0x2040c0c}, {0x3d400118, 0x1010007}, - {0x3d40011c, 0x401}, + {0x3d40011c, 0x402}, {0x3d400130, 0x20600}, {0x3d400134, 0xc100002}, {0x3d400138, 0xd8}, @@ -45,7 +46,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d4001b0, 0x11}, {0x3d4001c0, 0x1}, {0x3d4001c4, 0x1}, - {0x3d4000f4, 0xc99}, + {0x3d4000f4, 0x699}, {0x3d400108, 0x70e1617}, {0x3d400200, 0x1f}, {0x3d40020c, 0x0}, @@ -53,6 +54,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400204, 0x80808}, {0x3d400214, 0x7070707}, {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, {0x3d400250, 0x29001701}, {0x3d400254, 0x2c}, {0x3d40025c, 0x4000030}, @@ -64,22 +66,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400498, 0x620096}, {0x3d40049c, 0x1100e07}, {0x3d4004a0, 0xc8012c}, - {0x3d402020, 0x21}, + {0x3d402020, 0x20}, {0x3d402024, 0x7d00}, {0x3d402050, 0x20d040}, - {0x3d402064, 0xc001c}, + {0x3d402064, 0x6001c}, {0x3d4020dc, 0x840000}, {0x3d4020e0, 0x310000}, {0x3d4020e8, 0x66004d}, {0x3d4020ec, 0x16004d}, - {0x3d402100, 0xa040305}, + {0x3d402100, 0xa040105}, {0x3d402104, 0x30407}, {0x3d402108, 0x203060b}, {0x3d40210c, 0x505000}, {0x3d402110, 0x2040202}, {0x3d402114, 0x2030202}, {0x3d402118, 0x1010004}, - {0x3d40211c, 0x301}, + {0x3d40211c, 0x302}, {0x3d402130, 0x20300}, {0x3d402134, 0xa100002}, {0x3d402138, 0x1d}, @@ -88,8 +90,8 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d402190, 0x3818200}, {0x3d402194, 0x80303}, {0x3d4021b4, 0x100}, - {0x3d4020f4, 0xc99}, - {0x3d403020, 0x21}, + {0x3d4020f4, 0x599}, + {0x3d403020, 0x20}, {0x3d403024, 0x1f40}, {0x3d403050, 0x20d040}, {0x3d403064, 0x30007}, @@ -104,7 +106,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403110, 0x2040202}, {0x3d403114, 0x2030202}, {0x3d403118, 0x1010004}, - {0x3d40311c, 0x301}, + {0x3d40311c, 0x302}, {0x3d403130, 0x20300}, {0x3d403134, 0xa100002}, {0x3d403138, 0x8}, @@ -113,7 +115,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403190, 0x3818200}, {0x3d403194, 0x80303}, {0x3d4031b4, 0x100}, - {0x3d4030f4, 0xc99}, + {0x3d4030f4, 0x599}, {0x3d400028, 0x0}, }; @@ -201,8 +203,8 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x220024, 0x1ab}, {0x2003a, 0x0}, {0x20056, 0x3}, - {0x120056, 0xa}, - {0x220056, 0xa}, + {0x120056, 0x3}, + {0x220056, 0x3}, {0x1004d, 0xe00}, {0x1014d, 0xe00}, {0x1104d, 0xe00}, @@ -323,727 +325,726 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { /* ddr phy trained csr */ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, + {0x200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x200cb, 0x0}, + {0x10043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x10143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x11043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x11143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x12043, 0x0}, + {0x112043, 0x0}, + {0x212043, 0x0}, + {0x12143, 0x0}, + {0x112143, 0x0}, + {0x212143, 0x0}, + {0x13043, 0x0}, + {0x113043, 0x0}, + {0x213043, 0x0}, + {0x13143, 0x0}, + {0x113143, 0x0}, + {0x213143, 0x0}, + {0x80, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x1080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x2080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x3080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x4080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x5080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x6080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x7080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x8080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x9080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x10080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x10180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x11080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x11180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x12080, 0x0}, + {0x112080, 0x0}, + {0x212080, 0x0}, + {0x12180, 0x0}, + {0x112180, 0x0}, + {0x212180, 0x0}, + {0x13080, 0x0}, + {0x113080, 0x0}, + {0x213080, 0x0}, + {0x13180, 0x0}, + {0x113180, 0x0}, + {0x213180, 0x0}, + {0x10081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x10181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x11081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x11181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x12081, 0x0}, + {0x112081, 0x0}, + {0x212081, 0x0}, + {0x12181, 0x0}, + {0x112181, 0x0}, + {0x212181, 0x0}, + {0x13081, 0x0}, + {0x113081, 0x0}, + {0x213081, 0x0}, + {0x13181, 0x0}, + {0x113181, 0x0}, + {0x213181, 0x0}, + {0x100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x120d0, 0x0}, + {0x1120d0, 0x0}, + {0x2120d0, 0x0}, + {0x121d0, 0x0}, + {0x1121d0, 0x0}, + {0x2121d0, 0x0}, + {0x130d0, 0x0}, + {0x1130d0, 0x0}, + {0x2130d0, 0x0}, + {0x131d0, 0x0}, + {0x1131d0, 0x0}, + {0x2131d0, 0x0}, + {0x100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x120d1, 0x0}, + {0x1120d1, 0x0}, + {0x2120d1, 0x0}, + {0x121d1, 0x0}, + {0x1121d1, 0x0}, + {0x2121d1, 0x0}, + {0x130d1, 0x0}, + {0x1130d1, 0x0}, + {0x2130d1, 0x0}, + {0x131d1, 0x0}, + {0x1131d1, 0x0}, + {0x2131d1, 0x0}, + {0x10068, 0x0}, + {0x10168, 0x0}, + {0x10268, 0x0}, + {0x10368, 0x0}, + {0x10468, 0x0}, + {0x10568, 0x0}, + {0x10668, 0x0}, + {0x10768, 0x0}, + {0x10868, 0x0}, + {0x11068, 0x0}, + {0x11168, 0x0}, + {0x11268, 0x0}, + {0x11368, 0x0}, + {0x11468, 0x0}, + {0x11568, 0x0}, + {0x11668, 0x0}, + {0x11768, 0x0}, + {0x11868, 0x0}, + {0x12068, 0x0}, + {0x12168, 0x0}, + {0x12268, 0x0}, + {0x12368, 0x0}, + {0x12468, 0x0}, + {0x12568, 0x0}, + {0x12668, 0x0}, + {0x12768, 0x0}, + {0x12868, 0x0}, + {0x13068, 0x0}, + {0x13168, 0x0}, + {0x13268, 0x0}, + {0x13368, 0x0}, + {0x13468, 0x0}, + {0x13568, 0x0}, + {0x13668, 0x0}, + {0x13768, 0x0}, + {0x13868, 0x0}, + {0x10069, 0x0}, + {0x10169, 0x0}, + {0x10269, 0x0}, + {0x10369, 0x0}, + {0x10469, 0x0}, + {0x10569, 0x0}, + {0x10669, 0x0}, + {0x10769, 0x0}, + {0x10869, 0x0}, + {0x11069, 0x0}, + {0x11169, 0x0}, + {0x11269, 0x0}, + {0x11369, 0x0}, + {0x11469, 0x0}, + {0x11569, 0x0}, + {0x11669, 0x0}, + {0x11769, 0x0}, + {0x11869, 0x0}, + {0x12069, 0x0}, + {0x12169, 0x0}, + {0x12269, 0x0}, + {0x12369, 0x0}, + {0x12469, 0x0}, + {0x12569, 0x0}, + {0x12669, 0x0}, + {0x12769, 0x0}, + {0x12869, 0x0}, + {0x13069, 0x0}, + {0x13169, 0x0}, + {0x13269, 0x0}, + {0x13369, 0x0}, + {0x13469, 0x0}, + {0x13569, 0x0}, + {0x13669, 0x0}, + {0x13769, 0x0}, + {0x13869, 0x0}, + {0x1008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x1018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x1108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x1118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x1208c, 0x0}, + {0x11208c, 0x0}, + {0x21208c, 0x0}, + {0x1218c, 0x0}, + {0x11218c, 0x0}, + {0x21218c, 0x0}, + {0x1308c, 0x0}, + {0x11308c, 0x0}, + {0x21308c, 0x0}, + {0x1318c, 0x0}, + {0x11318c, 0x0}, + {0x21318c, 0x0}, + {0x1008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x1018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x1108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x1118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x1208d, 0x0}, + {0x11208d, 0x0}, + {0x21208d, 0x0}, + {0x1218d, 0x0}, + {0x11218d, 0x0}, + {0x21218d, 0x0}, + {0x1308d, 0x0}, + {0x11308d, 0x0}, + {0x21308d, 0x0}, + {0x1318d, 0x0}, + {0x11318d, 0x0}, + {0x21318d, 0x0}, + {0x100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x120c0, 0x0}, + {0x1120c0, 0x0}, + {0x2120c0, 0x0}, + {0x121c0, 0x0}, + {0x1121c0, 0x0}, + {0x2121c0, 0x0}, + {0x122c0, 0x0}, + {0x1122c0, 0x0}, + {0x2122c0, 0x0}, + {0x123c0, 0x0}, + {0x1123c0, 0x0}, + {0x2123c0, 0x0}, + {0x124c0, 0x0}, + {0x1124c0, 0x0}, + {0x2124c0, 0x0}, + {0x125c0, 0x0}, + {0x1125c0, 0x0}, + {0x2125c0, 0x0}, + {0x126c0, 0x0}, + {0x1126c0, 0x0}, + {0x2126c0, 0x0}, + {0x127c0, 0x0}, + {0x1127c0, 0x0}, + {0x2127c0, 0x0}, + {0x128c0, 0x0}, + {0x1128c0, 0x0}, + {0x2128c0, 0x0}, + {0x130c0, 0x0}, + {0x1130c0, 0x0}, + {0x2130c0, 0x0}, + {0x131c0, 0x0}, + {0x1131c0, 0x0}, + {0x2131c0, 0x0}, + {0x132c0, 0x0}, + {0x1132c0, 0x0}, + {0x2132c0, 0x0}, + {0x133c0, 0x0}, + {0x1133c0, 0x0}, + {0x2133c0, 0x0}, + {0x134c0, 0x0}, + {0x1134c0, 0x0}, + {0x2134c0, 0x0}, + {0x135c0, 0x0}, + {0x1135c0, 0x0}, + {0x2135c0, 0x0}, + {0x136c0, 0x0}, + {0x1136c0, 0x0}, + {0x2136c0, 0x0}, + {0x137c0, 0x0}, + {0x1137c0, 0x0}, + {0x2137c0, 0x0}, + {0x138c0, 0x0}, + {0x1138c0, 0x0}, + {0x2138c0, 0x0}, + {0x100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x120c1, 0x0}, + {0x1120c1, 0x0}, + {0x2120c1, 0x0}, + {0x121c1, 0x0}, + {0x1121c1, 0x0}, + {0x2121c1, 0x0}, + {0x122c1, 0x0}, + {0x1122c1, 0x0}, + {0x2122c1, 0x0}, + {0x123c1, 0x0}, + {0x1123c1, 0x0}, + {0x2123c1, 0x0}, + {0x124c1, 0x0}, + {0x1124c1, 0x0}, + {0x2124c1, 0x0}, + {0x125c1, 0x0}, + {0x1125c1, 0x0}, + {0x2125c1, 0x0}, + {0x126c1, 0x0}, + {0x1126c1, 0x0}, + {0x2126c1, 0x0}, + {0x127c1, 0x0}, + {0x1127c1, 0x0}, + {0x2127c1, 0x0}, + {0x128c1, 0x0}, + {0x1128c1, 0x0}, + {0x2128c1, 0x0}, + {0x130c1, 0x0}, + {0x1130c1, 0x0}, + {0x2130c1, 0x0}, + {0x131c1, 0x0}, + {0x1131c1, 0x0}, + {0x2131c1, 0x0}, + {0x132c1, 0x0}, + {0x1132c1, 0x0}, + {0x2132c1, 0x0}, + {0x133c1, 0x0}, + {0x1133c1, 0x0}, + {0x2133c1, 0x0}, + {0x134c1, 0x0}, + {0x1134c1, 0x0}, + {0x2134c1, 0x0}, + {0x135c1, 0x0}, + {0x1135c1, 0x0}, + {0x2135c1, 0x0}, + {0x136c1, 0x0}, + {0x1136c1, 0x0}, + {0x2136c1, 0x0}, + {0x137c1, 0x0}, + {0x1137c1, 0x0}, + {0x2137c1, 0x0}, + {0x138c1, 0x0}, + {0x1138c1, 0x0}, + {0x2138c1, 0x0}, + {0x10020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x11020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x12020, 0x0}, + {0x112020, 0x0}, + {0x212020, 0x0}, + {0x13020, 0x0}, + {0x113020, 0x0}, + {0x213020, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x20074, 0x0}, + {0x100aa, 0x0}, + {0x110aa, 0x0}, + {0x120aa, 0x0}, + {0x130aa, 0x0}, + {0x20010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x20011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x120ae, 0x0}, + {0x1120ae, 0x0}, + {0x2120ae, 0x0}, + {0x120af, 0x0}, + {0x1120af, 0x0}, + {0x2120af, 0x0}, + {0x130ae, 0x0}, + {0x1130ae, 0x0}, + {0x2130ae, 0x0}, + {0x130af, 0x0}, + {0x1130af, 0x0}, + {0x2130af, 0x0}, + {0x20020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x120a0, 0x0}, + {0x120a1, 0x0}, + {0x120a2, 0x0}, + {0x120a3, 0x0}, + {0x120a4, 0x0}, + {0x120a5, 0x0}, + {0x120a6, 0x0}, + {0x120a7, 0x0}, + {0x130a0, 0x0}, + {0x130a1, 0x0}, + {0x130a2, 0x0}, + {0x130a3, 0x0}, + {0x130a4, 0x0}, + {0x130a5, 0x0}, + {0x130a6, 0x0}, + {0x130a7, 0x0}, + {0x2007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x2007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x400fd, 0x0}, + {0x400c0, 0x0}, + {0x90201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x90202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x90203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x90205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x90206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x90207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x90208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x10062, 0x0}, + {0x10162, 0x0}, + {0x10262, 0x0}, + {0x10362, 0x0}, + {0x10462, 0x0}, + {0x10562, 0x0}, + {0x10662, 0x0}, + {0x10762, 0x0}, + {0x10862, 0x0}, + {0x11062, 0x0}, + {0x11162, 0x0}, + {0x11262, 0x0}, + {0x11362, 0x0}, + {0x11462, 0x0}, + {0x11562, 0x0}, + {0x11662, 0x0}, + {0x11762, 0x0}, + {0x11862, 0x0}, + {0x12062, 0x0}, + {0x12162, 0x0}, + {0x12262, 0x0}, + {0x12362, 0x0}, + {0x12462, 0x0}, + {0x12562, 0x0}, + {0x12662, 0x0}, + {0x12762, 0x0}, + {0x12862, 0x0}, + {0x13062, 0x0}, + {0x13162, 0x0}, + {0x13262, 0x0}, + {0x13362, 0x0}, + {0x13462, 0x0}, + {0x13562, 0x0}, + {0x13662, 0x0}, + {0x13762, 0x0}, + {0x13862, 0x0}, + {0x20077, 0x0}, + {0x10001, 0x0}, + {0x11001, 0x0}, + {0x12001, 0x0}, + {0x13001, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x10030, 0x0}, + {0x10130, 0x0}, + {0x10230, 0x0}, + {0x10330, 0x0}, + {0x10430, 0x0}, + {0x10530, 0x0}, + {0x10630, 0x0}, + {0x10730, 0x0}, + {0x10830, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + {0x11030, 0x0}, + {0x11130, 0x0}, + {0x11230, 0x0}, + {0x11330, 0x0}, + {0x11430, 0x0}, + {0x11530, 0x0}, + {0x11630, 0x0}, + {0x11730, 0x0}, + {0x11830, 0x0}, + {0x12040, 0x0}, + {0x12140, 0x0}, + {0x12240, 0x0}, + {0x12340, 0x0}, + {0x12440, 0x0}, + {0x12540, 0x0}, + {0x12640, 0x0}, + {0x12740, 0x0}, + {0x12840, 0x0}, + {0x12030, 0x0}, + {0x12130, 0x0}, + {0x12230, 0x0}, + {0x12330, 0x0}, + {0x12430, 0x0}, + {0x12530, 0x0}, + {0x12630, 0x0}, + {0x12730, 0x0}, + {0x12830, 0x0}, + {0x13040, 0x0}, + {0x13140, 0x0}, + {0x13240, 0x0}, + {0x13340, 0x0}, + {0x13440, 0x0}, + {0x13540, 0x0}, + {0x13640, 0x0}, + {0x13740, 0x0}, + {0x13840, 0x0}, + {0x13030, 0x0}, + {0x13130, 0x0}, + {0x13230, 0x0}, + {0x13330, 0x0}, + {0x13430, 0x0}, + {0x13530, 0x0}, + {0x13630, 0x0}, + {0x13730, 0x0}, + {0x13830, 0x0}, }; - /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg[] = { {0xd0000, 0x0}, @@ -1054,7 +1055,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { {0x54008, 0x131f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x2dd4}, {0x5401a, 0x31}, @@ -1094,7 +1094,6 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1134,7 +1133,6 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1200,7 +1198,7 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { {0x5403b, 0x4d}, {0x5403c, 0x4d}, {0x5403d, 0x1600}, - { 0xd0000, 0x1 }, + {0xd0000, 0x1}, }; /* DRAM PHY init engine image */ @@ -1693,15 +1691,15 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x400d6, 0x20a}, {0x400d7, 0x20b}, {0x2003a, 0x2}, - {0x2000b, 0x5d}, + {0x2000b, 0x34b}, {0x2000c, 0xbb}, {0x2000d, 0x753}, {0x2000e, 0x2c}, - {0x12000b, 0xc}, + {0x12000b, 0x70}, {0x12000c, 0x19}, {0x12000d, 0xfa}, {0x12000e, 0x10}, - {0x22000b, 0x3}, + {0x22000b, 0x1c}, {0x22000c, 0x6}, {0x22000d, 0x3e}, {0x22000e, 0x10}, @@ -1842,5 +1840,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 3000, 400, 100,}, }; From 3d634b0b4460919ecc6ad236786ba9fcacdbe3d0 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 23 Jun 2023 09:44:17 -0700 Subject: [PATCH 087/109] board: gateworks: venice: switch to 2-bank dram config Switch to a 2-bank dram config to properly support 4GiB. Signed-off-by: Tim Harvey Reviewed-by: Peng Fan --- board/gateworks/venice/venice.c | 2 +- include/configs/imx8mm_venice.h | 9 +++++---- include/configs/imx8mn_venice.h | 9 +++++---- include/configs/imx8mp_venice.h | 9 +++++---- 4 files changed, 16 insertions(+), 13 deletions(-) diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 3067480e6ac..a39ae58c8a0 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -20,7 +20,7 @@ int board_phys_sdram_size(phys_size_t *size) if (!size) return -EINVAL; - *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + *size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE); return 0; } diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index b33b8283085..046d5685d04 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -31,10 +31,11 @@ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 #define CFG_SYS_INIT_RAM_SIZE SZ_2M +/* SDRAM configuration: 4GiB */ #define CFG_SYS_SDRAM_BASE 0x40000000 - -/* SDRAM configuration */ -#define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_4G +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2 0xC0000000 +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 3db997e9e7f..1cc054a82ba 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -25,10 +25,11 @@ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 #define CFG_SYS_INIT_RAM_SIZE SZ_2M +/* SDRAM configuration: 4GiB */ #define CFG_SYS_SDRAM_BASE 0x40000000 - -/* SDRAM configuration */ -#define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_4G +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2 0xC0000000 +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index b5ee8c98fbb..47413ecd7fb 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -25,10 +25,11 @@ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 #define CFG_SYS_INIT_RAM_SIZE SZ_2M +/* SDRAM configuration: 4GiB */ #define CFG_SYS_SDRAM_BASE 0x40000000 - -/* SDRAM configuration */ -#define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_4G +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2 0xC0000000 +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif From c8645e74113c62e724f1f091acff28f8dccb18c8 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 23 Jun 2023 09:44:59 -0700 Subject: [PATCH 088/109] configs: imx8m: Prepare imx8m-venice boards for HAB support In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. This also needs to occur in the SPL so enable CONFIG_SPL_BOARD_INIT and add a void spl_board_init function which calls arch_misc_init to probe the CAAM driver. Signed-off-by: Tim Harvey Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 9 +++++++++ board/gateworks/venice/spl.c | 5 +++++ configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 5 files changed, 17 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 67db3e46ecd..3d62d7052e7 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -124,6 +124,9 @@ config TARGET_IMX8MM_VENICE select IMX8M_LPDDR4 select GATEWORKS_SC select MISC + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" @@ -175,6 +178,9 @@ config TARGET_IMX8MN_VENICE select IMX8M_LPDDR4 select GATEWORKS_SC select MISC + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MP_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Plus" @@ -232,6 +238,9 @@ config TARGET_IMX8MP_VENICE select IMX8M_LPDDR4 select GATEWORKS_SC select MISC + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 606738a8c97..5aa209578b2 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -373,3 +373,8 @@ const char *spl_board_loader_name(u32 boot_device) return NULL; } } + +void spl_board_init(void) +{ + arch_misc_init(); +} diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index e533a40f24a..a485910a529 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -36,6 +36,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index c066f6d8ba0..39f930ae2ca 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x950000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SYS_SPL_MALLOC=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index ee4b84db191..294206ba8b2 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x98fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SYS_SPL_MALLOC=y From cb5fe9e33697962e4821acc040d0fe9e5eea6712 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 2 Jul 2023 03:03:51 +0200 Subject: [PATCH 089/109] ARM: imx: romapi: Fix signed integer bitwise ops misuse Bitwise operations on signed integers are not defined, replace them with per-call checks. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam Reviewed-by: Heiko Schocher --- arch/arm/mach-imx/spl_imx_romapi.c | 32 ++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 9164045115f..4af41699678 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -76,13 +76,16 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, u32 image_offset; ret = rom_api_query_boot_infor(QUERY_IVT_OFF, &offset); - ret |= rom_api_query_boot_infor(QUERY_PAGE_SZ, &pagesize); - ret |= rom_api_query_boot_infor(QUERY_IMG_OFF, &image_offset); + if (ret != ROM_API_OKAY) + goto err; - if (ret != ROM_API_OKAY) { - puts("ROMAPI: Failure query boot infor pagesize/offset\n"); - return -1; - } + ret = rom_api_query_boot_infor(QUERY_PAGE_SZ, &pagesize); + if (ret != ROM_API_OKAY) + goto err; + + ret = rom_api_query_boot_infor(QUERY_IMG_OFF, &image_offset); + if (ret != ROM_API_OKAY) + goto err; header = (struct legacy_img_hdr *)(CONFIG_SPL_IMX_ROMAPI_LOADADDR); @@ -124,6 +127,10 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, } return 0; + +err: + puts("ROMAPI: Failure query boot infor pagesize/offset\n"); + return -1; } static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector, @@ -344,12 +351,12 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, u32 boot, bstage; ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot); - ret |= rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage); + if (ret != ROM_API_OKAY) + goto err; - if (ret != ROM_API_OKAY) { - puts("ROMAPI: failure at query_boot_info\n"); - return -1; - } + ret = rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage); + if (ret != ROM_API_OKAY) + goto err; printf("Boot Stage: "); @@ -374,4 +381,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, return spl_romapi_load_image_stream(spl_image, bootdev); return spl_romapi_load_image_seekable(spl_image, bootdev, boot); +err: + puts("ROMAPI: failure at query_boot_info\n"); + return -1; } From 1ac30d1301fa7681dd400c21fb5cc41470c85d0a Mon Sep 17 00:00:00 2001 From: Luca Ellero Date: Wed, 5 Jul 2023 14:56:16 +0200 Subject: [PATCH 090/109] dm: adc: add iMX93 ADC support This commit adds driver for iMX93 ADC. The driver is implemented using driver model and provides ADC uclass's methods for ADC single channel operations: - adc_start_channel() - adc_channel_data() - adc_stop() ADC features: - channels: 4 - resolution: 12-bit Signed-off-by: Luca Ellero Reviewed-by: Haibo Chen --- drivers/adc/Kconfig | 8 ++ drivers/adc/Makefile | 1 + drivers/adc/imx93-adc.c | 290 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 drivers/adc/imx93-adc.c diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index e719c38bb31..4336732dee5 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -63,3 +63,11 @@ config STM32_ADC - core driver to deal with common resources - child driver to deal with individual ADC resources (declare ADC device and associated channels, start/stop conversions) + +config ADC_IMX93 + bool "Enable NXP IMX93 ADC driver" + help + This enables basic driver for NXP IMX93 ADC. + It provides: + - 4 analog input channels + - 12-bit resolution diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index c1387f3a346..5336c820973 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_ADC_SANDBOX) += sandbox.o obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o obj-$(CONFIG_SARADC_MESON) += meson-saradc.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o +obj-$(CONFIG_ADC_IMX93) += imx93-adc.o diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c new file mode 100644 index 00000000000..41d04e0426c --- /dev/null +++ b/drivers/adc/imx93-adc.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 ASEM Srl + * Author: Luca Ellero + * + * Originally based on NXP linux-imx kernel v5.15 drivers/iio/adc/imx93_adc.c + */ + +#include +#include +#include +#include +#include +#include +#include + +#define IMX93_ADC_MCR 0x00 +#define IMX93_ADC_MSR 0x04 +#define IMX93_ADC_ISR 0x10 +#define IMX93_ADC_IMR 0x20 +#define IMX93_ADC_CIMR0 0x24 +#define IMX93_ADC_CTR0 0x94 +#define IMX93_ADC_NCMR0 0xA4 +#define IMX93_ADC_PCDR0 0x100 +#define IMX93_ADC_PCDR1 0x104 +#define IMX93_ADC_PCDR2 0x108 +#define IMX93_ADC_PCDR3 0x10c +#define IMX93_ADC_PCDR4 0x110 +#define IMX93_ADC_PCDR5 0x114 +#define IMX93_ADC_PCDR6 0x118 +#define IMX93_ADC_PCDR7 0x11c +#define IMX93_ADC_CALSTAT 0x39C + +#define IMX93_ADC_MCR_MODE_MASK BIT(29) +#define IMX93_ADC_MCR_NSTART_MASK BIT(24) +#define IMX93_ADC_MCR_CALSTART_MASK BIT(14) +#define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8) +#define IMX93_ADC_MCR_PWDN_MASK BIT(0) + +#define IMX93_ADC_MSR_CALFAIL_MASK BIT(30) +#define IMX93_ADC_MSR_CALBUSY_MASK BIT(29) +#define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0) + +#define IMX93_ADC_ISR_EOC_MASK BIT(1) + +#define IMX93_ADC_IMR_EOC_MASK BIT(1) +#define IMX93_ADC_IMR_ECH_MASK BIT(0) + +#define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0) + +#define IDLE 0 +#define POWER_DOWN 1 +#define WAIT_STATE 2 +#define BUSY_IN_CALIBRATION 3 +#define SAMPLE 4 +#define CONVERSION 6 + +#define IMX93_ADC_MAX_CHANNEL 3 +#define IMX93_ADC_DAT_MASK 0xfff +#define IMX93_ADC_TIMEOUT 100000 + +struct imx93_adc_priv { + int active_channel; + void __iomem *regs; + struct clk ipg_clk; +}; + +static void imx93_adc_power_down(struct imx93_adc_priv *adc) +{ + u32 mcr, msr; + int ret; + + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr, + ((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) == POWER_DOWN), 50); + if (ret == -ETIMEDOUT) + pr_warn("ADC not in power down mode, current MSR: %x\n", msr); +} + +static void imx93_adc_power_up(struct imx93_adc_priv *adc) +{ + u32 mcr; + + /* bring ADC out of power down state, in idle state */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); +} + +static void imx93_adc_config_ad_clk(struct imx93_adc_priv *adc) +{ + u32 mcr; + + /* put adc in power down mode */ + imx93_adc_power_down(adc); + + /* config the AD_CLK equal to bus clock */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + /* bring ADC out of power down state, in idle state */ + imx93_adc_power_up(adc); +} + +static int imx93_adc_calibration(struct imx93_adc_priv *adc) +{ + u32 mcr, msr; + int ret; + + /* make sure ADC is in power down mode */ + imx93_adc_power_down(adc); + + /* config SAR controller operating clock */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + /* bring ADC out of power down state */ + imx93_adc_power_up(adc); + + /* + * we use the default TSAMP/NRSMPL/AVGEN in MCR, + * can add the setting of these bit if need + */ + + /* run calibration */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + /* wait calibration to be finished */ + ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr, + !(msr & IMX93_ADC_MSR_CALBUSY_MASK), 2000000); + if (ret == -ETIMEDOUT) { + pr_warn("ADC calibration timeout\n"); + return ret; + } + + /* check whether calbration is successful or not */ + msr = readl(adc->regs + IMX93_ADC_MSR); + if (msr & IMX93_ADC_MSR_CALFAIL_MASK) { + pr_warn("ADC calibration failed!\n"); + return -EAGAIN; + } + + return 0; +} + +static int imx93_adc_channel_data(struct udevice *dev, int channel, + unsigned int *data) +{ + struct imx93_adc_priv *adc = dev_get_priv(dev); + u32 isr, pcda; + int ret; + + if (channel != adc->active_channel) { + pr_err("Requested channel is not active!\n"); + return -EINVAL; + } + + ret = readl_poll_timeout(adc->regs + IMX93_ADC_ISR, isr, + (isr & IMX93_ADC_ISR_EOC_MASK), IMX93_ADC_TIMEOUT); + + /* clear interrupts */ + writel(isr, adc->regs + IMX93_ADC_ISR); + + if (ret == -ETIMEDOUT) { + pr_warn("ADC conversion timeout!\n"); + return ret; + } + + pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel * 4); + + *data = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda); + + return 0; +} + +static int imx93_adc_start_channel(struct udevice *dev, int channel) +{ + struct imx93_adc_priv *adc = dev_get_priv(dev); + u32 imr, mcr; + + /* config channel mask register */ + writel(1 << channel, adc->regs + IMX93_ADC_NCMR0); + + /* config interrupt mask */ + imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1); + writel(imr, adc->regs + IMX93_ADC_IMR); + writel(1 << channel, adc->regs + IMX93_ADC_CIMR0); + + /* config one-shot mode */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + /* start normal conversion */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + adc->active_channel = channel; + + return 0; +} + +static int imx93_adc_stop(struct udevice *dev) +{ + struct imx93_adc_priv *adc = dev_get_priv(dev); + + imx93_adc_power_down(adc); + + adc->active_channel = -1; + + return 0; +} + +static int imx93_adc_probe(struct udevice *dev) +{ + struct imx93_adc_priv *adc = dev_get_priv(dev); + unsigned int ret; + + ret = imx93_adc_calibration(adc); + if (ret < 0) + return ret; + + imx93_adc_config_ad_clk(adc); + + adc->active_channel = -1; + + return 0; +} + +static int imx93_adc_of_to_plat(struct udevice *dev) +{ + struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + struct imx93_adc_priv *adc = dev_get_priv(dev); + unsigned int ret; + + adc->regs = dev_read_addr_ptr(dev); + if (adc->regs == (struct imx93_adc *)FDT_ADDR_T_NONE) { + pr_err("Dev: %s - can't get address!", dev->name); + return -ENODATA; + } + + ret = clk_get_by_name(dev, "ipg", &adc->ipg_clk); + if (ret < 0) { + pr_err("Can't get ADC ipg clk: %d\n", ret); + return ret; + } + ret = clk_enable(&adc->ipg_clk); + if(ret) { + pr_err("Can't enable ADC ipg clk: %d\n", ret); + return ret; + } + + uc_pdata->data_mask = IMX93_ADC_DAT_MASK; + uc_pdata->data_format = ADC_DATA_FORMAT_BIN; + uc_pdata->data_timeout_us = IMX93_ADC_TIMEOUT; + + /* Mask available channel bits: [0:3] */ + uc_pdata->channel_mask = (2 << IMX93_ADC_MAX_CHANNEL) - 1; + + return 0; +} + +static const struct adc_ops imx93_adc_ops = { + .start_channel = imx93_adc_start_channel, + .channel_data = imx93_adc_channel_data, + .stop = imx93_adc_stop, +}; + +static const struct udevice_id imx93_adc_ids[] = { + { .compatible = "nxp,imx93-adc" }, + { } +}; + +U_BOOT_DRIVER(imx93_adc) = { + .name = "imx93-adc", + .id = UCLASS_ADC, + .of_match = imx93_adc_ids, + .ops = &imx93_adc_ops, + .probe = imx93_adc_probe, + .of_to_plat = imx93_adc_of_to_plat, + .priv_auto = sizeof(struct imx93_adc_priv), +}; From e7ff54d963039ab8e5fbf033c8579a25e7d75650 Mon Sep 17 00:00:00 2001 From: Luca Ellero Date: Wed, 5 Jul 2023 14:56:17 +0200 Subject: [PATCH 091/109] imx93_evk: defconfig: add adc support iMX93 ADC features: - 4 channels - 12 bit resolution Signed-off-by: Luca Ellero --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 0de563f790b..65f473885c6 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -81,6 +81,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC_IMX93=y CONFIG_CPU=y CONFIG_CPU_IMX=y CONFIG_IMX_RGPIO2P=y From 48d1fb92a9244d8c9b6687158034c754ef7d7971 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Jul 2023 01:26:10 +0200 Subject: [PATCH 092/109] ARM: dts: imx: Fix eMMC boot on Data Modul i.MX8M Plus eDM SBC In case the i.MX8M Plus starts from eMMC BOOT1/BOOT2 HW partitions, the flash.bin container is stored at offset 0 from the start, that means the fitImage itb is at offset 0x2c0 instead of 0x300 sectors from the start. Handle this difference in custom spl_mmc_get_uboot_raw_sector() . Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Reviewed-by: Jaehoon Chung --- board/data_modul/imx8mp_edm_sbc/spl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index c30185e48d4..2fdd95a730c 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -107,6 +107,20 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[4] = BOOT_DEVICE_NONE; } +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect) +{ + const u32 boot_dev = spl_boot_device(); + int part; + + if (boot_dev == BOOT_DEVICE_MMC2) { /* eMMC */ + part = spl_mmc_emmc_boot_partition(mmc); + if (part == 1 || part == 2) /* eMMC BOOT1/BOOT2 HW partitions */ + return sect - 0x40; + } + + return sect; +} + static struct dram_timing_info *dram_timing_info[8] = { &dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */ NULL, /* 32 Gbit x16 */ From 1b4c3e612549ea97c90301173bd56ff9f6907503 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 25 May 2023 17:02:29 -0400 Subject: [PATCH 093/109] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. The hardware configuration (EC) is determined at runtime by reading from the SOM EEPROM. To support both hardware configurations (EC and non-EC), adjust/fix the PHY reset gpios according to the hardware configuration read at runtime from the SOM EEPROM. This adjustement is done in U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees. Signed-off-by: Hugo Villeneuve --- arch/arm/dts/imx8mn-var-som-symphony.dts | 4 - .../variscite/imx8mn_var_som/imx8mn_var_som.c | 80 +++++++++++++++++++ configs/imx8mn_var_som_defconfig | 2 + 3 files changed, 82 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts index 3ed7021a487..5c8e4e81752 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony.dts +++ b/arch/arm/dts/imx8mn-var-som-symphony.dts @@ -56,10 +56,6 @@ }; }; -ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; -}; - &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index a89457e8f57..61b9455a8f4 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -14,6 +14,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -161,4 +162,83 @@ int checkboard(void) #endif /* CONFIG_DISPLAY_BOARDINFO */ +static int insert_gpios_prop(void *blob, int node, const char *prop, + unsigned int phandle, u32 gpio, u32 flags) +{ + fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio), + cpu_to_fdt32(flags) }; + return fdt_setprop(blob, node, prop, &val, sizeof(val)); +} + +static int configure_phy_reset_gpios(void *blob) +{ + int node; + int phynode; + int ret; + u32 handle; + u32 gpio; + u32 flags; + char path[1024]; + const char *eth_alias = "ethernet0"; + + snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4", + fdt_get_alias(blob, eth_alias)); + + phynode = fdt_path_offset(blob, path); + if (phynode < 0) { + pr_err("%s(): unable to locate PHY node: %s\n", __func__, path); + return 0; + } + + if (gd_board_type() & VAR_EEPROM_F_ETH) { + snprintf(path, sizeof(path), "%s", + fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */ + gpio = 9; + flags = GPIO_ACTIVE_LOW; + } else { + snprintf(path, sizeof(path), "%s/gpio@20", + fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */ + gpio = 5; + flags = GPIO_ACTIVE_HIGH; + } + + node = fdt_path_offset(blob, path); + if (node < 0) { + pr_err("%s(): unable to locate GPIO node: %s\n", __func__, + path); + return 0; + } + + handle = fdt_get_phandle(blob, node); + if (handle < 0) { + pr_err("%s(): unable to locate GPIO controller handle: %s\n", + __func__, path); + } + + ret = insert_gpios_prop(blob, phynode, "reset-gpios", + handle, gpio, flags); + if (ret < 0) { + pr_err("%s(): failed to set reset-gpios property\n", __func__); + return ret; + } + + return 0; +} + +#if defined(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *blob) +{ + /* Fix U-Boot device tree: */ + return configure_phy_reset_gpios(blob); +} +#endif /* CONFIG_OF_BOARD_FIXUP */ + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Fix kernel device tree: */ + return configure_phy_reset_gpios(blob); +} +#endif /* CONFIG_OF_BOARD_SETUP */ + #endif /* CONFIG_SPL_BUILD */ diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index e54c20e1531..b346b14ebdd 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -23,9 +23,11 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_OF_BOARD_FIXUP=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" From 8d916e5c15451756b0b8d4542f4586eed416d40e Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 3 Apr 2023 13:14:26 +0200 Subject: [PATCH 094/109] board: colibri-imx8x: initialize snvs Initialize Secure Non-Volatile Storage, aka SNVS. Signed-off-by: Andrejs Cainikovs --- board/toradex/colibri-imx8x/colibri-imx8x.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index f504385aec9..6c0b09787c8 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -139,6 +140,13 @@ int board_init(void) { board_gpio_init(); + if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } + return 0; } From d90d6074e8f2dcb1db08dff1a63a0c2c80eda4e6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 30 May 2023 17:45:57 -0500 Subject: [PATCH 095/109] clk: imx8mp: Update clocks based on kernel 6.4-RC4 There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Tested-by: Tim Harvey #imx8mp-venice-gw74xx --- drivers/clk/imx/clk-imx8mp.c | 3 ++- include/dt-bindings/clock/imx8mp-clock.h | 14 ++++++++++++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 09bef596f22..a21a3ce34bb 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,7 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde8..3f28ce685f4 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319 - -#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 From 451799a6ceac3139e88aa0762ffdc5284ce75333 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 30 May 2023 17:45:58 -0500 Subject: [PATCH 096/109] arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4 Several changes have been made to the device tree in the kernel, so update that as well as the corresponding imx8mp-u-boot.dtsi files to prevent breaking the booting. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mp-u-boot.dtsi | 3 + arch/arm/dts/imx8mp.dtsi | 502 ++++++++++++++++++++++++-------- 2 files changed, 386 insertions(+), 119 deletions(-) diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 68cd0e10f02..36e7444a627 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,9 @@ &aips3 { bootph-pre-ram; + spba-bus@30800000 { + bootph-pre-ram; + }; }; &iomuxc { diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a..428c60462e3 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; @@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; }; @@ -406,12 +409,36 @@ status = "disabled"; }; + gpt1: timer@302d0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@302e0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; + clock-names = "ipg", "per"; + }; + + gpt3: timer@302f0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; + clock-names = "ipg", "per"; + }; + iomuxc: pinctrl@30330000 { compatible = "fsl,imx8mp-iomuxc"; reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { + gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -424,27 +451,44 @@ #address-cells = <1>; #size-cells = <1>; - imx8mp_uid: unique-id@420 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x8 0x8> describes fuses 0x420 and + * 0x430). + */ + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - eth_mac1: mac-address@90 { + eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; - eth_mac2: mac-address@96 { + eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; + + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ + reg = <0x264 0x10>; + }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -523,6 +567,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>; + interrupts = ; interrupt-controller; #interrupt-cells = <3>; @@ -589,7 +634,7 @@ reg = ; }; - pgc_hsiomix: power-domains@17 { + pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = ; clocks = <&clk IMX8MP_CLK_HSIO_AXI>, @@ -631,6 +676,14 @@ reg = ; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; + + pgc_mlmix: power-domain@24 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; }; }; }; @@ -693,6 +746,30 @@ clocks = <&osc_24m>; clock-names = "per"; }; + + gpt6: timer@306e0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x306e0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; + clock-names = "ipg", "per"; + }; + + gpt5: timer@306f0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x306f0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; + clock-names = "ipg", "per"; + }; + + gpt4: timer@30700000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x30700000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; + clock-names = "ipg", "per"; + }; }; aips3: bus@30800000 { @@ -702,112 +779,129 @@ #size-cells = <1>; ranges; - ecspi1: spi@30820000 { + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30800000 0x100000>; #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, - <&clk IMX8MP_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + ranges; - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, - <&clk IMX8MP_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, - <&clk IMX8MP_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_UART1_ROOT>, - <&clk IMX8MP_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_UART3_ROOT>, - <&clk IMX8MP_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_UART2_ROOT>, - <&clk IMX8MP_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - flexcan1: can@308c0000 { - compatible = "fsl,imx8mp-flexcan"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN1_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 4>; - status = "disabled"; - }; + uart2: serial@30890000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - flexcan2: can@308d0000 { - compatible = "fsl,imx8mp-flexcan"; - reg = <0x308d0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN2_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 5>; - status = "disabled"; + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 5>; + status = "disabled"; + }; }; crypto: crypto@30900000 { @@ -1063,11 +1157,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-200M { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; }; - opp-1000M { + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; }; @@ -1080,10 +1174,78 @@ #size-cells = <1>; ranges; + mipi_dsi: dsi@32e60000 { + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x400>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <200000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif1: endpoint { + remote-endpoint = <&lcdif1_to_dsim>; + }; + }; + }; + }; + + lcdif1: display-controller@32e80000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; + status = "disabled"; + + port { + lcdif1_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif1>; + }; + }; + }; + + lcdif2: display-controller@32e90000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e90000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; + status = "disabled"; + + port { + lcdif2_to_ldb: endpoint { + remote-endpoint = <&ldb_from_lcdif2>; + }; + }; + }; + media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; reg = <0x32ec0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>, @@ -1122,12 +1284,55 @@ "disp1", "disp2", "isp", "phy"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>; + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <500000000>, <200000000>; - + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <500000000>, <200000000>, + <0>, <0>, <1039500000>; #power-domain-cells = <1>; + + lvds_bridge: bridge@5c { + compatible = "fsl,imx8mp-ldb"; + reg = <0x5c 0x4>, <0x128 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif2: endpoint { + remote-endpoint = <&lcdif2_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ldb_lvds_ch1: endpoint { + }; + }; + }; + }; }; pcie_phy: pcie-phy@32f00000 { @@ -1158,6 +1363,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>; + #clock-cells = <0>; }; }; @@ -1165,6 +1371,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1192,6 +1405,32 @@ status = "disabled"; }; + pcie_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names = "dbi", "addr_space"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; @@ -1223,6 +1462,28 @@ power-domains = <&pgc_gpu2d>; }; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; + }; + vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1234,6 +1495,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; @@ -1279,7 +1543,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = ; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; @@ -1292,9 +1556,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = ; phys = <&usb3_phy0>, <&usb3_phy0>; @@ -1321,7 +1585,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = ; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; @@ -1334,9 +1598,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = ; phys = <&usb3_phy1>, <&usb3_phy1>; From 788ff422e55f954e90552a9eda1d49ffa788e9c2 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 30 May 2023 17:49:34 -0500 Subject: [PATCH 097/109] arm: dts: imx8mp-beacon-kit: Enable USB Power domains The USB Power domains should not have been removed as it causes the board to hang if the USB is started. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi index 5ca631e9d8c..b56f3a2bd2e 100644 --- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi @@ -185,12 +185,10 @@ &usb3_0 { dma-ranges = <0x40000000 0x40000000 0xc0000000>; - /delete-property/ power-domains; }; &usb3_1 { dma-ranges = <0x40000000 0x40000000 0xc0000000>; - /delete-property/ power-domains; }; &usb_dwc3_0 { From cd9a3e3f90ee2e62a9067a570007b7331eda7b97 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 11 Jul 2023 11:09:14 +0200 Subject: [PATCH 098/109] verdin-imx8mm/verdin-imx8mp: synchronise device trees with linux Synchronise device trees with linux v6.5-rc1. Signed-off-by: Marcel Ziswiler --- arch/arm/dts/imx8mm-mx8menlo.dts | 17 +-- arch/arm/dts/imx8mm-verdin-dahlia.dtsi | 150 ------------------------ arch/arm/dts/imx8mm-verdin-dev.dtsi | 97 ++++++++++++++- arch/arm/dts/imx8mm-verdin.dtsi | 30 ++--- arch/arm/dts/imx8mp-verdin-dahlia.dtsi | 129 -------------------- arch/arm/dts/imx8mp-verdin-dev.dtsi | 125 +++++++++++++++++++- arch/arm/dts/imx8mp-verdin-wifi.dtsi | 5 + arch/arm/dts/imx8mp-verdin.dtsi | 91 +++++++++----- board/toradex/verdin-imx8mm/MAINTAINERS | 1 - board/toradex/verdin-imx8mp/MAINTAINERS | 1 - 10 files changed, 309 insertions(+), 337 deletions(-) delete mode 100644 arch/arm/dts/imx8mm-verdin-dahlia.dtsi delete mode 100644 arch/arm/dts/imx8mp-verdin-dahlia.dtsi diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts index 32f6f2f50c1..0b123a84018 100644 --- a/arch/arm/dts/imx8mm-mx8menlo.dts +++ b/arch/arm/dts/imx8mm-mx8menlo.dts @@ -10,6 +10,7 @@ / { model = "MENLO MX8MM EMBEDDED DEVICE"; compatible = "menlo,mx8menlo", + "toradex,verdin-imx8mm-nonwifi", "toradex,verdin-imx8mm", "fsl,imx8mm"; @@ -250,21 +251,21 @@ /* SODIMM 96 */ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* CPLD_D[7] */ - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x184 /* CPLD_D[6] */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x184 /* CPLD_D[5] */ - MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x184 /* CPLD_D[4] */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x184 /* CPLD_D[3] */ - MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x184 /* CPLD_D[2] */ - MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x184 /* CPLD_D[1] */ - MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x184 /* CPLD_D[0] */ - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x184 /* KBD_intK */ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4 /* DISP_reset */ diff --git a/arch/arm/dts/imx8mm-verdin-dahlia.dtsi b/arch/arm/dts/imx8mm-verdin-dahlia.dtsi deleted file mode 100644 index c2a5c2f7b20..00000000000 --- a/arch/arm/dts/imx8mm-verdin-dahlia.dtsi +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - sound_card: sound-card { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,name = "imx8mm-wm8904"; - simple-audio-card,routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Headphone Jack", "MICBIAS", - "IN1L", "Headphone Jack"; - simple-audio-card,widgets = - "Microphone", "Headphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - - dailink_master: simple-audio-card,codec { - clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; - sound-dai = <&wm8904_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - }; -}; - -/* Verdin SPI_1 */ -&ecspi2 { - status = "okay"; -}; - -/* EEPROM on display adapter boards */ -&eeprom_display_adapter { - status = "okay"; -}; - -/* EEPROM on Verdin Development board */ -&eeprom_carrier_board { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - status = "okay"; -}; - -/* Current measurement into module VCC */ -&hwmon { - status = "okay"; -}; - -&hwmon_temp { - vs-supply = <®_1p8v>; - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -/* Verdin I2C_1 */ -&i2c4 { - status = "okay"; - - /* Audio Codec */ - wm8904_1a: audio-codec@1a { - compatible = "wlf,wm8904"; - AVDD-supply = <®_3p3v>; - clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; - clock-names = "mclk"; - CPVDD-supply = <®_3p3v>; - DBVDD-supply = <®_3p3v>; - DCVDD-supply = <®_3p3v>; - MICVDD-supply = <®_3p3v>; - reg = <0x1a>; - #sound-dai-cells = <0>; - }; -}; - -/* Verdin PCIE_1 */ -&pcie0 { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&pwm1 { - status = "okay"; -}; - -/* Verdin PWM_1 */ -&pwm2 { - status = "okay"; -}; - -/* Verdin PWM_2 */ -&pwm3 { - status = "okay"; -}; - -/* Verdin I2S_1 */ -&sai2 { - status = "okay"; -}; - -/* Verdin UART_3 */ -&uart1 { - status = "okay"; -}; - -/* Verdin UART_1 */ -&uart2 { - status = "okay"; -}; - -/* Verdin UART_2 */ -&uart3 { - status = "okay"; -}; - -/* Verdin USB_1 */ -&usbotg1 { - status = "okay"; -}; - -/* Verdin USB_2 */ -&usbotg2 { - status = "okay"; -}; - -/* Verdin SD_1 */ -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-verdin-dev.dtsi b/arch/arm/dts/imx8mm-verdin-dev.dtsi index 73cc3fafa01..3c4b8ca125e 100644 --- a/arch/arm/dts/imx8mm-verdin-dev.dtsi +++ b/arch/arm/dts/imx8mm-verdin-dev.dtsi @@ -3,14 +3,13 @@ * Copyright 2022 Toradex */ -#include "imx8mm-verdin-dahlia.dtsi" - / { sound_card: sound-card { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,name = "imx8mm-nau8822"; simple-audio-card,routing = "Headphones", "LHP", @@ -41,27 +40,121 @@ }; }; +/* Verdin SPI_1 */ +&ecspi2 { + status = "okay"; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&hwmon_temp { + vs-supply = <®_1p8v>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + &gpio_expander_21 { status = "okay"; }; /* Verdin I2C_1 */ &i2c4 { + status = "okay"; + /* Audio Codec */ nau8822_1a: audio-codec@1a { compatible = "nuvoton,nau8822"; reg = <0x1a>; + #sound-dai-cells = <0>; }; }; +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + /* Verdin UART_1, connector X50 through RS485 transceiver */ &uart2 { linux,rs485-enabled-at-boot-time; rs485-rts-active-low; rs485-rx-during-tx; + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + disable-over-current; + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + disable-over-current; + status = "okay"; }; /* Limit frequency on dev board due to long traces and bad signal integrity */ &usdhc2 { max-frequency = <100000000>; + status = "okay"; }; diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi index bcab830c6e9..6f081158714 100644 --- a/arch/arm/dts/imx8mm-verdin.dtsi +++ b/arch/arm/dts/imx8mm-verdin.dtsi @@ -3,8 +3,8 @@ * Copyright 2022 Toradex */ -#include "dt-bindings/phy/phy-imx8-pcie.h" -#include "dt-bindings/pwm/pwm.h" +#include +#include #include "imx8mm.dtsi" / { @@ -56,7 +56,11 @@ hdmi_connector: hdmi-connector { compatible = "hdmi-connector"; ddc-i2c-bus = <&i2c2>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; label = "hdmi"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; type = "a"; status = "disabled"; }; @@ -95,9 +99,10 @@ compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ - off-on-delay = <500000>; + off-on-delay-us = <500000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_eth>; + regulator-always-on; regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; @@ -134,7 +139,7 @@ enable-active-high; /* Verdin SD_1_PWR_EN (SODIMM 76) */ gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - off-on-delay = <100000>; + off-on-delay-us = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; regulator-max-microvolt = <3300000>; @@ -183,15 +188,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -358,7 +363,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; reg = <0x25>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC @@ -598,7 +602,7 @@ hdmi_lontium_lt8912: hdmi@48 { compatible = "lontium,lt8912b"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; reg = <0x48>; /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ /* Verdin GPIO_10_DSI (SODIMM 21) */ @@ -610,7 +614,7 @@ compatible = "atmel,maxtouch"; /* * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) */ interrupt-parent = <&gpio3>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; @@ -653,9 +657,6 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; assigned-clock-rates = <10000000>, <250000000>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; /* PCIE_1_RESET# (SODIMM 244) */ @@ -664,6 +665,7 @@ &pcie_phy { clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "ref"; fsl,clkreq-unsupported; fsl,refclk-pad-mode = ; fsl,tx-deemph-gen1 = <0x2d>; @@ -739,7 +741,6 @@ adp-disable; dr_mode = "otg"; hnp-disable; - over-current-active-low; samsung,picophy-dc-vol-level-adjust = <7>; samsung,picophy-pre-emp-curr-control = <3>; srp-disable; @@ -749,7 +750,6 @@ /* Verdin USB_2 */ &usbotg2 { dr_mode = "host"; - over-current-active-low; samsung,picophy-dc-vol-level-adjust = <7>; samsung,picophy-pre-emp-curr-control = <3>; vbus-supply = <®_usb_otg2_vbus>; diff --git a/arch/arm/dts/imx8mp-verdin-dahlia.dtsi b/arch/arm/dts/imx8mp-verdin-dahlia.dtsi deleted file mode 100644 index 4b8f86f6308..00000000000 --- a/arch/arm/dts/imx8mp-verdin-dahlia.dtsi +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/* TODO: Audio Codec */ - -&backlight { - power-supply = <®_3p3v>; -}; - -/* Verdin SPI_1 */ -&ecspi1 { - status = "okay"; -}; - -/* EEPROM on display adapter boards */ -&eeprom_display_adapter { - status = "okay"; -}; - -/* EEPROM on Verdin Development board */ -&eeprom_carrier_board { - status = "okay"; -}; - -&eqos { - status = "okay"; -}; - -&flexcan1 { - status = "okay"; -}; - -&flexcan2 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - status = "okay"; -}; - -/* Current measurement into module VCC */ -&hwmon { - status = "okay"; -}; - -&hwmon_temp { - vs-supply = <®_1p8v>; - status = "okay"; -}; - -/* Verdin I2C_2_DSI */ -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -/* Verdin I2C_1 */ -&i2c4 { - status = "okay"; - - /* TODO: Audio Codec */ -}; - -/* TODO: Verdin PCIE_1 */ - -/* Verdin PWM_1 */ -&pwm1 { - status = "okay"; -}; - -/* Verdin PWM_2 */ -&pwm2 { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&pwm3 { - status = "okay"; -}; - -®_usdhc2_vmmc { - vin-supply = <®_3p3v>; -}; - -/* TODO: Verdin I2S_1 */ - -/* Verdin UART_1 */ -&uart1 { - status = "okay"; -}; - -/* Verdin UART_2 */ -&uart2 { - status = "okay"; -}; - -/* Verdin UART_3, used as the Linux Console */ -&uart3 { - status = "okay"; -}; - -/* Verdin USB_1 */ -&usb3_0 { - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -/* Verdin USB_2 */ -&usb3_1 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -/* Verdin SD_1 */ -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mp-verdin-dev.dtsi b/arch/arm/dts/imx8mp-verdin-dev.dtsi index cefabe65b25..bdfdd4c782f 100644 --- a/arch/arm/dts/imx8mp-verdin-dev.dtsi +++ b/arch/arm/dts/imx8mp-verdin-dev.dtsi @@ -3,8 +3,6 @@ * Copyright 2022 Toradex */ -#include "imx8mp-verdin-dahlia.dtsi" - / { /* TODO: Audio Codec */ @@ -12,7 +10,7 @@ compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */ - off-on-delay = <500000>; + off-on-delay-us = <500000>; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "+V3.3_ETH"; @@ -21,16 +19,106 @@ }; }; +&backlight { + power-supply = <®_3p3v>; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + status = "okay"; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&eqos { + status = "okay"; +}; + &fec { phy-supply = <®_eth2phy>; status = "okay"; }; +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + &gpio_expander_21 { status = "okay"; vcc-supply = <®_1p8v>; }; +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&hwmon_temp { + vs-supply = <®_1p8v>; + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; + + /* TODO: Audio Codec */ +}; + +/* Verdin PCIE_1 */ +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm3 { + status = "okay"; +}; + +®_usdhc2_vmmc { + vin-supply = <®_3p3v>; +}; + /* TODO: Verdin I2C_1 with Audio Codec */ /* Verdin UART_1, connector X50 through RS485 transceiver */ @@ -38,9 +126,40 @@ linux,rs485-enabled-at-boot-time; rs485-rts-active-low; rs485-rx-during-tx; + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux Console */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3_1 { + fsl,permanently-attached; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; }; /* Limit frequency on dev board due to long traces and bad signal integrity */ &usdhc2 { max-frequency = <100000000>; + status = "okay"; }; diff --git a/arch/arm/dts/imx8mp-verdin-wifi.dtsi b/arch/arm/dts/imx8mp-verdin-wifi.dtsi index 36289c175e6..ef94f9a57e2 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi.dtsi @@ -65,6 +65,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt_uart>; status = "okay"; + + bluetooth { + compatible = "mrvl,88w8997"; + max-speed = <921600>; + }; }; /* On-module Wi-Fi */ diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi index 7b712d1888e..e9e4fcb562f 100644 --- a/arch/arm/dts/imx8mp-verdin.dtsi +++ b/arch/arm/dts/imx8mp-verdin.dtsi @@ -3,7 +3,8 @@ * Copyright 2022 Toradex */ -#include "dt-bindings/pwm/pwm.h" +#include +#include #include "imx8mp.dtsi" / { @@ -49,7 +50,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - button-wakeup { + key-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; @@ -86,7 +87,7 @@ compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ - off-on-delay = <500000>; + off-on-delay-us = <500000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_eth>; regulator-always-on; @@ -127,7 +128,7 @@ enable-active-high; /* Verdin SD_1_PWR_EN (SODIMM 76) */ gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; - off-on-delay = <100000>; + off-on-delay-us = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; regulator-max-microvolt = <3300000>; @@ -354,16 +355,6 @@ "SODIMM_82", "SODIMM_70", "SODIMM_72"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <29 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; }; &gpio3 { @@ -432,6 +423,16 @@ "SODIMM_256", "SODIMM_48", "SODIMM_44"; + + ctrl-sleep-moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + }; }; /* On-module I2C */ @@ -452,7 +453,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; reg = <0x25>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the @@ -678,8 +678,8 @@ status = "disabled"; }; - lvds_ti_sn65dsi83: bridge@2c { - compatible = "ti,sn65dsi83"; + lvds_ti_sn65dsi84: bridge@2c { + compatible = "ti,sn65dsi84"; /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ /* Verdin GPIO_10_DSI (SODIMM 21) */ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; @@ -712,7 +712,7 @@ compatible = "atmel,maxtouch"; /* * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) */ interrupt-parent = <&gpio4>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; @@ -748,7 +748,20 @@ }; }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; +}; /* Verdin PWM_1 */ &pwm1 { @@ -806,28 +819,45 @@ }; /* Verdin USB_1 */ -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; +&usb3_0 { + fsl,disable-port-power-control; + fsl,over-current-active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_oc_n>; }; &usb_dwc3_0 { + /* dual role only, not full featured OTG */ adp-disable; dr_mode = "otg"; hnp-disable; maximum-speed = "high-speed"; - over-current-active-low; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_id>; + role-switch-default-mode = "peripheral"; srp-disable; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_id>; + self-powered; + type = "micro"; + vbus-supply = <®_usb1_vbus>; + }; }; /* Verdin USB_2 */ +&usb3_1 { + fsl,disable-port-power-control; +}; + &usb3_phy1 { vbus-supply = <®_usb2_vbus>; }; &usb_dwc3_1 { - disable-over-current; dr_mode = "host"; }; @@ -1045,7 +1075,6 @@ pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = - , /* SODIMM 157 */ /* CSI_1_MCLK */ ; /* SODIMM 91 */ }; @@ -1220,7 +1249,7 @@ pinctrl_usb1_vbus: usb1vbusgrp { fsl,pins = - ; /* SODIMM 155 */ + ; /* SODIMM 155 */ }; /* USB_1_ID */ @@ -1229,9 +1258,15 @@ ; /* SODIMM 161 */ }; + /* USB_1_OC# */ + pinctrl_usb_1_oc_n: usb1ocngrp { + fsl,pins = + ; /* SODIMM 157 */ + }; + pinctrl_usb2_vbus: usb2vbusgrp { fsl,pins = - ; /* SODIMM 185 */ + ; /* SODIMM 185 */ }; /* On-module Wi-Fi */ diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS index 974b3a10329..b0f4329253a 100644 --- a/board/toradex/verdin-imx8mm/MAINTAINERS +++ b/board/toradex/verdin-imx8mm/MAINTAINERS @@ -3,7 +3,6 @@ M: Marcel Ziswiler W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini S: Maintained F: arch/arm/dts/imx8mm-verdin.dtsi -F: arch/arm/dts/imx8mm-verdin-dahlia.dtsi F: arch/arm/dts/imx8mm-verdin-dev.dtsi F: arch/arm/dts/imx8mm-verdin-wifi.dtsi F: arch/arm/dts/imx8mm-verdin-wifi-dev.dts diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS index cff3c503838..ea04a83926a 100644 --- a/board/toradex/verdin-imx8mp/MAINTAINERS +++ b/board/toradex/verdin-imx8mp/MAINTAINERS @@ -1,6 +1,5 @@ Verdin iMX8M Plus F: arch/arm/dts/imx8mp-verdin.dtsi -F: arch/arm/dts/imx8mp-verdin-dahlia.dtsi F: arch/arm/dts/imx8mp-verdin-dev.dtsi F: arch/arm/dts/imx8mp-verdin-wifi.dtsi F: arch/arm/dts/imx8mp-verdin-wifi-dev.dts From 5e161626f93219432ebfc85dec18a1a2337d1a73 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Tue, 11 Jul 2023 11:09:15 +0200 Subject: [PATCH 099/109] configs: verdin-imx8mm: enable spl_gpio_hog Enable CONFIG_SPL_GPIO_HOG option to be able to control GPIO hogs from SPL. Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler --- configs/verdin-imx8mm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 0eb18915154..09e14c6f8c4 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -98,6 +98,7 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y From cf77093e3126f5980df526c08f80c2ccc91687c0 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Tue, 11 Jul 2023 11:09:16 +0200 Subject: [PATCH 100/109] arm64: dts: verdin-imx8mm: add ctrl_sleep_moci# hog Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal may be used to control some power-rails on the carrier board, therefore it should be set to high when the module is booting. To do this as early as possible is generally a good idea and the issue was noticed on the Yavia carrier board where it is needed to power the I2C EEPROM on the carrier board. Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler --- arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi index 494229e4e62..2b268f55cb9 100644 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi @@ -56,6 +56,10 @@ &gpio5 { bootph-pre-ram; + + ctrl-sleep-moci-hog { + bootph-pre-ram; + }; }; &i2c1 { @@ -88,6 +92,10 @@ }; }; +&pinctrl_ctrl_sleep_moci { + bootph-pre-ram; +}; + &pinctrl_i2c1 { bootph-pre-ram; }; From ce2cf345f78048a3c8cb9d7e98343a1c189a7c19 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Tue, 11 Jul 2023 11:09:17 +0200 Subject: [PATCH 101/109] configs: verdin-imx8mp: enable spl_gpio_hog Enable CONFIG_SPL_GPIO_HOG option to be able to control GPIO hogs from SPL. Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler --- configs/verdin-imx8mp_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index faf57fd473e..2df0f4f3443 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -109,6 +109,7 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_FSL_CAAM=y CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y From 214a986f132d749532fa15835498e1a6b723e191 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Tue, 11 Jul 2023 11:09:18 +0200 Subject: [PATCH 102/109] arm64: dts: verdin-imx8mp: add ctrl_sleep_moci# hog Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal may be used to control some power-rails on the carrier board, therefore it should be set to high when the module is booting. To do this as early as possible is generally a good idea and the issue was noticed on the Yavia carrier board where it is needed to power the I2C EEPROM on the carrier board. Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler --- arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 9c6c417f7ee..0162f9b2da3 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -62,6 +62,10 @@ &gpio4 { bootph-pre-ram; + + ctrl-sleep-moci-hog { + bootph-pre-ram; + }; }; &gpio5 { @@ -106,6 +110,10 @@ bootph-pre-ram; }; +&pinctrl_ctrl_sleep_moci { + bootph-pre-ram; +}; + &pinctrl_i2c1 { bootph-pre-ram; }; From 68bad63ee0e4ec532d698c775da599c9b260cbef Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Jul 2023 18:09:01 -0300 Subject: [PATCH 103/109] mx28evk: Convert to CONFIG_DM_SERIAL The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam --- arch/arm/Kconfig | 1 - arch/arm/mach-imx/mxs/Kconfig | 1 + configs/mx28evk_defconfig | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 17d69d27262..e00c9ee4543 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -919,7 +919,6 @@ config ARCH_MX28 bool "NXP i.MX28 family" select CPU_ARM926EJS select GPIO_EXTRA_HEADER - select PL011_SERIAL if !TARGET_XEA select MACH_IMX select SUPPORT_SPL diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index b4a281e82d4..0fd4758cc67 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -41,6 +41,7 @@ choice config TARGET_MX28EVK bool "Support mx28evk" + select PL01X_SERIAL select BOARD_EARLY_INIT_F config TARGET_XEA diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index dad8839a6c1..df0cceaea71 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -62,6 +62,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RTC_MXS=y -CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_USB=y From 9a38d889a1209472aa7736e6b219f69e970dc1fc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Jul 2023 18:09:02 -0300 Subject: [PATCH 104/109] mx23evk: Convert to CONFIG_DM_SERIAL The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam --- arch/arm/Kconfig | 2 +- arch/arm/mach-imx/mxs/Kconfig | 1 + configs/mx23evk_defconfig | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e00c9ee4543..ac079da7527 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -912,7 +912,7 @@ config ARCH_MX23 select CPU_ARM926EJS select GPIO_EXTRA_HEADER select MACH_IMX - select PL011_SERIAL + select PL011_SERIAL if !TARGET_MX23EVK select SUPPORT_SPL config ARCH_MX28 diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 0fd4758cc67..6b9d5c95697 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -14,6 +14,7 @@ config TARGET_MX23_OLINUXINO config TARGET_MX23EVK bool "Support mx23evk" + select PL01X_SERIAL select BOARD_EARLY_INIT_F config TARGET_XFI3 diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index 3602ead8635..7d0e7cc1e00 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y From e713364f36ee19908d46a9e77472d1782fbe9b92 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Jul 2023 18:09:03 -0300 Subject: [PATCH 105/109] mx23_olinuxino: Convert to CONFIG_DM_SERIAL The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam --- arch/arm/Kconfig | 1 - arch/arm/mach-imx/mxs/Kconfig | 1 + configs/mx23_olinuxino_defconfig | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ac079da7527..b3115b054c8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -912,7 +912,6 @@ config ARCH_MX23 select CPU_ARM926EJS select GPIO_EXTRA_HEADER select MACH_IMX - select PL011_SERIAL if !TARGET_MX23EVK select SUPPORT_SPL config ARCH_MX28 diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 6b9d5c95697..d3233d8d14f 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -10,6 +10,7 @@ choice config TARGET_MX23_OLINUXINO bool "Support mx23_olinuxino" + select PL01X_SERIAL select BOARD_EARLY_INIT_F config TARGET_MX23EVK diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 89b69fb3236..24968e18710 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -50,6 +50,7 @@ CONFIG_LED_STATUS_BOOT=0 CONFIG_LED_STATUS_CMD=y CONFIG_MMC_MXS=y CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y From 5386aefb6da2ade3354852e7bff9433634ac16fc Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 12 Jul 2023 12:20:46 +0200 Subject: [PATCH 106/109] config: xea: Disable support for boot methods EXTLINUX and VBE The XEA system (imx287 based) is not using support for EXTLINUX and VBE. As those configuration options have been enabled by default with modern Kconfig it is safe to explicitly disable them. After that change the u-boot.img size has been reduced by ~16 KiB. Signed-off-by: Lukasz Majewski --- configs/imx28_xea_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index c6c6a032453..a174bdb9396 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_FIT=y CONFIG_TIMESTAMP=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8" From 65648b26c67ad63c6ed68fd217233923b9d9d0e8 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 12 Jul 2023 12:20:47 +0200 Subject: [PATCH 107/109] config: xea: Disable support for FAT file system On the XEA (imx287) system the FAT file system is not used neither in SPL nor u-boot proper. Hence, to save ~6KiB of u-boot.img size - it has been disabled. Signed-off-by: Lukasz Majewski --- configs/imx28_xea_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index a174bdb9396..96d15e89af8 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -123,5 +123,4 @@ CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXS_SPI=y -CONFIG_FS_FAT=y # CONFIG_SPL_OF_LIBFDT is not set From 0a4e4143603fc7468ffb3bacf73b52d9620f27db Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 29 May 2023 13:08:34 -0500 Subject: [PATCH 108/109] arm64: imx: imx8mp-beacon: Enable LTO With LTO enabled, SPL shrinks about 10K and U-Boot shrinks about 30K. Signed-off-by: Adam Ford --- configs/imx8mp_beacon_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 99c4043ace8..77a10b901de 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y CONFIG_TARGET_IMX8MP_BEACON=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_LTO=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y From cdbef023e2538da12b3ca4a2b8a5b7bd1c3ada02 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Jul 2023 18:57:57 -0300 Subject: [PATCH 109/109] mx7dsabresd: Retrieve the second MAC address from fuses Currently, a random MAC address is assigned to eth1 in Linux. Fix this behavor by retrieving the second MAC address from the fuses. Signed-off-by: Fabio Estevam --- board/freescale/mx7dsabresd/mx7dsabresd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 2777ae13bce..cff2e6a8717 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -292,6 +292,7 @@ int power_init_board(void) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + unsigned char eth1addr[6]; imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); @@ -303,6 +304,11 @@ int board_late_init(void) */ clrsetbits_le16(&wdog->wcr, 0, 0x10); + /* Get the second MAC address */ + imx_get_mac_from_fuse(1, eth1addr); + if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) + eth_env_set_enetaddr("eth1addr", eth1addr); + return 0; }