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Merge branch '2024-07-23-remove-or-update-some-platforms'

Browse Source 
- Update a few platforms to use DM_I2C finally, and remove a number of
  other older platforms.
This commit is contained in:
Tom Rini 2024-07-23 10:43:58 -06:00
commit f659ba4383
106 changed files with 54 additions and 13792 deletions
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13
arch/arm/dts/Makefile
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@ -1006,21 +1006,8 @@ dtb-$(CONFIG_TARGET_OMAP3_EVM) += \
omap3-evm-37xx.dtb \ omap3-evm-37xx.dtb \
omap3-evm.dtb omap3-evm.dtb
dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
omap3-beagle-xm-ab.dtb \
omap3-beagle-xm.dtb \
omap3-beagle.dtb
dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
omap4-panda.dtb \
omap4-panda-es.dtb
dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
omap4-sdp.dtb \
omap4-sdp-es23plus.dtb
dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
at91-sama7g5ek.dtb at91-sama7g5ek.dtb

68
arch/arm/dts/elpida_ecb240abacn.dtsi
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@ -1,68 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common devices used in different OMAP boards
*/
/ {
elpida_ECB240ABACN: lpddr2 {
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
tDQSCK-max-derated = <6000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
tDQSCK-max-derated = <6000>;
};
};
};

14
arch/arm/dts/omap3-beagle-u-boot.dtsi
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@ -1,14 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
#include "omap3-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart3;
};
};

14
arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi
View File

@ -1,14 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
#include "omap3-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart3;
};
};

13
arch/arm/dts/omap3-beagle-xm-ab.dts
View File

@ -1,13 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap3-beagle-xm.dts"
/ {
/* HS USB Port 2 Power enable was inverted with the xM C */
hsusb2_power: hsusb2_power_reg {
enable-active-high;
};
};

14
arch/arm/dts/omap3-beagle-xm-u-boot.dtsi
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@ -1,14 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
#include "omap3-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart3;
};
};

406
arch/arm/dts/omap3-beagle-xm.dts
View File

@ -1,406 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "omap36xx.dtsi"
/ {
model = "TI OMAP3 BeagleBoard xM";
compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
aliases {
display0 = &dvi0;
display1 = &tv0;
ethernet = &ethernet;
};
led-controller-1 {
compatible = "gpio-leds";
led-1 {
label = "beagleboard::usr0";
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
linux,default-trigger = "heartbeat";
};
led-2 {
label = "beagleboard::usr1";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
linux,default-trigger = "mmc0";
};
};
led-controller-2 {
compatible = "pwm-leds";
led-3 {
label = "beagleboard::pmu_stat";
pwms = <&twl_pwmled 1 7812500>;
max-brightness = <127>;
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3beagle";
ti,mcbsp = <&mcbsp2>;
};
gpio_keys {
compatible = "gpio-keys";
user {
label = "user";
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
linux,code = <0x114>;
wakeup-source;
};
};
/* HS USB Port 2 Power */
hsusb2_power: hsusb2_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb2_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */
startup-delay-us = <70000>;
};
/* HS USB Host PHY on PORT 2 */
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
tfp410: encoder0 {
compatible = "ti,tfp410";
powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
/* XXX pinctrl from twl */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
tv0: connector1 {
compatible = "svideo-connector";
label = "tv";
port {
tv_connector_in: endpoint {
remote-endpoint = <&venc_out>;
};
};
};
etb@5401b000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x5401b000 0x1000>;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {
etb_in: endpoint {
slave-mode;
remote-endpoint = <&etm_out>;
};
};
};
etm@54010000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x54010000 0x1000>;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {
etm_out: endpoint {
remote-endpoint = <&etb_in>;
};
};
};
};
&omap3_pmx_wkup {
gpio1_pins: pinmux_gpio1_pins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
>;
};
dss_dpi_pins2: pinmux_dss_dpi_pins1 {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
>;
};
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_pins
>;
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
>;
};
hsusb2_pins: pinmux_hsusb2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
>;
};
dss_dpi_pins1: pinmux_dss_dpi_pins2 {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_2_pins
>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
twl_power: power {
compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
ti,use_poweroff;
};
};
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <100000>;
};
&mmc1 {
vmmc-supply = <&vmmc1>;
vqmmc-supply = <&vsim>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */
ti,pullups = <0x000002>;
/*
* pulldowns:
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
* BIT(15), BIT(16), BIT(17)
*/
ti,pulldowns = <0x03a1c4>;
};
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
&uart3 {
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins>;
};
&usbhshost {
port2-mode = "ehci-phy";
};
&usbhsehci {
phys = <0 &hsusb2_phy>;
#address-cells = <1>;
#size-cells = <0>;
hub@2 {
compatible = "usb424,9514";
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
};
};
&vaux2 {
regulator-name = "usb_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
&mcbsp2 {
status = "okay";
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <
&dss_dpi_pins1
&dss_dpi_pins2
>;
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
&venc {
status = "okay";
vdda-supply = <&vdac>;
port {
venc_out: endpoint {
remote-endpoint = <&tv_connector_in>;
ti,channels = <2>;
};
};
};

433
arch/arm/dts/omap3-beagle.dts
View File

@ -1,433 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "omap34xx.dtsi"
/ {
model = "TI OMAP3 BeagleBoard";
compatible = "ti,omap3-beagle", "ti,omap3";
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
aliases {
display0 = &dvi0;
display1 = &tv0;
};
leds {
compatible = "gpio-leds";
led-pmu-stat {
label = "beagleboard::pmu_stat";
gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
};
led-heartbeat {
label = "beagleboard::usr0";
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
linux,default-trigger = "heartbeat";
};
led-mmc {
label = "beagleboard::usr1";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
linux,default-trigger = "mmc0";
};
};
/* HS USB Port 2 Power */
hsusb2_power: hsusb2_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb2_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */
startup-delay-us = <70000>;
};
/* HS USB Host PHY on PORT 2 */
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3beagle";
ti,mcbsp = <&mcbsp2>;
};
gpio_keys {
compatible = "gpio-keys";
user {
label = "user";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
linux,code = <0x114>;
wakeup-source;
};
};
tfp410: encoder0 {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
pinctrl-names = "default";
pinctrl-0 = <&tfp410_pins>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
tv0: connector1 {
compatible = "svideo-connector";
label = "tv";
port {
tv_connector_in: endpoint {
remote-endpoint = <&venc_out>;
};
};
};
etb@540000000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x5401b000 0x1000>;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {
etb_in: endpoint {
slave-mode;
remote-endpoint = <&etm_out>;
};
};
};
etm@54010000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x54010000 0x1000>;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {
etm_out: endpoint {
remote-endpoint = <&etb_in>;
};
};
};
};
&omap3_pmx_wkup {
gpio1_pins: pinmux_gpio1_pins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
>;
};
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_pins
>;
hsusb2_pins: pinmux_hsusb2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
>;
};
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_2_pins
>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&i2c3 {
clock-frequency = <100000>;
};
&mmc1 {
vmmc-supply = <&vmmc1>;
vqmmc-supply = <&vsim>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&usbhshost {
port2-mode = "ehci-phy";
};
&usbhsehci {
phys = <0 &hsusb2_phy>;
};
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */
ti,pullups = <0x000002>;
/*
* pulldowns:
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
* BIT(15), BIT(16), BIT(17)
*/
ti,pulldowns = <0x03a1c4>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins>;
};
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
&vaux2 {
regulator-name = "vdd_ehci";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
&mcbsp2 {
status = "okay";
};
/* Needed to power the DPI pins */
&vpll2 {
regulator-always-on;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
&venc {
status = "okay";
vdda-supply = <&vdac>;
port {
venc_out: endpoint {
remote-endpoint = <&tv_connector_in>;
ti,channels = <2>;
};
};
};
&gpmc {
status = "okay";
ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */
/* Chip select 0 */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* NAND I/O window, 4 bytes */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-ecc-opt = "ham1";
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <16>;
#address-cells = <1>;
#size-cells = <1>;
gpmc,device-width = <2>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <36>;
gpmc,cs-wr-off-ns = <36>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <24>;
gpmc,adv-wr-off-ns = <36>;
gpmc,oe-on-ns = <6>;
gpmc,oe-off-ns = <48>;
gpmc,we-on-ns = <6>;
gpmc,we-off-ns = <30>;
gpmc,rd-cycle-ns = <72>;
gpmc,wr-cycle-ns = <72>;
gpmc,access-ns = <54>;
gpmc,wr-access-ns = <30>;
partition@0 {
label = "X-Loader";
reg = <0 0x80000>;
};
partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1e0000>;
};
partition@1c0000 {
label = "U-Boot Env";
reg = <0x260000 0x20000>;
};
partition@280000 {
label = "Kernel";
reg = <0x280000 0x400000>;
};
partition@780000 {
label = "Filesystem";
reg = <0x680000 0xf980000>;
};
};
};

488
arch/arm/dts/omap4-l4-abe.dtsi
View File

@ -1,488 +0,0 @@
&l4_abe { /* 0x40100000 */
compatible = "ti,omap4-l4-abe", "simple-bus";
reg = <0x40100000 0x400>,
<0x40100400 0x400>;
reg-names = "la", "ap";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
<0x49000000 0x49000000 0x100000>;
segment@0 { /* 0x40100000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges =
/* CPU to L4 ABE mapping */
<0x00000000 0x00000000 0x000400>, /* ap 0 */
<0x00000400 0x00000400 0x000400>, /* ap 1 */
<0x00022000 0x00022000 0x001000>, /* ap 2 */
<0x00023000 0x00023000 0x001000>, /* ap 3 */
<0x00024000 0x00024000 0x001000>, /* ap 4 */
<0x00025000 0x00025000 0x001000>, /* ap 5 */
<0x00026000 0x00026000 0x001000>, /* ap 6 */
<0x00027000 0x00027000 0x001000>, /* ap 7 */
<0x00028000 0x00028000 0x001000>, /* ap 8 */
<0x00029000 0x00029000 0x001000>, /* ap 9 */
<0x0002a000 0x0002a000 0x001000>, /* ap 10 */
<0x0002b000 0x0002b000 0x001000>, /* ap 11 */
<0x0002e000 0x0002e000 0x001000>, /* ap 12 */
<0x0002f000 0x0002f000 0x001000>, /* ap 13 */
<0x00030000 0x00030000 0x001000>, /* ap 14 */
<0x00031000 0x00031000 0x001000>, /* ap 15 */
<0x00032000 0x00032000 0x001000>, /* ap 16 */
<0x00033000 0x00033000 0x001000>, /* ap 17 */
<0x00038000 0x00038000 0x001000>, /* ap 18 */
<0x00039000 0x00039000 0x001000>, /* ap 19 */
<0x0003a000 0x0003a000 0x001000>, /* ap 20 */
<0x0003b000 0x0003b000 0x001000>, /* ap 21 */
<0x0003c000 0x0003c000 0x001000>, /* ap 22 */
<0x0003d000 0x0003d000 0x001000>, /* ap 23 */
<0x0003e000 0x0003e000 0x001000>, /* ap 24 */
<0x0003f000 0x0003f000 0x001000>, /* ap 25 */
<0x00080000 0x00080000 0x010000>, /* ap 26 */
<0x00080000 0x00080000 0x001000>, /* ap 27 */
<0x000a0000 0x000a0000 0x010000>, /* ap 28 */
<0x000a0000 0x000a0000 0x001000>, /* ap 29 */
<0x000c0000 0x000c0000 0x010000>, /* ap 30 */
<0x000c0000 0x000c0000 0x001000>, /* ap 31 */
<0x000f1000 0x000f1000 0x001000>, /* ap 32 */
<0x000f2000 0x000f2000 0x001000>, /* ap 33 */
/* L3 to L4 ABE mapping */
<0x49000000 0x49000000 0x000400>, /* ap 0 */
<0x49000400 0x49000400 0x000400>, /* ap 1 */
<0x49022000 0x49022000 0x001000>, /* ap 2 */
<0x49023000 0x49023000 0x001000>, /* ap 3 */
<0x49024000 0x49024000 0x001000>, /* ap 4 */
<0x49025000 0x49025000 0x001000>, /* ap 5 */
<0x49026000 0x49026000 0x001000>, /* ap 6 */
<0x49027000 0x49027000 0x001000>, /* ap 7 */
<0x49028000 0x49028000 0x001000>, /* ap 8 */
<0x49029000 0x49029000 0x001000>, /* ap 9 */
<0x4902a000 0x4902a000 0x001000>, /* ap 10 */
<0x4902b000 0x4902b000 0x001000>, /* ap 11 */
<0x4902e000 0x4902e000 0x001000>, /* ap 12 */
<0x4902f000 0x4902f000 0x001000>, /* ap 13 */
<0x49030000 0x49030000 0x001000>, /* ap 14 */
<0x49031000 0x49031000 0x001000>, /* ap 15 */
<0x49032000 0x49032000 0x001000>, /* ap 16 */
<0x49033000 0x49033000 0x001000>, /* ap 17 */
<0x49038000 0x49038000 0x001000>, /* ap 18 */
<0x49039000 0x49039000 0x001000>, /* ap 19 */
<0x4903a000 0x4903a000 0x001000>, /* ap 20 */
<0x4903b000 0x4903b000 0x001000>, /* ap 21 */
<0x4903c000 0x4903c000 0x001000>, /* ap 22 */
<0x4903d000 0x4903d000 0x001000>, /* ap 23 */
<0x4903e000 0x4903e000 0x001000>, /* ap 24 */
<0x4903f000 0x4903f000 0x001000>, /* ap 25 */
<0x49080000 0x49080000 0x010000>, /* ap 26 */
<0x49080000 0x49080000 0x001000>, /* ap 27 */
<0x490a0000 0x490a0000 0x010000>, /* ap 28 */
<0x490a0000 0x490a0000 0x001000>, /* ap 29 */
<0x490c0000 0x490c0000 0x010000>, /* ap 30 */
<0x490c0000 0x490c0000 0x001000>, /* ap 31 */
<0x490f1000 0x490f1000 0x001000>, /* ap 32 */
<0x490f2000 0x490f2000 0x001000>; /* ap 33 */
target-module@22000 { /* 0x40122000, ap 2 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2208c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x22000 0x1000>,
<0x49022000 0x49022000 0x1000>;
mcbsp1: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@24000 { /* 0x40124000, ap 4 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2408c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x24000 0x1000>,
<0x49024000 0x49024000 0x1000>;
mcbsp2: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@26000 { /* 0x40126000, ap 6 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x26000 0x1000>,
<0x49026000 0x49026000 0x1000>;
mcbsp3: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@28000 { /* 0x40128000, ap 8 08.0 */
compatible = "ti,sysc-mcasp", "ti,sysc";
reg = <0x28000 0x4>,
<0x28004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x28000 0x1000>,
<0x49028000 0x49028000 0x1000>;
/*
* Child device unsupported by davinci-mcasp. At least
* RX path is disabled for omap4, and only DIT mode
* works with no I2S. See also old Android kernel
* omap-mcasp driver for more information.
*/
};
target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2a000 0x1000>,
<0x4902a000 0x4902a000 0x1000>;
};
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2e000 0x1000>,
<0x4902e000 0x4902e000 0x1000>;
dmic: dmic@0 {
compatible = "ti,omap4-dmic";
reg = <0x0 0x7f>, /* MPU private access */
<0x4902e000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 67>;
dma-names = "up_link";
status = "disabled";
};
};
target-module@30000 { /* 0x40130000, ap 14 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x30000 0x4>,
<0x30010 0x4>,
<0x30014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x30000 0x1000>,
<0x49030000 0x49030000 0x1000>;
wdt3: wdt@0 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
};
};
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x32000 0x1000>,
<0x49032000 0x49032000 0x1000>;
/* Must be only enabled for boards with pdmclk wired */
status = "disabled";
mcpdm: mcpdm@0 {
compatible = "ti,omap4-mcpdm";
reg = <0x0 0x7f>, /* MPU private access */
<0x49032000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
};
};
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x38000 0x1000>,
<0x49038000 0x49038000 0x1000>;
timer5: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x49038000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
};
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3a000 0x1000>,
<0x4903a000 0x4903a000 0x1000>;
timer6: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903a000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
};
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3c000 0x1000>,
<0x4903c000 0x4903c000 0x1000>;
timer7: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903c000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
};
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3e000 0x1000>,
<0x4903e000 0x4903e000 0x1000>;
timer8: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903e000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,timer-dsp;
};
};
target-module@80000 { /* 0x40180000, ap 26 1a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000 0x10000>,
<0x49080000 0x49080000 0x10000>;
};
target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xa0000 0x10000>,
<0x490a0000 0x490a0000 0x10000>;
};
target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc0000 0x10000>,
<0x490c0000 0x490c0000 0x10000>;
};
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xf1000 0x4>,
<0xf1010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf1000 0x1000>,
<0x490f1000 0x490f1000 0x1000>;
/*
* No child device binding or driver in mainline.
* See Android tree and related upstreaming efforts
* for the old driver.
*/
};
};
};

2473
arch/arm/dts/omap4-l4.dtsi
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44
arch/arm/dts/omap4-mcpdm.dtsi
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@ -1,44 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common omap4 mcpdm configuration
*
* Only include this file if your board has pdmclk wired from the
* pmic to ABE as mcpdm uses an external clock for the module.
*/
&omap4_pmx_core {
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
/* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
/* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
/* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)
/* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
/* 0x4a10010e abe_clks.abe_clks ah26 */
OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
};
&mcpdm_module {
/*
* McPDM pads must be muxed at the interconnect target module
* level as the module on the SoC needs external clock from
* the PMIC
*/
pinctrl-names = "default";
pinctrl-0 = <&mcpdm_pins>;
status = "okay";
};
&mcpdm {
clocks = <&twl6040>;
clock-names = "pdmclk";
};

573
arch/arm/dts/omap4-panda-common.dtsi
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@ -1,573 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/input/input.h>
#include "elpida_ecb240abacn.dtsi"
#include "omap4-mcpdm.dtsi"
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
chosen {
stdout-path = &uart3;
};
aliases {
display0 = &dvi0;
display1 = &hdmi0;
ethernet = &ethernet;
};
leds: leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <
&led_wkgpio_pins
>;
led-heartbeat {
label = "pandaboard::status1";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-mmc {
label = "pandaboard::status2";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
gpio_keys: gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <
&button_pins
>;
buttonS2 {
label = "button S2";
gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */
linux,code = <BTN_0>;
wakeup-source;
};
};
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "PandaBoard";
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
"AFMR", "Line In";
};
/* HS USB Port 1 Power */
hsusb1_power: hsusb1_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */
startup-delay-us = <70000>;
enable-active-high;
/*
* boot-on is required along with always-on as the
* regulator framework doesn't enable the regulator
* if boot-on is not there.
*/
regulator-always-on;
regulator-boot-on;
};
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
#phy-cells = <0>;
vcc-supply = <&hsusb1_power>;
clocks = <&auxclk3_ck>;
clock-names = "main_clk";
clock-frequency = <19200000>;
};
/* regulator for wl12xx on sdio5 */
wl12xx_vmmc: wl12xx_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
tfp410: encoder0 {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
tpd12s015: encoder1 {
compatible = "ti,tpd12s015";
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
<&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
<&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
hdmi0: connector1 {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&dss_dpi_pins
&tfp410_pins
&dss_hdmi_pins
&tpd12s015_pins
&hsusbb1_pins
>;
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */
OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */
OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */
OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */
OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */
OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */
OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */
OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */
OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */
OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */
OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */
OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */
OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */
OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */
OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */
OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */
OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */
OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */
OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */
OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */
OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */
OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */
OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */
OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */
OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */
OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */
OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */
OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */
>;
};
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */
>;
};
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
>;
};
hsusbb1_pins: pinmux_hsusbb1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
>;
};
/*
* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
* REVISIT: Are the pull-ups needed for GPIO 48 and 49?
*/
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */
OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */
OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */
>;
};
/* wl12xx GPIO inputs and SDIO pins */
wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
>;
};
button_pins: pinmux_button_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */
>;
};
};
&omap4_pmx_wkup {
led_wkgpio_pins: pinmux_leds_wkpins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* IRQ# = 7 */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
};
twl6040: twl@4b {
compatible = "ti,twl6040";
#clock-cells = <0>;
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&twl6040_pins>;
/* IRQ# = 119 */
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
vio-supply = <&v1v8>;
v2v1-supply = <&v2v1>;
enable-active-high;
};
};
#include "twl6030.dtsi"
#include "twl6030_omap4.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <100000>;
/*
* Display monitor features are burnt in their EEPROM as EDID data.
* The EEPROM is connected as I2C slave device.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&mmc4 {
status = "disabled";
};
&mmc5 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_pins>;
vmmc-supply = <&wl12xx_vmmc>;
interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x10e>;
non-removable;
bus-width = <4>;
cap-power-off-card;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
/* gpio_53 with gpmc_ncs3 pad as wakeup */
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x3a>;
interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>;
};
};
&emif1 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&emif2 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&mcbsp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
status = "okay";
};
&twl_usb_comparator {
usb-supply = <&vusb>;
};
&uart2 {
interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART2_RX>;
};
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART3_RX>;
};
&uart4 {
interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART4_RX>;
};
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};
&usbhshost {
port1-mode = "ehci-phy";
};
&usbhsehci {
phys = <&hsusb1_phy>;
#address-cells = <1>;
#size-cells = <0>;
hub@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
};
};
&dss {
status = "okay";
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
&dsi2 {
status = "okay";
vdd-supply = <&vcxio>;
};
&hdmi {
status = "okay";
vdda-supply = <&vdac>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};

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arch/arm/dts/omap4-panda-es.dts
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@ -1,82 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "omap4460.dtsi"
#include "omap4-panda-common.dtsi"
/ {
model = "TI OMAP4 PandaBoard-ES";
compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
};
/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
&sound {
ti,model = "PandaBoardES";
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"AFML", "Line In",
"AFMR", "Line In";
};
/* PandaboardES has external pullups on SCL & SDA */
&dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};
&omap4_pmx_core {
led_gpio_pins: gpio_led_pmx {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
>;
};
button_pins: pinmux_button_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
>;
};
};
&led_wkgpio_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
&leds {
pinctrl-0 = <
&led_gpio_pins
&led_wkgpio_pins
>;
led-heartbeat {
gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
};
led-mmc {
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
};
&gpio_keys {
buttonS2 {
gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */
};
};
&gpio1_target {
ti,no-reset-on-init;
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "omap443x.dtsi"
#include "omap4-panda-common.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
};

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arch/arm/dts/omap4-sdp-es23plus.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap4-sdp.dts"
/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
&dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "omap443x.dtsi"
#include "elpida_ecb240abacn.dtsi"
#include "omap4-mcpdm.dtsi"
/ {
model = "TI OMAP4 SDP board";
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
aliases {
display0 = &lcd0;
display1 = &lcd1;
display2 = &hdmi0;
};
vdd_eth: fixedregulator-vdd-eth {
pinctrl-names = "default";
pinctrl-0 = <&enet_enable_gpio>;
compatible = "regulator-fixed";
regulator-name = "VDD_ETH";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */
enable-active-high;
regulator-boot-on;
startup-delay-us = <25000>;
};
vbat: fixedregulator-vbat {
compatible = "regulator-fixed";
regulator-name = "VBAT";
regulator-min-microvolt = <3750000>;
regulator-max-microvolt = <3750000>;
regulator-boot-on;
};
led-controller-1 {
compatible = "gpio-leds";
led-1 {
label = "omap4:green:debug0";
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
};
led-2 {
label = "omap4:green:debug1";
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
};
led-3 {
label = "omap4:green:debug2";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
};
led-4 {
label = "omap4:green:debug3";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
};
led-5 {
label = "omap4:green:debug4";
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
};
led-6 {
label = "omap4:blue:user";
gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
};
led-7 {
label = "omap4:red:user";
gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
};
led-8 {
label = "omap4:green:user";
gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
};
};
led-controller-2 {
compatible = "pwm-leds";
led-9 {
label = "omap4::keypad";
pwms = <&twl_pwm 0 7812500>;
max-brightness = <127>;
};
led-10 {
label = "omap4:green:chrg";
pwms = <&twl_pwmled 0 7812500>;
max-brightness = <255>;
};
};
backlight {
compatible = "pwm-backlight";
pwms = <&twl_pwm 1 7812500>;
brightness-levels = <
0 10 20 30 40
50 60 70 80 90
100 110 120 127
>;
default-brightness-level = <13>;
};
sound {
compatible = "ti,abe-twl6040";
ti,model = "SDP4430";
ti,jack-detection = <1>;
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
ti,dmic = <&dmic>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Earphone Spk", "EP",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"Vibrator", "VIBRAL",
"Vibrator", "VIBRAR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"MAINMIC", "Main Handset Mic",
"Main Handset Mic", "Main Mic Bias",
"SUBMIC", "Sub Handset Mic",
"Sub Handset Mic", "Main Mic Bias",
"AFML", "Line In",
"AFMR", "Line In",
"DMic", "Digital Mic",
"Digital Mic", "Digital Mic1 Bias";
};
/* regulator for wl12xx on sdio5 */
wl12xx_vmmc: wl12xx_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
<&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
<&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "c";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&dss_hdmi_pins
&tpd12s015_pins
>;
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */
OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
>;
};
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */
OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */
>;
};
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
>;
};
dmic_pins: pinmux_dmic_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */
OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */
OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */
OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */
OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */
OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
>;
};
mcspi1_pins: pinmux_mcspi1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
>;
};
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
>;
};
/* wl12xx GPIO output for WLAN_EN */
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */
>;
};
/* wl12xx GPIO inputs and SDIO pins */
wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
>;
};
/* gpio_48 for ENET_ENABLE */
enet_enable_gpio: pinmux_enet_enable_gpio {
pinctrl-single,pins = <
OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */
>;
};
ks8851_pins: pinmux_ks8851_pins {
pinctrl-single,pins = <
/* ENET_INT */
OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */
/*
* Misterious pin which makes the ethernet working
* The legacy board file requested this pin on boot
* (ETH_KS8851_QUART) and set it to high, similarly to
* the ENET_ENABLE pin.
* We could use gpio-hog to keep it high, but let's use
* it as a reset GPIO for ks8851.
*/
OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
};
twl6040: twl@4b {
compatible = "ti,twl6040";
#clock-cells = <0>;
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&twl6040_pins>;
/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
vio-supply = <&v1v8>;
v2v1-supply = <&v2v1>;
enable-active-high;
/* regulators for vibra motor */
vddvibl-supply = <&vbat>;
vddvibr-supply = <&vbat>;
vibra {
/* Vibra driver, motor resistance parameters */
ti,vibldrv-res = <8>;
ti,vibrdrv-res = <3>;
ti,viblmotor-res = <10>;
ti,vibrmotor-res = <10>;
};
};
};
#include "twl6030.dtsi"
#include "twl6030_omap4.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
/*
* Temperature Sensor
* https://www.ti.com/lit/ds/symlink/tmp105.pdf
*/
tmp105@48 {
compatible = "ti,tmp105";
reg = <0x48>;
};
/*
* Ambient Light Sensor
* http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
*/
bh1780@29 {
compatible = "rohm,bh1780";
reg = <0x29>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
/*
* 3-Axis Digital Compass
* https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
*/
hmc5843@1e {
compatible = "honeywell,hmc5843";
reg = <0x1e>;
};
};
&mcspi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi1_pins>;
eth@0 {
pinctrl-names = "default";
pinctrl-0 = <&ks8851_pins>;
compatible = "ks8851";
spi-max-frequency = <24000000>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
vdd-supply = <&vdd_eth>;
reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
};
};
&mmc1 {
vmmc-supply = <&vmmc>;
bus-width = <8>;
};
&mmc2 {
vmmc-supply = <&vaux1>;
bus-width = <8>;
ti,non-removable;
};
&mmc3 {
status = "disabled";
};
&mmc4 {
status = "disabled";
};
&mmc5 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_pins>;
vmmc-supply = <&wl12xx_vmmc>;
non-removable;
bus-width = <4>;
cap-power-off-card;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1281";
reg = <2>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>;
};
};
&emif1 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&emif2 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&keypad {
keypad,num-rows = <8>;
keypad,num-columns = <8>;
linux,keymap = <0x00000012 /* KEY_E */
0x00010013 /* KEY_R */
0x00020014 /* KEY_T */
0x00030066 /* KEY_HOME */
0x0004003f /* KEY_F5 */
0x000500f0 /* KEY_UNKNOWN */
0x00060017 /* KEY_I */
0x0007002a /* KEY_LEFTSHIFT */
0x01000020 /* KEY_D*/
0x01010021 /* KEY_F */
0x01020022 /* KEY_G */
0x010300e7 /* KEY_SEND */
0x01040040 /* KEY_F6 */
0x010500f0 /* KEY_UNKNOWN */
0x01060025 /* KEY_K */
0x0107001c /* KEY_ENTER */
0x0200002d /* KEY_X */
0x0201002e /* KEY_C */
0x0202002f /* KEY_V */
0x0203006b /* KEY_END */
0x02040041 /* KEY_F7 */
0x020500f0 /* KEY_UNKNOWN */
0x02060034 /* KEY_DOT */
0x0207003a /* KEY_CAPSLOCK */
0x0300002c /* KEY_Z */
0x0301004e /* KEY_KPLUS */
0x03020030 /* KEY_B */
0x0303003b /* KEY_F1 */
0x03040042 /* KEY_F8 */
0x030500f0 /* KEY_UNKNOWN */
0x03060018 /* KEY_O */
0x03070039 /* KEY_SPACE */
0x04000011 /* KEY_W */
0x04010015 /* KEY_Y */
0x04020016 /* KEY_U */
0x0403003c /* KEY_F2 */
0x04040073 /* KEY_VOLUMEUP */
0x040500f0 /* KEY_UNKNOWN */
0x04060026 /* KEY_L */
0x04070069 /* KEY_LEFT */
0x0500001f /* KEY_S */
0x05010023 /* KEY_H */
0x05020024 /* KEY_J */
0x0503003d /* KEY_F3 */
0x05040043 /* KEY_F9 */
0x05050072 /* KEY_VOLUMEDOWN */
0x05060032 /* KEY_M */
0x0507006a /* KEY_RIGHT */
0x06000010 /* KEY_Q */
0x0601001e /* KEY_A */
0x06020031 /* KEY_N */
0x0603009e /* KEY_BACK */
0x0604000e /* KEY_BACKSPACE */
0x060500f0 /* KEY_UNKNOWN */
0x06060019 /* KEY_P */
0x06070067 /* KEY_UP */
0x07000094 /* KEY_PROG1 */
0x07010095 /* KEY_PROG2 */
0x070200ca /* KEY_PROG3 */
0x070300cb /* KEY_PROG4 */
0x0704003e /* KEY_F4 */
0x070500f0 /* KEY_UNKNOWN */
0x07060160 /* KEY_OK */
0x0707006c>; /* KEY_DOWN */
linux,input-no-autorepeat;
};
&uart2 {
interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART2_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART3_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&uart4 {
interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART4_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
};
&mcbsp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
status = "okay";
};
&mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
status = "okay";
};
&dmic {
pinctrl-names = "default";
pinctrl-0 = <&dmic_pins>;
status = "okay";
};
&twl_usb_comparator {
usb-supply = <&vusb>;
};
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};
&dss {
status = "okay";
};
&dsi1 {
status = "okay";
vdd-supply = <&vcxio>;
port {
dsi1_out_ep: endpoint {
remote-endpoint = <&lcd0_in>;
lanes = <0 1 2 3 4 5>;
};
};
lcd0: panel@0 {
compatible = "tpo,taal", "panel-dsi-cm";
reg = <0>;
label = "lcd0";
reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
port {
lcd0_in: endpoint {
remote-endpoint = <&dsi1_out_ep>;
};
};
};
};
&dsi2 {
status = "okay";
vdd-supply = <&vcxio>;
port {
dsi2_out_ep: endpoint {
remote-endpoint = <&lcd1_in>;
lanes = <0 1 2 3 4 5>;
};
};
lcd1: panel@0 {
compatible = "tpo,taal", "panel-dsi-cm";
reg = <0>;
label = "lcd1";
reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
port {
lcd1_in: endpoint {
remote-endpoint = <&dsi2_out_ep>;
};
};
};
};
&hdmi {
status = "okay";
vdda-supply = <&vdac>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};

47
arch/arm/dts/omap4-u-boot.dtsi
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@ -1,47 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* (C) Copyright 2020 Tero Kristo <t-kristo@ti.com>
*/
&l4_cfg {
segment@0 {
/* SCM Core */
target-module@2000 {
compatible = "simple-bus";
};
/* USB HS */
target-module@64000 {
compatible = "simple-bus";
};
};
segment@80000 {
/* USB OTG */
target-module@2b000 {
compatible = "simple-bus";
};
};
};
&l4_per {
segment@0 {
/* UART3 */
target-module@20000 {
compatible = "simple-bus";
};
/* I2C1 */
target-module@70000 {
compatible = "simple-bus";
};
/* MMC1 */
target-module@9c000 {
compatible = "simple-bus";
};
};
};

663
arch/arm/dts/omap4.dtsi
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@ -1,663 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/omap4.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap4.h>
/ {
compatible = "ti,omap4430", "ti,omap4";
interrupt-parent = <&wakeupgen>;
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&L2>;
reg = <0x0>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&L2>;
reg = <0x1>;
};
};
/*
* Note that 4430 needs cross trigger interface (CTI) supported
* before we can configure the interrupts. This means sampling
* events are not supported for pmu. Note that 4460 does not use
* CTI, see also 4460.dtsi.
*/
pmu {
compatible = "arm,cortex-a9-pmu";
ti,hwmods = "debugss";
};
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
interrupt-parent = <&gic>;
};
L2: cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
cache-unified;
cache-level = <2>;
};
local-timer@48240600 {
compatible = "arm,cortex-a9-twd-timer";
clocks = <&mpu_periphclk>;
reg = <0x48240600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@48281000 {
compatible = "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48281000 0x1000>;
interrupt-parent = <&gic>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
dsp {
compatible = "ti,omap3-c64";
};
iva {
compatible = "ti,ivahd";
ti,hwmods = "iva";
};
};
/*
* XXX: Use a flat representation of the OMAP4 interconnect.
* The real OMAP interconnect network is quite complex.
* Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0x44000000 0x1000>,
<0x44800000 0x2000>,
<0x45000000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l4_wkup: interconnect@4a300000 {
};
l4_cfg: interconnect@4a000000 {
};
l4_per: interconnect@48000000 {
};
l4_abe: interconnect@40100000 {
};
ocmcram: sram@40304000 {
compatible = "mmio-sram";
reg = <0x40304000 0xa000>; /* 40k */
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 4>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
ti,no-idle-on-init;
clocks = <&l3_div_ck>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
reg = <0x52000000 0x4>,
<0x52000010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-delay-us = <2>;
clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x52000000 0x1000000>;
/* No child device binding, driver in staging */
};
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
<0x55082010 0x4>,
<0x55082014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
ranges = <0x0 0x55082000 0x100>;
#size-cells = <1>;
#address-cells = <1>;
mmu_ipu: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
target-module@4012c000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
<0x4902c000 0x4902c000 0x1000>; /* L3 */
/* No child device binding or driver in mainline */
};
dmm@4e000000 {
compatible = "ti,omap4-dmm";
reg = <0x4e000000 0x800>;
interrupts = <0 113 0x4>;
ti,hwmods = "dmm";
};
emif1: emif@4c000000 {
compatible = "ti,emif-4d";
reg = <0x4c000000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif1";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
emif2: emif@4d000000 {
compatible = "ti,emif-4d";
reg = <0x4d000000 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif2";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
aes1_target: target-module@4b501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b501080 0x4>,
<0x4b501084 0x4>,
<0x4b501088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b501000 0x1000>;
aes1: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 111>, <&sdma 110>;
dma-names = "tx", "rx";
};
};
aes2_target: target-module@4b701000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b701080 0x4>,
<0x4b701084 0x4>,
<0x4b701088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b701000 0x1000>;
aes2: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 114>, <&sdma 113>;
dma-names = "tx", "rx";
};
};
sham_target: target-module@4b100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x4b100100 0x4>,
<0x4b100110 0x4>,
<0x4b100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x300>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 119>;
dma-names = "rx";
};
};
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v2";
regulator-name = "abb_mpu";
#address-cells = <0>;
#size-cells = <0>;
ti,tranxdone-status-mask = <0x80>;
clocks = <&sys_clkin_ck>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
status = "disabled";
};
abb_iva: regulator-abb-iva {
compatible = "ti,abb-v2";
regulator-name = "abb_iva";
#address-cells = <0>;
#size-cells = <0>;
ti,tranxdone-status-mask = <0x80000000>;
clocks = <&sys_clkin_ck>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
status = "disabled";
};
sgx_module: target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
/*
* DSS is only using l3 mapping without l4 as noted in the TRM
* "10.1.3 DSS Register Manual" for omap4460.
*/
target-module@58000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58000000 4>,
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x58000000 0x1000000>;
dss: dss@0 {
compatible = "ti,omap4-dss";
reg = <0 0x80>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000000>;
target-module@1000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x1000 0x4>,
<0x1010 0x4>,
<0x1014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x1000>;
dispc@0 {
compatible = "ti,omap4-dispc";
reg = <0 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
};
target-module@2000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2000 0x4>,
<0x2010 0x4>,
<0x2014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
rfbi: encoder@0 {
reg = <0 0x1000>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
};
target-module@3000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x3000 0x4>;
reg-names = "rev";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x3000 0x1000>;
venc: encoder@0 {
compatible = "ti,omap4-venc";
reg = <0 0x1000>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck";
};
};
target-module@4000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4000 0x1000>;
dsi1: encoder@0 {
compatible = "ti,omap4-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
#address-cells = <1>;
#size-cells = <0>;
};
};
target-module@5000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x5000 0x4>,
<0x5010 0x4>,
<0x5014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5000 0x1000>;
dsi2: encoder@0 {
compatible = "ti,omap4-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
#address-cells = <1>;
#size-cells = <0>;
};
};
target-module@6000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x6000 0x4>,
<0x6010 0x4>;
reg-names = "rev", "sysc";
/*
* Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
* but HDMI audio will fail with them.
*/
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x2000>;
hdmi: encoder@0 {
compatible = "ti,omap4-hdmi";
reg = <0 0x200>,
<0x200 0x100>,
<0x300 0x100>,
<0x400 0x1000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
};
};
};
};
};
};
#include "omap4-l4.dtsi"
#include "omap4-l4-abe.dtsi"
#include "omap44xx-clocks.dtsi"
&prm {
prm_tesla: prm@400 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
#reset-cells = <1>;
};
prm_core: prm@700 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;
#reset-cells = <1>;
};
prm_ivahd: prm@f00 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0xf00 0x100>;
#reset-cells = <1>;
};
prm_device: prm@1b00 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1b00 0x40>;
#reset-cells = <1>;
};
};

16
arch/arm/dts/omap443x-clocks.dtsi
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@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP4 clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&prm_clocks {
bandgap_fclk: bandgap_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "bandgap_fclk";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
};
};

73
arch/arm/dts/omap443x.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP443x SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap4.dtsi"
/ {
cpus {
cpu0: cpu@0 {
/* OMAP443x variants OPP50-OPPNT */
operating-points = <
/* kHz uV */
300000 1025000
600000 1200000
800000 1313000
1008000 1375000
>;
clock-latency = <300000>; /* From legacy driver */
/* cooling options */
#cooling-cells = <2>; /* min followed by max */
};
};
thermal-zones {
#include "omap4-cpu-thermal.dtsi"
};
ocp {
bandgap: bandgap@4a002260 {
reg = <0x4a002260 0x4
0x4a00232C 0x4>;
compatible = "ti,omap4430-bandgap";
#thermal-sensor-cells = <0>;
};
};
ocp {
abb_mpu: regulator-abb-mpu {
status = "okay";
reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>;
reg-names = "base-address", "int-address";
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1025000 0 0 0 0 0
1200000 0 0 0 0 0
1313000 0 0 0 0 0
1375000 1 0 0 0 0
1389000 1 0 0 0 0
>;
};
/* Default unused, just provide register info for record */
abb_iva: regulator-abb-iva {
reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>;
reg-names = "base-address", "int-address";
};
};
};
&cpu_thermal {
coefficients = <0 20000>;
};
/include/ "omap443x-clocks.dtsi"

128
arch/arm/dts/omap4460.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP4460 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap4.dtsi"
/ {
cpus {
/* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
cpu0: cpu@0 {
operating-points = <
/* kHz uV */
350000 1025000
700000 1200000
920000 1313000
>;
clock-latency = <300000>; /* From legacy driver */
/* cooling options */
#cooling-cells = <2>; /* min followed by max */
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "debugss";
};
thermal-zones {
#include "omap4-cpu-thermal.dtsi"
};
ocp {
bandgap: bandgap@4a002260 {
reg = <0x4a002260 0x4
0x4a00232C 0x4
0x4a002378 0x18>;
compatible = "ti,omap4460-bandgap";
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
#thermal-sensor-cells = <0>;
};
abb_mpu: regulator-abb-mpu {
status = "okay";
reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
<0x4A002268 0x4>;
reg-names = "base-address", "int-address",
"efuse-address";
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1025000 0 0 0 0 0
1200000 0 0 0 0 0
1313000 0 0 0x100000 0x40000 0
1375000 1 0 0 0 0
1389000 1 0 0 0 0
>;
};
abb_iva: regulator-abb-iva {
status = "okay";
reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
<0x4A002268 0x4>;
reg-names = "base-address", "int-address",
"efuse-address";
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
950000 0 0 0 0 0
1140000 0 0 0 0 0
1291000 0 0 0x200000 0 0
1375000 1 0 0 0 0
1376000 1 0 0 0 0
>;
};
};
};
&cpu_thermal {
coefficients = <348 (-9301)>;
};
/* Only some L4 CFG interconnect ranges are different on 4460 */
&l4_cfg_segment_300000 {
ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
<0x00040000 0x00340000 0x001000>, /* ap 68 */
<0x00020000 0x00320000 0x004000>, /* ap 71 */
<0x00024000 0x00324000 0x002000>, /* ap 72 */
<0x00026000 0x00326000 0x001000>, /* ap 73 */
<0x00027000 0x00327000 0x001000>, /* ap 74 */
<0x00028000 0x00328000 0x001000>, /* ap 75 */
<0x00029000 0x00329000 0x001000>, /* ap 76 */
<0x00030000 0x00330000 0x010000>, /* ap 77 */
<0x0002a000 0x0032a000 0x002000>, /* ap 90 */
<0x0002c000 0x0032c000 0x004000>, /* ap 91 */
<0x00010000 0x00310000 0x008000>, /* ap 92 */
<0x00018000 0x00318000 0x004000>, /* ap 93 */
<0x0001c000 0x0031c000 0x002000>, /* ap 94 */
<0x0001e000 0x0031e000 0x002000>; /* ap 95 */
};
&l4_cfg_target_0 {
ranges = <0x00000000 0x00000000 0x00010000>,
<0x00010000 0x00010000 0x00008000>,
<0x00018000 0x00018000 0x00004000>,
<0x0001c000 0x0001c000 0x00002000>,
<0x0001e000 0x0001e000 0x00002000>,
<0x00020000 0x00020000 0x00004000>,
<0x00024000 0x00024000 0x00002000>,
<0x00026000 0x00026000 0x00001000>,
<0x00027000 0x00027000 0x00001000>,
<0x00028000 0x00028000 0x00001000>,
<0x00029000 0x00029000 0x00001000>,
<0x0002a000 0x0002a000 0x00002000>,
<0x0002c000 0x0002c000 0x00004000>,
<0x00030000 0x00030000 0x00010000>;
};
/include/ "omap446x-clocks.dtsi"

24
arch/arm/dts/omap446x-clocks.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP4 clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&prm_clocks {
div_ts_ck: div_ts_ck@1888 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l4_wkup_clk_mux_ck>;
ti,bit-shift = <24>;
reg = <0x1888>;
ti,dividers = <8>, <16>, <32>;
};
bandgap_ts_fclk: bandgap_ts_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&div_ts_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
};
};

1324
arch/arm/dts/omap44xx-clocks.dtsi
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105
arch/arm/dts/twl6030.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
* https://www.ti.com/lit/ds/symlink/twl6030.pdf
*/
&twl {
compatible = "ti,twl6030";
interrupt-controller;
#interrupt-cells = <1>;
rtc {
compatible = "ti,twl4030-rtc";
interrupts = <11>;
};
vaux1: regulator-vaux1 {
compatible = "ti,twl6030-vaux1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
vaux2: regulator-vaux2 {
compatible = "ti,twl6030-vaux2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2800000>;
};
vaux3: regulator-vaux3 {
compatible = "ti,twl6030-vaux3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
vmmc: regulator-vmmc {
compatible = "ti,twl6030-vmmc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
};
vpp: regulator-vpp {
compatible = "ti,twl6030-vpp";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2500000>;
};
vusim: regulator-vusim {
compatible = "ti,twl6030-vusim";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2900000>;
};
vdac: regulator-vdac {
compatible = "ti,twl6030-vdac";
};
vana: regulator-vana {
compatible = "ti,twl6030-vana";
};
vcxio: regulator-vcxio {
compatible = "ti,twl6030-vcxio";
regulator-always-on;
};
vusb: regulator-vusb {
compatible = "ti,twl6030-vusb";
};
v1v8: regulator-v1v8 {
compatible = "ti,twl6030-v1v8";
regulator-always-on;
};
v2v1: regulator-v2v1 {
compatible = "ti,twl6030-v2v1";
regulator-always-on;
};
twl_usb_comparator: usb-comparator {
compatible = "ti,twl6030-usb";
interrupts = <4>, <10>;
};
twl_pwm: pwm {
/* provides two PWMs (id 0, 1 for PWM1 and PWM2) */
compatible = "ti,twl6030-pwm";
#pwm-cells = <2>;
};
twl_pwmled: pwmled {
/* provides one PWM (id 0 for Charging indicator LED) */
compatible = "ti,twl6030-pwmled";
#pwm-cells = <2>;
};
gpadc {
compatible = "ti,twl6030-gpadc";
interrupts = <3>;
#io-channel-cells = <1>;
};
};

35
arch/arm/dts/twl6030_omap4.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
&twl {
/*
* On most OMAP4 platforms, the twl6030 IRQ line is connected
* to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is
* connected to the fref_clk0_out.sys_drm_msecure line.
* Therefore, configure the defaults for the SYS_NIRQ1 and
* fref_clk0_out.sys_drm_msecure pins here.
*/
pinctrl-names = "default";
pinctrl-0 = <
&twl6030_pins
&twl6030_wkup_pins
>;
};
&omap4_pmx_wkup {
twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
>;
};
};
&omap4_pmx_core {
twl6030_pins: pinmux_twl6030_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
>;
};
};

249
arch/arm/include/asm/arch-omap4/clock.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
*/
#ifndef _CLOCKS_OMAP4_H_
#define _CLOCKS_OMAP4_H_
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
* loop, allow for a minimum of 2 ms wait (in reality the wait will be
* much more than that)
*/
#define LDELAY 1000000
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
#define CM_DLL_CTRL_NO_OVERRIDE 0
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
#define CM_CLKMODE_DPLL_EN_SHIFT 0
#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
#define DPLL_EN_STOP 1
#define DPLL_EN_MN_BYPASS 4
#define DPLL_EN_LOW_POWER_BYPASS 5
#define DPLL_EN_FAST_RELOCK_BYPASS 6
#define DPLL_EN_LOCK 7
/* CM_IDLEST_DPLL fields */
#define ST_DPLL_CLK_MASK 1
/* CM_CLKSEL_DPLL */
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
#define CM_CLKSEL_DPLL_M_SHIFT 8
#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
#define CM_CLKSEL_DPLL_N_SHIFT 0
#define CM_CLKSEL_DPLL_N_MASK 0x7F
#define CM_CLKSEL_DCC_EN_SHIFT 22
#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT 0
#define CLKSEL_L3_SHIFT 4
#define CLKSEL_L4_SHIFT 8
#define CLKSEL_CORE_X2_DIV_1 0
#define CLKSEL_L3_CORE_DIV_2 1
#define CLKSEL_L4_L3_DIV_2 1
/* CM_ABE_PLL_REF_CLKSEL */
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
/* CM_BYPCLK_DPLL_IVA */
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
/* CM_SHADOW_FREQ_CONFIG1 */
#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
/*CM_<clock_domain>__CLKCTRL */
#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
#define CD_CLKCTRL_CLKTRCTRL_MASK 3
#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
#define MODULE_CLKCTRL_MODULEMODE_MASK 3
#define MODULE_CLKCTRL_IDLEST_SHIFT 16
#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
#define MODULE_CLKCTRL_IDLEST_IDLE 2
#define MODULE_CLKCTRL_IDLEST_DISABLED 3
/* CM_L4PER_GPIO4_CLKCTRL */
#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
/* CM_L3INIT_HSMMCn_CLKCTRL */
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
/* CM_CAM_ISS_CLKCTRL */
#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
/* CM_DSS_DSS_CLKCTRL */
#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8)
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
/* Clock frequencies */
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
/* PMIC */
#define SMPS_I2C_SLAVE_ADDR 0x12
/* TWL6030 SMPS */
#define SMPS_REG_ADDR_VCORE1 0x55
#define SMPS_REG_ADDR_VCORE2 0x5B
#define SMPS_REG_ADDR_VCORE3 0x61
/* TWL6032 SMPS */
#define SMPS_REG_ADDR_SMPS1 0x55
#define SMPS_REG_ADDR_SMPS2 0x5B
#define SMPS_REG_ADDR_SMPS5 0x49
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0
#define TPS62361_REG_ADDR_SET1 0x1
#define TPS62361_REG_ADDR_SET2 0x2
#define TPS62361_REG_ADDR_SET3 0x3
#define TPS62361_REG_ADDR_CTRL 0x4
#define TPS62361_REG_ADDR_TEMP 0x5
#define TPS62361_REG_ADDR_RMP_CTRL 0x6
#define TPS62361_REG_ADDR_CHIP_ID 0x8
#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
#define TPS62361_BASE_VOLT_MV 500
#define TPS62361_VSEL0_GPIO 7
/* AUXCLKx reg fields */
#define AUXCLK_ENABLE_MASK (1 << 8)
#define AUXCLK_SRCSELECT_SHIFT 1
#define AUXCLK_SRCSELECT_MASK (3 << 1)
#define AUXCLK_CLKDIV_SHIFT 16
#define AUXCLK_CLKDIV_MASK (0xF << 16)
#define AUXCLK_SRCSELECT_SYS_CLK 0
#define AUXCLK_SRCSELECT_CORE_DPLL 1
#define AUXCLK_SRCSELECT_PER_DPLL 2
#define AUXCLK_SRCSELECT_ALTERNATE 3
#define AUXCLK_CLKDIV_2 1
#define AUXCLK_CLKDIV_16 0xF
/* ALTCLKSRC */
#define ALTCLKSRC_MODE_MASK 3
#define ALTCLKSRC_ENABLE_INT_MASK 4
#define ALTCLKSRC_ENABLE_EXT_MASK 8
#define ALTCLKSRC_MODE_ACTIVE 1
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */
#define V_SCLK V_OSCK
struct omap4_scrm_regs {
u32 revision; /* 0x0000 */
u32 pad00[63];
u32 clksetuptime; /* 0x0100 */
u32 pmicsetuptime; /* 0x0104 */
u32 pad01[2];
u32 altclksrc; /* 0x0110 */
u32 pad02[2];
u32 c2cclkm; /* 0x011c */
u32 pad03[56];
u32 extclkreq; /* 0x0200 */
u32 accclkreq; /* 0x0204 */
u32 pwrreq; /* 0x0208 */
u32 pad04[1];
u32 auxclkreq0; /* 0x0210 */
u32 auxclkreq1; /* 0x0214 */
u32 auxclkreq2; /* 0x0218 */
u32 auxclkreq3; /* 0x021c */
u32 auxclkreq4; /* 0x0220 */
u32 auxclkreq5; /* 0x0224 */
u32 pad05[3];
u32 c2cclkreq; /* 0x0234 */
u32 pad06[54];
u32 auxclk0; /* 0x0310 */
u32 auxclk1; /* 0x0314 */
u32 auxclk2; /* 0x0318 */
u32 auxclk3; /* 0x031c */
u32 auxclk4; /* 0x0320 */
u32 auxclk5; /* 0x0324 */
u32 pad07[54];
u32 rsttime_reg; /* 0x0400 */
u32 pad08[6];
u32 c2crstctrl; /* 0x041c */
u32 extpwronrstctrl; /* 0x0420 */
u32 pad09[59];
u32 extwarmrstst_reg; /* 0x0510 */
u32 apewarmrstst_reg; /* 0x0514 */
u32 pad10[1];
u32 c2cwarmrstst_reg; /* 0x051C */
};
#endif /* _CLOCKS_OMAP4_H_ */

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arch/arm/include/asm/arch-omap4/cpu.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006-2010
* Texas Instruments, <www.ti.com>
*/
#ifndef _CPU_H
#define _CPU_H
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
#include <asm/arch/hardware.h>
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res[0xc];
u32 tiocp_cfg; /* 0x10 rw */
u32 tistat; /* 0x14 r */
u32 tisr; /* 0x18 rw */
u32 tier; /* 0x1c rw */
u32 twer; /* 0x20 rw */
u32 tclr; /* 0x24 rw */
u32 tcrr; /* 0x28 rw */
u32 tldr; /* 0x2c rw */
u32 ttgr; /* 0x30 rw */
u32 twpc; /* 0x34 r */
u32 tmar; /* 0x38 rw */
u32 tcar1; /* 0x3c r */
u32 tcicr; /* 0x40 rw */
u32 tcar2; /* 0x44 r */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
/* enable sys_clk NO-prescale /1 */
#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
/* Watchdog */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct watchdog {
u8 res1[0x34];
u32 wwps; /* 0x34 r */
u8 res2[0x10];
u32 wspr; /* 0x48 rw */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
#define TCLR_ST (0x1 << 0)
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
/* I2C base */
#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000)
/* MUSB base */
#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000)
/* OMAP4 GPIO registers */
#define OMAP_GPIO_REVISION 0x0000
#define OMAP_GPIO_SYSCONFIG 0x0010
#define OMAP_GPIO_SYSSTATUS 0x0114
#define OMAP_GPIO_IRQSTATUS1 0x0118
#define OMAP_GPIO_IRQSTATUS2 0x0128
#define OMAP_GPIO_IRQENABLE2 0x012c
#define OMAP_GPIO_IRQENABLE1 0x011c
#define OMAP_GPIO_WAKE_EN 0x0120
#define OMAP_GPIO_CTRL 0x0130
#define OMAP_GPIO_OE 0x0134
#define OMAP_GPIO_DATAIN 0x0138
#define OMAP_GPIO_DATAOUT 0x013c
#define OMAP_GPIO_LEVELDETECT0 0x0140
#define OMAP_GPIO_LEVELDETECT1 0x0144
#define OMAP_GPIO_RISINGDETECT 0x0148
#define OMAP_GPIO_FALLINGDETECT 0x014c
#define OMAP_GPIO_DEBOUNCE_EN 0x0150
#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
#define OMAP_GPIO_SETIRQENABLE1 0x0164
#define OMAP_GPIO_CLEARWKUENA 0x0180
#define OMAP_GPIO_SETWKUENA 0x0184
#define OMAP_GPIO_CLEARDATAOUT 0x0190
#define OMAP_GPIO_SETDATAOUT 0x0194
/*
* PRCM
*/
/* PRM */
#define PRM_BASE 0x4A306000
#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
#define PRM_RSTST_WARM_RESET_MASK 0x07EA
#endif /* _CPU_H */

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arch/arm/include/asm/arch-omap4/ehci.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* OMAP EHCI port support
* Based on LINUX KERNEL
* drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*/
#ifndef _OMAP4_EHCI_H_
#define _OMAP4_EHCI_H_
#define OMAP_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00)
#define OMAP_UHH_BASE (OMAP44XX_L4_CORE_BASE + 0x64000)
#define OMAP_USBTLL_BASE (OMAP44XX_L4_CORE_BASE + 0x62000)
/* UHH, TLL and opt clocks */
#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL
#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK (1 << 24)
/* TLL Register Set */
#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1
#define OMAP_UHH_SYSCONFIG_SOFTRESET 1
#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2)
#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2)
#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4)
#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \
OMAP_UHH_SYSCONFIG_NOSTDBY)
#endif /* _OMAP4_EHCI_H_ */

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arch/arm/include/asm/arch-omap4/gpio.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This work is derived from the linux 2.6.27 kernel source
* To fetch, use the kernel repository
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
* Use the v2.6.27 tag.
*
* Below is the original's header including its copyright
*
* linux/arch/arm/plat-omap/gpio.c
*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*/
#ifndef _GPIO_OMAP4_H
#define _GPIO_OMAP4_H
#include <asm/omap_gpio.h>
#define OMAP_MAX_GPIO 192
#define OMAP44XX_GPIO1_BASE 0x4A310000
#define OMAP44XX_GPIO2_BASE 0x48055000
#define OMAP44XX_GPIO3_BASE 0x48057000
#define OMAP44XX_GPIO4_BASE 0x48059000
#define OMAP44XX_GPIO5_BASE 0x4805B000
#define OMAP44XX_GPIO6_BASE 0x4805D000
#endif /* _GPIO_OMAP4_H */

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arch/arm/include/asm/arch-omap4/hardware.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* hardware.h
*
* hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_HARDWARE_H
#define __OMAP_HARDWARE_H
#include <asm/arch/omap.h>
/*
* Common hardware definitions
*/
/* BCH Error Location Module */
#define ELM_BASE 0x48078000
/* GPMC Base address */
#define GPMC_BASE 0x50000000
#endif

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arch/arm/include/asm/arch-omap4/i2c.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2004-2010
* Texas Instruments, <www.ti.com>
*/
#ifndef _OMAP4_I2C_H_
#define _OMAP4_I2C_H_
#define I2C_DEFAULT_BASE I2C_BASE1
#endif /* _OMAP4_I2C_H_ */

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arch/arm/include/asm/arch-omap4/mem.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
*
* Author
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* Initial Code from:
* Richard Woodruff <r-woodruff2@ti.com>
*/
#ifndef _MEM_H_
#define _MEM_H_
/*
* GPMC settings -
* Definitions is as per the following format
* #define <PART>_GPMC_CONFIG<x> <value>
* Where:
* PART is the part name e.g. STNOR - Intel Strata Flash
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
* Value is corresponding value
*
* For every valid PRCM configuration there should be only one definition of
* the same. if values are independent of the board, this definition will be
* present in this file if values are dependent on the board, then this should
* go into corresponding mem-boardName.h file
*
* Currently valid part Names are (PART):
* M_NAND - Micron NAND
* STNOR - STMicrolelctronics M29W128GL
*/
#define GPMC_SIZE_256M 0x0
#define GPMC_SIZE_128M 0x8
#define GPMC_SIZE_64M 0xC
#define GPMC_SIZE_32M 0xE
#define GPMC_SIZE_16M 0xF
#define M_NAND_GPMC_CONFIG1 0x00000800
#define M_NAND_GPMC_CONFIG2 0x001e1e00
#define M_NAND_GPMC_CONFIG3 0x001e1e00
#define M_NAND_GPMC_CONFIG4 0x16051807
#define M_NAND_GPMC_CONFIG5 0x00151e1e
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008
#define STNOR_GPMC_CONFIG1 0x00001200
#define STNOR_GPMC_CONFIG2 0x00101000
#define STNOR_GPMC_CONFIG3 0x00030301
#define STNOR_GPMC_CONFIG4 0x10041004
#define STNOR_GPMC_CONFIG5 0x000C1010
#define STNOR_GPMC_CONFIG6 0x08070280
#define STNOR_GPMC_CONFIG7 0x00000F48
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#endif /* endif _MEM_H_ */

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arch/arm/include/asm/arch-omap4/mmc_host_def.h
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/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
#include <asm/omap_mmc.h>
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x4809C000
#define OMAP_HSMMC2_BASE 0x480B4000
#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */

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arch/arm/include/asm/arch-omap4/mux_omap4.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2004-2009
* Texas Instruments Incorporated
* Richard Woodruff <r-woodruff2@ti.com>
* Aneesh V <aneesh@ti.com>
* Balaji Krishnamoorthy <balajitk@ti.com>
*/
#ifndef _MUX_OMAP4_H_
#define _MUX_OMAP4_H_
#include <asm/types.h>
struct pad_conf_entry {
u16 offset;
u16 val;
};
#ifdef CONFIG_OFF_PADCONF
#define OFF_PD (1 << 12)
#define OFF_PU (3 << 12)
#define OFF_OUT_PTD (0 << 10)
#define OFF_OUT_PTU (2 << 10)
#define OFF_IN (1 << 10)
#define OFF_OUT (0 << 10)
#define OFF_EN (1 << 9)
#else
#define OFF_PD (0 << 12)
#define OFF_PU (0 << 12)
#define OFF_OUT_PTD (0 << 10)
#define OFF_OUT_PTU (0 << 10)
#define OFF_IN (0 << 10)
#define OFF_OUT (0 << 10)
#define OFF_EN (0 << 9)
#endif
#define IEN (1 << 8)
#define IDIS (0 << 8)
#define PTU (3 << 3)
#define PTD (1 << 3)
#define EN (1 << 3)
#define DIS (0 << 3)
#define M0 0
#define M1 1
#define M2 2
#define M3 3
#define M4 4
#define M5 5
#define M6 6
#define M7 7
#define SAFE_MODE M7
#ifdef CONFIG_OFF_PADCONF
#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
#else
#define OFF_IN_PD 0
#define OFF_IN_PU 0
#define OFF_OUT_PD 0
#define OFF_OUT_PU 0
#endif
#define CORE_REVISION 0x0000
#define CORE_HWINFO 0x0004
#define CORE_SYSCONFIG 0x0010
#define GPMC_AD0 0x0040
#define GPMC_AD1 0x0042
#define GPMC_AD2 0x0044
#define GPMC_AD3 0x0046
#define GPMC_AD4 0x0048
#define GPMC_AD5 0x004A
#define GPMC_AD6 0x004C
#define GPMC_AD7 0x004E
#define GPMC_AD8 0x0050
#define GPMC_AD9 0x0052
#define GPMC_AD10 0x0054
#define GPMC_AD11 0x0056
#define GPMC_AD12 0x0058
#define GPMC_AD13 0x005A
#define GPMC_AD14 0x005C
#define GPMC_AD15 0x005E
#define GPMC_A16 0x0060
#define GPMC_A17 0x0062
#define GPMC_A18 0x0064
#define GPMC_A19 0x0066
#define GPMC_A20 0x0068
#define GPMC_A21 0x006A
#define GPMC_A22 0x006C
#define GPMC_A23 0x006E
#define GPMC_A24 0x0070
#define GPMC_A25 0x0072
#define GPMC_NCS0 0x0074
#define GPMC_NCS1 0x0076
#define GPMC_NCS2 0x0078
#define GPMC_NCS3 0x007A
#define GPMC_NWP 0x007C
#define GPMC_CLK 0x007E
#define GPMC_NADV_ALE 0x0080
#define GPMC_NOE 0x0082
#define GPMC_NWE 0x0084
#define GPMC_NBE0_CLE 0x0086
#define GPMC_NBE1 0x0088
#define GPMC_WAIT0 0x008A
#define GPMC_WAIT1 0x008C
#define C2C_DATA11 0x008E
#define C2C_DATA12 0x0090
#define C2C_DATA13 0x0092
#define C2C_DATA14 0x0094
#define C2C_DATA15 0x0096
#define HDMI_HPD 0x0098
#define HDMI_CEC 0x009A
#define HDMI_DDC_SCL 0x009C
#define HDMI_DDC_SDA 0x009E
#define CSI21_DX0 0x00A0
#define CSI21_DY0 0x00A2
#define CSI21_DX1 0x00A4
#define CSI21_DY1 0x00A6
#define CSI21_DX2 0x00A8
#define CSI21_DY2 0x00AA
#define CSI21_DX3 0x00AC
#define CSI21_DY3 0x00AE
#define CSI21_DX4 0x00B0
#define CSI21_DY4 0x00B2
#define CSI22_DX0 0x00B4
#define CSI22_DY0 0x00B6
#define CSI22_DX1 0x00B8
#define CSI22_DY1 0x00BA
#define CAM_SHUTTER 0x00BC
#define CAM_STROBE 0x00BE
#define CAM_GLOBALRESET 0x00C0
#define USBB1_ULPITLL_CLK 0x00C2
#define USBB1_ULPITLL_STP 0x00C4
#define USBB1_ULPITLL_DIR 0x00C6
#define USBB1_ULPITLL_NXT 0x00C8
#define USBB1_ULPITLL_DAT0 0x00CA
#define USBB1_ULPITLL_DAT1 0x00CC
#define USBB1_ULPITLL_DAT2 0x00CE
#define USBB1_ULPITLL_DAT3 0x00D0
#define USBB1_ULPITLL_DAT4 0x00D2
#define USBB1_ULPITLL_DAT5 0x00D4
#define USBB1_ULPITLL_DAT6 0x00D6
#define USBB1_ULPITLL_DAT7 0x00D8
#define USBB1_HSIC_DATA 0x00DA
#define USBB1_HSIC_STROBE 0x00DC
#define USBC1_ICUSB_DP 0x00DE
#define USBC1_ICUSB_DM 0x00E0
#define SDMMC1_CLK 0x00E2
#define SDMMC1_CMD 0x00E4
#define SDMMC1_DAT0 0x00E6
#define SDMMC1_DAT1 0x00E8
#define SDMMC1_DAT2 0x00EA
#define SDMMC1_DAT3 0x00EC
#define SDMMC1_DAT4 0x00EE
#define SDMMC1_DAT5 0x00F0
#define SDMMC1_DAT6 0x00F2
#define SDMMC1_DAT7 0x00F4
#define ABE_MCBSP2_CLKX 0x00F6
#define ABE_MCBSP2_DR 0x00F8
#define ABE_MCBSP2_DX 0x00FA
#define ABE_MCBSP2_FSX 0x00FC
#define ABE_MCBSP1_CLKX 0x00FE
#define ABE_MCBSP1_DR 0x0100
#define ABE_MCBSP1_DX 0x0102
#define ABE_MCBSP1_FSX 0x0104
#define ABE_PDM_UL_DATA 0x0106
#define ABE_PDM_DL_DATA 0x0108
#define ABE_PDM_FRAME 0x010A
#define ABE_PDM_LB_CLK 0x010C
#define ABE_CLKS 0x010E
#define ABE_DMIC_CLK1 0x0110
#define ABE_DMIC_DIN1 0x0112
#define ABE_DMIC_DIN2 0x0114
#define ABE_DMIC_DIN3 0x0116
#define UART2_CTS 0x0118
#define UART2_RTS 0x011A
#define UART2_RX 0x011C
#define UART2_TX 0x011E
#define HDQ_SIO 0x0120
#define I2C1_SCL 0x0122
#define I2C1_SDA 0x0124
#define I2C2_SCL 0x0126
#define I2C2_SDA 0x0128
#define I2C3_SCL 0x012A
#define I2C3_SDA 0x012C
#define I2C4_SCL 0x012E
#define I2C4_SDA 0x0130
#define MCSPI1_CLK 0x0132
#define MCSPI1_SOMI 0x0134
#define MCSPI1_SIMO 0x0136
#define MCSPI1_CS0 0x0138
#define MCSPI1_CS1 0x013A
#define MCSPI1_CS2 0x013C
#define MCSPI1_CS3 0x013E
#define UART3_CTS_RCTX 0x0140
#define UART3_RTS_SD 0x0142
#define UART3_RX_IRRX 0x0144
#define UART3_TX_IRTX 0x0146
#define SDMMC5_CLK 0x0148
#define SDMMC5_CMD 0x014A
#define SDMMC5_DAT0 0x014C
#define SDMMC5_DAT1 0x014E
#define SDMMC5_DAT2 0x0150
#define SDMMC5_DAT3 0x0152
#define MCSPI4_CLK 0x0154
#define MCSPI4_SIMO 0x0156
#define MCSPI4_SOMI 0x0158
#define MCSPI4_CS0 0x015A
#define UART4_RX 0x015C
#define UART4_TX 0x015E
#define USBB2_ULPITLL_CLK 0x0160
#define USBB2_ULPITLL_STP 0x0162
#define USBB2_ULPITLL_DIR 0x0164
#define USBB2_ULPITLL_NXT 0x0166
#define USBB2_ULPITLL_DAT0 0x0168
#define USBB2_ULPITLL_DAT1 0x016A
#define USBB2_ULPITLL_DAT2 0x016C
#define USBB2_ULPITLL_DAT3 0x016E
#define USBB2_ULPITLL_DAT4 0x0170
#define USBB2_ULPITLL_DAT5 0x0172
#define USBB2_ULPITLL_DAT6 0x0174
#define USBB2_ULPITLL_DAT7 0x0176
#define USBB2_HSIC_DATA 0x0178
#define USBB2_HSIC_STROBE 0x017A
#define UNIPRO_TX0 0x017C
#define UNIPRO_TY0 0x017E
#define UNIPRO_TX1 0x0180
#define UNIPRO_TY1 0x0182
#define UNIPRO_TX2 0x0184
#define UNIPRO_TY2 0x0186
#define UNIPRO_RX0 0x0188
#define UNIPRO_RY0 0x018A
#define UNIPRO_RX1 0x018C
#define UNIPRO_RY1 0x018E
#define UNIPRO_RX2 0x0190
#define UNIPRO_RY2 0x0192
#define USBA0_OTG_CE 0x0194
#define USBA0_OTG_DP 0x0196
#define USBA0_OTG_DM 0x0198
#define FREF_CLK1_OUT 0x019A
#define FREF_CLK2_OUT 0x019C
#define SYS_NIRQ1 0x019E
#define SYS_NIRQ2 0x01A0
#define SYS_BOOT0 0x01A2
#define SYS_BOOT1 0x01A4
#define SYS_BOOT2 0x01A6
#define SYS_BOOT3 0x01A8
#define SYS_BOOT4 0x01AA
#define SYS_BOOT5 0x01AC
#define DPM_EMU0 0x01AE
#define DPM_EMU1 0x01B0
#define DPM_EMU2 0x01B2
#define DPM_EMU3 0x01B4
#define DPM_EMU4 0x01B6
#define DPM_EMU5 0x01B8
#define DPM_EMU6 0x01BA
#define DPM_EMU7 0x01BC
#define DPM_EMU8 0x01BE
#define DPM_EMU9 0x01C0
#define DPM_EMU10 0x01C2
#define DPM_EMU11 0x01C4
#define DPM_EMU12 0x01C6
#define DPM_EMU13 0x01C8
#define DPM_EMU14 0x01CA
#define DPM_EMU15 0x01CC
#define DPM_EMU16 0x01CE
#define DPM_EMU17 0x01D0
#define DPM_EMU18 0x01D2
#define DPM_EMU19 0x01D4
#define WAKEUPEVENT_0 0x01D8
#define WAKEUPEVENT_1 0x01DC
#define WAKEUPEVENT_2 0x01E0
#define WAKEUPEVENT_3 0x01E4
#define WAKEUPEVENT_4 0x01E8
#define WAKEUPEVENT_5 0x01EC
#define WAKEUPEVENT_6 0x01F0
#define WKUP_REVISION 0x0000
#define WKUP_HWINFO 0x0004
#define WKUP_SYSCONFIG 0x0010
#define PAD0_SIM_IO 0x0040
#define PAD1_SIM_CLK 0x0042
#define PAD0_SIM_RESET 0x0044
#define PAD1_SIM_CD 0x0046
#define PAD0_SIM_PWRCTRL 0x0048
#define PAD1_SR_SCL 0x004A
#define PAD0_SR_SDA 0x004C
#define PAD1_FREF_XTAL_IN 0x004E
#define PAD0_FREF_SLICER_IN 0x0050
#define PAD1_FREF_CLK_IOREQ 0x0052
#define PAD0_FREF_CLK0_OUT 0x0054
#define PAD1_FREF_CLK3_REQ 0x0056
#define PAD0_FREF_CLK3_OUT 0x0058
#define PAD1_FREF_CLK4_REQ 0x005A
#define PAD0_FREF_CLK4_OUT 0x005C
#define PAD1_SYS_32K 0x005E
#define PAD0_SYS_NRESPWRON 0x0060
#define PAD1_SYS_NRESWARM 0x0062
#define PAD0_SYS_PWR_REQ 0x0064
#define PAD1_SYS_PWRON_RESET 0x0066
#define PAD0_SYS_BOOT6 0x0068
#define PAD1_SYS_BOOT7 0x006A
#define PAD0_JTAG_NTRST 0x006C
#define PAD1_JTAG_TCK 0x006D
#define PAD0_JTAG_RTCK 0x0070
#define PAD1_JTAG_TMS_TMSC 0x0072
#define PAD0_JTAG_TDI 0x0074
#define PAD1_JTAG_TDO 0x0076
#define PADCONF_WAKEUPEVENT_0 0x007C
#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0
#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4
#define PADCONF_MODE 0x05A8
#define CONTROL_XTAL_OSCILLATOR 0x05AC
#define CONTROL_CONTROL_I2C_2 0x0604
#define CONTROL_CONTROL_JTAG 0x0608
#define CONTROL_CONTROL_SYS 0x060C
#define CONTROL_SPARE_RW 0x0614
#define CONTROL_SPARE_R 0x0618
#define CONTROL_SPARE_R_C0 0x061C
#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A
#endif /* _MUX_OMAP4_H_ */

143
arch/arm/include/asm/arch-omap4/omap.h
View File

@ -1,143 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Authors:
* Aneesh V <aneesh@ti.com>
*
* Derived from OMAP3 work by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*/
#ifndef _OMAP4_H_
#define _OMAP4_H_
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
#include <linux/sizes.h>
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
#define OMAP44XX_L4_CORE_BASE 0x4A000000
#define OMAP44XX_L4_WKUP_BASE 0x4A300000
#define OMAP44XX_L4_PER_BASE 0x48000000
#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
/* General Purpose Timers */
#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
/*
* Hardware Register Details
*/
/* Watchdog Timer */
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
/* GP Timer */
#define TCLR_ST (0x1 << 0)
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
/* Control Module */
#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
#define CONTROL_EFUSE_2_OVERRIDE 0x99084000
/* LPDDR2 IO regs */
#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
#define LPDDR2IO_GR10_WD_MASK (3 << 17)
#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
#define MMC1_PWRDNZ (1 << 26)
#define MMC1_PBIASLITE_PWRDNZ (1 << 22)
#define MMC1_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__
struct s32ktimer {
unsigned char res[0x10];
unsigned int s32k_cr; /* 0x10 */
};
#define DEVICE_TYPE_SHIFT (0x8)
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#endif /* __ASSEMBLY__ */
/*
* Non-secure SRAM Addresses
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
* at 0x40304000(EMU base) so that our code works for both EMU and GP
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
#define NON_SECURE_SRAM_IMG_END 0x4030C000
#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
/* ABB settings */
#define OMAP_ABB_SETTLING_TIME 50
#define OMAP_ABB_CLOCK_CYCLES 16
/* ABB tranxdone mask */
#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
#define OMAP44XX_SAR_RAM_BASE 0x4a326000
#define OMAP_REBOOT_REASON_OFFSET 0xA0C
#define OMAP_REBOOT_REASON_SIZE 0x0F
/* Boot parameters */
#ifndef __ASSEMBLY__
struct omap_boot_parameters {
unsigned int boot_message;
unsigned int boot_device_descriptor;
unsigned char boot_device;
unsigned char reset_reason;
unsigned char ch_flags;
};
int omap_reboot_mode(char *mode, unsigned int length);
int omap_reboot_mode_clear(void);
int omap_reboot_mode_store(char *mode);
#endif
#endif

22
arch/arm/include/asm/arch-omap4/spl.h
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@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012
* Texas Instruments, <www.ti.com>
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NONE 0x00
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x03
#define BOOT_DEVICE_ONENAND 0x04
#define BOOT_DEVICE_MMC1 0x05
#define BOOT_DEVICE_MMC2 0x06
#define BOOT_DEVICE_MMC2_2 0x07
#define BOOT_DEVICE_UART 0x43
#define BOOT_DEVICE_USB 0x45
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
#endif

71
arch/arm/include/asm/arch-omap4/sys_proto.h
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@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/arch/omap.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/omap_common.h>
#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/mux_omap4.h>
#include <asm/ti-common/sys_proto.h>
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2;
extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2;
extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2;
#else
extern const struct lpddr2_device_details elpida_2G_S4_details;
extern const struct lpddr2_device_details elpida_4G_S4_details;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
extern const struct lpddr2_device_timings jedec_default_timings;
#else
extern const struct lpddr2_device_timings elpida_2G_S4_timings;
#endif
struct omap_sysinfo {
char *board_string;
};
extern const struct omap_sysinfo sysinfo;
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs(void);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void setup_early_clocks(void);
void prcm_init(void);
void do_board_detect(void);
void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap4_ddr_clk(void);
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdram_init(void);
u32 omap_sdram_size(void);
u32 cortex_rev(void);
void save_omap_boot_params(void);
void init_omap_revision(void);
void do_io_settings(void);
void sri2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
void setup_warmreset_time(void);
#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102
#endif

16
arch/arm/include/asm/omap_common.h
View File

@ -490,7 +490,7 @@ struct omap_sys_ctrl_regs {
u32 ctrl_core_sma_sw_1; u32 ctrl_core_sma_sw_1;
}; };
#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) #if defined(CONFIG_OMAP54XX)
struct dpll_params { struct dpll_params {
u32 m; u32 m;
u32 n; u32 n;
@ -523,7 +523,7 @@ struct dpll_regs {
u32 cm_div_h23_dpll; u32 cm_div_h23_dpll;
u32 cm_div_h24_dpll; u32 cm_div_h24_dpll;
}; };
#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ #endif /* CONFIG_OMAP54XX */
struct dplls { struct dplls {
const struct dpll_params *mpu; const struct dpll_params *mpu;
@ -547,7 +547,7 @@ struct pmic_data {
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
}; };
#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) #if defined(CONFIG_OMAP54XX)
enum { enum {
OPP_LOW, OPP_LOW,
OPP_NOM, OPP_NOM,
@ -593,7 +593,7 @@ struct vcores_data {
struct volts eve; struct volts eve;
struct volts iva; struct volts iva;
}; };
#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ #endif /* CONFIG_OMAP54XX */
extern struct prcm_regs const **prcm; extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap5_es1_prcm;
@ -626,7 +626,7 @@ const struct dpll_params *get_iva_dpll_params(struct dplls const *);
const struct dpll_params *get_usb_dpll_params(struct dplls const *); const struct dpll_params *get_usb_dpll_params(struct dplls const *);
const struct dpll_params *get_abe_dpll_params(struct dplls const *); const struct dpll_params *get_abe_dpll_params(struct dplls const *);
#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) #if defined(CONFIG_OMAP54XX)
void do_enable_clocks(u32 const *clk_domains, void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto, u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en, u32 const *clk_modules_explicit_en,
@ -635,7 +635,7 @@ void do_enable_clocks(u32 const *clk_domains,
void do_disable_clocks(u32 const *clk_domains, void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable, u32 const *clk_modules_disable,
u8 wait_for_disable); u8 wait_for_disable);
#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ #endif /* CONFIG_OMAP54XX */
void do_enable_ipu_clocks(u32 const *clk_domains, void do_enable_ipu_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto, u32 const *clk_modules_hw_auto,
@ -653,9 +653,9 @@ void enable_basic_uboot_clocks(void);
void enable_usb_clocks(int index); void enable_usb_clocks(int index);
void disable_usb_clocks(int index); void disable_usb_clocks(int index);
#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) #if defined(CONFIG_OMAP54XX)
void scale_vcores(struct vcores_data const *); void scale_vcores(struct vcores_data const *);
#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ #endif /* CONFIG_OMAP54XX */
int get_voltrail_opp(int rail_offset); int get_voltrail_opp(int rail_offset);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);

4
arch/arm/mach-lpc32xx/Kconfig
View File

@ -6,9 +6,6 @@ config SYS_SOC
choice choice
prompt "NXP LPC32xx board select" prompt "NXP LPC32xx board select"
config TARGET_DEVKIT3250
bool "Timll DevKit3250"
config TARGET_WORK_92105 config TARGET_WORK_92105
bool "Work Microwave Work_92105" bool "Work Microwave Work_92105"
@ -17,7 +14,6 @@ config TARGET_EA_LPC3250DEVKITV2
endchoice endchoice
source "board/timll/devkit3250/Kconfig"
source "board/work-microwave/work_92105/Kconfig" source "board/work-microwave/work_92105/Kconfig"
source "board/ea/ea-lpc3250devkitv2/Kconfig" source "board/ea/ea-lpc3250devkitv2/Kconfig"

27
arch/arm/mach-omap2/Kconfig
View File

@ -29,29 +29,6 @@ config OMAP34XX
imply SYS_THUMB_BUILD imply SYS_THUMB_BUILD
imply TWL4030_POWER imply TWL4030_POWER
config OMAP44XX
bool "OMAP44XX SoC"
select DM_EVENT
select SPL_USE_TINY_PRINTF
select SPL_SYS_NO_VECTOR_TABLE if SPL
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DISPLAY_PRINT
imply SPL_FS_EXT4
imply SPL_FS_FAT
imply SPL_GPIO
imply SPL_I2C
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC
imply SPL_NAND_SIMPLE
imply SPL_NAND_SUPPORT
imply SPL_POWER
imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
imply SYS_THUMB_BUILD
config OMAP54XX config OMAP54XX
bool "OMAP54XX SoC" bool "OMAP54XX SoC"
select ARM_CORTEX_A15_CVE_2017_5715 select ARM_CORTEX_A15_CVE_2017_5715
@ -162,7 +139,7 @@ config SYS_AUTOMATIC_SDRAM_DETECTION
bool bool
choice choice
depends on OMAP44XX || OMAP54XX depends on OMAP54XX
prompt "Static or dynamic DDR timing calculations" prompt "Static or dynamic DDR timing calculations"
default SYS_EMIF_PRECALCULATED_TIMING_REGS default SYS_EMIF_PRECALCULATED_TIMING_REGS
help help
@ -181,8 +158,6 @@ endchoice
source "arch/arm/mach-omap2/omap3/Kconfig" source "arch/arm/mach-omap2/omap3/Kconfig"
source "arch/arm/mach-omap2/omap4/Kconfig"
source "arch/arm/mach-omap2/omap5/Kconfig" source "arch/arm/mach-omap2/omap5/Kconfig"
source "arch/arm/mach-omap2/am33xx/Kconfig" source "arch/arm/mach-omap2/am33xx/Kconfig"

3
arch/arm/mach-omap2/Makefile
View File

@ -5,7 +5,6 @@
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(CONFIG_OMAP34XX) += omap3/ obj-$(CONFIG_OMAP34XX) += omap3/
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/ obj-$(CONFIG_OMAP54XX) += omap5/
obj-y += reset.o obj-y += reset.o
@ -19,7 +18,7 @@ endif
obj-y += utils.o obj-y += utils.o
obj-y += sysinfo-common.o obj-y += sysinfo-common.o
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) ifdef CONFIG_OMAP54XX
obj-y += hwinit-common.o obj-y += hwinit-common.o
obj-y += clocks-common.o obj-y += clocks-common.o
obj-y += emif-common.o obj-y += emif-common.o

4
arch/arm/mach-omap2/emif-common.c
View File

@ -202,7 +202,6 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
} }
} }
#ifndef CONFIG_OMAP44XX
static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
{ {
struct emif_reg_struct *emif = (struct emif_reg_struct *)base; struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@ -510,7 +509,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
else else
dra7_ddr3_init(base, regs); dra7_ddr3_init(base, regs);
} }
#endif
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
@ -1292,10 +1290,8 @@ static void do_sdram_init(u32 base)
if (emif_sdram_type(regs->sdram_config) == if (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_LPDDR2) EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs); lpddr2_init(base, regs);
#ifndef CONFIG_OMAP44XX
else else
ddr3_init(base, regs); ddr3_init(base, regs);
#endif
} }
#ifdef CONFIG_OMAP54XX #ifdef CONFIG_OMAP54XX
if (warm_reset() && (emif_sdram_type(regs->sdram_config) == if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==

10
arch/arm/mach-omap2/omap3/Kconfig
View File

@ -34,15 +34,6 @@ config TARGET_AM3517_EVM
select DM_SERIAL select DM_SERIAL
imply CMD_DM imply CMD_DM
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select DM
select DM_GPIO
select DM_SERIAL
select OMAP3_GPIO_5
select OMAP3_GPIO_6
imply CMD_DM
config TARGET_CM_T35 config TARGET_CM_T35
bool "CompuLab CM-T3530 and CM-T3730 boards" bool "CompuLab CM-T3530 and CM-T3730 boards"
select OMAP3_GPIO_2 select OMAP3_GPIO_2
@ -153,7 +144,6 @@ config SYS_SOC
default "omap3" default "omap3"
source "board/logicpd/am3517evm/Kconfig" source "board/logicpd/am3517evm/Kconfig"
source "board/beagle/beagle/Kconfig"
source "board/timll/devkit8000/Kconfig" source "board/timll/devkit8000/Kconfig"
source "board/ti/omap3evm/Kconfig" source "board/ti/omap3evm/Kconfig"
source "board/isee/igep00x0/Kconfig" source "board/isee/igep00x0/Kconfig"

21
arch/arm/mach-omap2/omap4/Kconfig
View File

@ -1,21 +0,0 @@
if OMAP44XX
choice
prompt "OMAP4 board select"
optional
config TARGET_OMAP4_PANDA
bool "TI OMAP4 PandaBoard"
config TARGET_OMAP4_SDP4430
bool "TI OMAP4 SDP4430"
endchoice
config SYS_SOC
default "omap4"
source "board/ti/panda/Kconfig"
source "board/ti/sdp4430/Kconfig"
endif

11
arch/arm/mach-omap2/omap4/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += boot.o
obj-y += sdram_elpida.o
obj-y += hwinit.o
obj-y += emif.o
obj-y += prcm-regs.o
obj-y += hw_data.o

103
arch/arm/mach-omap2/omap4/boot.c
View File

@ -1,103 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* OMAP4 boot
*
* Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
*/
#include <asm/io.h>
#include <asm/omap_common.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
static u32 boot_devices[] = {
BOOT_DEVICE_MMC2,
BOOT_DEVICE_XIP,
BOOT_DEVICE_XIPWAIT,
BOOT_DEVICE_NAND,
BOOT_DEVICE_XIPWAIT,
BOOT_DEVICE_MMC1,
BOOT_DEVICE_ONENAND,
BOOT_DEVICE_ONENAND,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_ONENAND,
BOOT_DEVICE_XIPWAIT,
BOOT_DEVICE_NAND,
BOOT_DEVICE_NAND,
BOOT_DEVICE_MMC1,
BOOT_DEVICE_ONENAND,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_XIP,
BOOT_DEVICE_XIPWAIT,
BOOT_DEVICE_NAND,
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC1,
BOOT_DEVICE_ONENAND,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_XIP,
BOOT_DEVICE_MMC2_2,
BOOT_DEVICE_NAND,
BOOT_DEVICE_MMC2_2,
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC2_2,
BOOT_DEVICE_MMC2_2,
BOOT_DEVICE_NONE,
BOOT_DEVICE_XIPWAIT,
};
u32 omap_sys_boot_device(void)
{
u32 sys_boot;
/* Grab the first 5 bits of the status register for SYS_BOOT. */
sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1);
if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
return BOOT_DEVICE_NONE;
return boot_devices[sys_boot];
}
int omap_reboot_mode(char *mode, unsigned int length)
{
unsigned int limit;
unsigned int i;
if (length < 2)
return -1;
if (!warm_reset())
return -1;
limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
OMAP_REBOOT_REASON_SIZE;
for (i = 0; i < (limit - 1); i++)
mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
OMAP_REBOOT_REASON_OFFSET + i));
mode[i] = '\0';
return 0;
}
int omap_reboot_mode_clear(void)
{
writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
return 0;
}
int omap_reboot_mode_store(char *mode)
{
unsigned int i;
for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
OMAP_REBOOT_REASON_OFFSET + i));
writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
OMAP_REBOOT_REASON_OFFSET + i));
return 0;
}

109
arch/arm/mach-omap2/omap4/emif.c
View File

@ -1,109 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* EMIF programming
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
*/
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
.max_freq = 400000000,
.RL = 6,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 15,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
.max_freq = 200000000,
.RL = 3,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 20,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
/*
* Min tCK values specified by JESD209-2
* Min tCK specifies the minimum duration of some AC timing parameters in terms
* of the number of cycles. If the calculated number of cycles based on the
* absolute time value is less than the min tCK value, min tCK value should
* be used instead. This typically happens at low frequencies.
*/
static const struct lpddr2_min_tck min_tck_jedec = {
.tRL = 3,
.tRP_AB = 3,
.tRCD = 3,
.tWR = 3,
.tRAS_MIN = 3,
.tRRD = 2,
.tWTR = 2,
.tXP = 2,
.tRTP = 2,
.tCKE = 3,
.tCKESR = 3,
.tFAW = 8
};
static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_jedec_200_mhz,
&timings_jedec_400_mhz
};
const struct lpddr2_device_timings jedec_default_timings = {
.ac_timings = jedec_ac_timings,
.min_tck = &min_tck_jedec
};
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
/* Assume Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &jedec_default_timings;
*cs1_device_timings = &jedec_default_timings;
}
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */

460
arch/arm/mach-omap2/omap4/hw_data.c
View File

@ -1,460 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* HW data initialization for OMAP4
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*/
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
/*
* The M & N values in the following tables are created using the
* following tool:
* tools/omap/clocks_get_m_n.c
* Please use this tool for creating the table for any new frequency.
*/
/*
* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
* OMAP4460 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/*
* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
* OMAP4430 OPP_TURBO frequency
* OMAP4470 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/*
* dpll locked at 1200 MHz - MPU clk at 600 MHz
* OMAP4430 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OMAP4460 OPP_NOM frequency */
/* OMAP4470 OPP_NOM (Low Power) frequency */
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OMAP4430 ES1 OPP_NOM frequency */
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OMAP4430 ES2.X OPP_NOM frequency */
static const struct dpll_params
core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
#else
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
#endif
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
struct dplls omap4430_dplls_es1 = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_es1_1524mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4430_dplls_es20 = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_es2_1600mhz_ddr200mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4430_dplls = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4460_dplls = {
.mpu = mpu_dpll_params_1400mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4470_dplls = {
.mpu = mpu_dpll_params_1600mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
.pmic_bus_init = sri2c_init,
.pmic_write = omap_vc_bypass_send_value,
};
/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
.pmic_bus_init = sri2c_init,
.pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data tps62361 = {
.base_offset = TPS62361_BASE_VOLT_MV,
.step = 10000, /* 10 mV represented in uV */
.start_code = 0,
.gpio = TPS62361_VSEL0_GPIO,
.gpio_en = 1,
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
.pmic_bus_init = sri2c_init,
.pmic_write = omap_vc_bypass_send_value,
};
struct vcores_data omap4430_volts_es1 = {
.mpu.value[OPP_NOM] = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030_4430es1,
.core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030_4430es1,
.mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030_4430es1,
};
struct vcores_data omap4430_volts = {
.mpu.value[OPP_NOM] = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030,
.core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030,
.mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
struct vcores_data omap4460_volts = {
.mpu.value[OPP_NOM] = 1203,
.mpu.addr = TPS62361_REG_ADDR_SET1,
.mpu.pmic = &tps62361,
.core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
.core.pmic = &twl6030,
.mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
/*
* Take closest integer part of the mV value corresponding to a TWL6032 SMPS
* voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
*/
struct vcores_data omap4470_volts = {
.mpu.value[OPP_NOM] = 1202,
.mpu.addr = SMPS_REG_ADDR_SMPS1,
.mpu.pmic = &twl6030,
.core.value[OPP_NOM] = 1126,
.core.addr = SMPS_REG_ADDR_SMPS2,
.core.pmic = &twl6030,
.mm.value[OPP_NOM] = 1139,
.mm.addr = SMPS_REG_ADDR_SMPS5,
.mm.pmic = &twl6030,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
/* Enable optional 48M functional clock for USB PHY */
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
/* Enable 32 KHz clock for USB PHY */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbotg_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_clksel_usb_60mhz,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
(*prcm) = &omap4_prcm;
switch (omap_rev) {
case OMAP4430_ES1_0:
*dplls_data = &omap4430_dplls_es1;
*omap_vcores = &omap4430_volts_es1;
break;
case OMAP4430_ES2_0:
*dplls_data = &omap4430_dplls_es20;
*omap_vcores = &omap4430_volts;
break;
case OMAP4430_ES2_1:
case OMAP4430_ES2_2:
case OMAP4430_ES2_3:
*dplls_data = &omap4430_dplls;
*omap_vcores = &omap4430_volts;
break;
case OMAP4460_ES1_0:
case OMAP4460_ES1_1:
*dplls_data = &omap4460_dplls;
*omap_vcores = &omap4460_volts;
break;
case OMAP4470_ES1_0:
*dplls_data = &omap4470_dplls;
*omap_vcores = &omap4470_volts;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
*ctrl = &omap4_ctrl;
}

186
arch/arm/mach-omap2/omap4/hwinit.c
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@ -1,186 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* Common functions for OMAP4 based boards
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*/
#include <palmas.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <linux/sizes.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
{ (void *)OMAP44XX_GPIO1_BASE },
{ (void *)OMAP44XX_GPIO2_BASE },
{ (void *)OMAP44XX_GPIO3_BASE },
{ (void *)OMAP44XX_GPIO4_BASE },
{ (void *)OMAP44XX_GPIO5_BASE },
{ (void *)OMAP44XX_GPIO6_BASE },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
#ifdef CONFIG_SPL_BUILD
/*
* Some tuning of IOs for optimal power and performance
*/
void do_io_settings(void)
{
u32 lpddr2io;
u32 omap4_rev = omap_revision();
if (omap4_rev == OMAP4430_ES1_0)
lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
else if (omap4_rev == OMAP4430_ES2_0)
lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
else
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
(*ctrl)->control_lpddr2io1_2);
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
/* EMIF2 */
writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
(*ctrl)->control_lpddr2io2_2);
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
* in turn programmed in the eFuse at manufacturing time after
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
(*ctrl)->control_ldosram_iva_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
(*ctrl)->control_ldosram_mpu_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
(*ctrl)->control_ldosram_core_voltage_ctrl);
}
/*
* Over-ride the register
* i. unconditionally for all 4430
* ii. only if un-trimmed for 4460
*/
if (!readl((*ctrl)->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
}
#endif /* CONFIG_SPL_BUILD */
/* dummy fuction for omap4 */
void config_data_eye_leveling_samples(u32 emif_base)
{
}
void init_omap_revision(void)
{
/*
* For some of the ES2/ES1 boards ID_CODE is not reliable:
* Also, ES1 and ES2 have different ARM revisions
* So use ARM revision for identification
*/
unsigned int arm_rev = cortex_rev();
switch (arm_rev) {
case MIDR_CORTEX_A9_R0P1:
*omap_si_rev = OMAP4430_ES1_0;
break;
case MIDR_CORTEX_A9_R1P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP4430_ES2_0;
break;
case OMAP4_CONTROL_ID_CODE_ES2_1:
*omap_si_rev = OMAP4430_ES2_1;
break;
case OMAP4_CONTROL_ID_CODE_ES2_2:
*omap_si_rev = OMAP4430_ES2_2;
break;
default:
*omap_si_rev = OMAP4430_ES2_0;
break;
}
break;
case MIDR_CORTEX_A9_R1P3:
*omap_si_rev = OMAP4430_ES2_3;
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4470_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP4470_ES1_0;
break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1;
break;
case OMAP4460_CONTROL_ID_CODE_ES1_0:
default:
*omap_si_rev = OMAP4460_ES1_0;
break;
}
break;
default:
*omap_si_rev = OMAP4430_SILICON_ID_INVALID;
break;
}
}
void omap_die_id(unsigned int *die_id)
{
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
}
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
}
void v7_outer_cache_disable(void)
{
omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
void vmmc_pbias_config(uint voltage)
{
u32 value = 0;
value = readl((*ctrl)->control_pbiaslite);
value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
writel(value, (*ctrl)->control_pbiaslite);
value = readl((*ctrl)->control_pbiaslite);
value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
writel(value, (*ctrl)->control_pbiaslite);
}

306
arch/arm/mach-omap2/omap4/prcm-regs.c
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@ -1,306 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* HW regs data for OMAP4
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*/
#include <asm/omap_common.h>
struct prcm_regs const omap4_prcm = {
/* cm1.ckgen */
.cm_clksel_core = 0x4a004100,
.cm_clksel_abe = 0x4a004108,
.cm_dll_ctrl = 0x4a004110,
.cm_clkmode_dpll_core = 0x4a004120,
.cm_idlest_dpll_core = 0x4a004124,
.cm_autoidle_dpll_core = 0x4a004128,
.cm_clksel_dpll_core = 0x4a00412c,
.cm_div_m2_dpll_core = 0x4a004130,
.cm_div_m3_dpll_core = 0x4a004134,
.cm_div_m4_dpll_core = 0x4a004138,
.cm_div_m5_dpll_core = 0x4a00413c,
.cm_div_m6_dpll_core = 0x4a004140,
.cm_div_m7_dpll_core = 0x4a004144,
.cm_ssc_deltamstep_dpll_core = 0x4a004148,
.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
.cm_emu_override_dpll_core = 0x4a004150,
.cm_clkmode_dpll_mpu = 0x4a004160,
.cm_idlest_dpll_mpu = 0x4a004164,
.cm_autoidle_dpll_mpu = 0x4a004168,
.cm_clksel_dpll_mpu = 0x4a00416c,
.cm_div_m2_dpll_mpu = 0x4a004170,
.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
.cm_bypclk_dpll_mpu = 0x4a00419c,
.cm_clkmode_dpll_iva = 0x4a0041a0,
.cm_idlest_dpll_iva = 0x4a0041a4,
.cm_autoidle_dpll_iva = 0x4a0041a8,
.cm_clksel_dpll_iva = 0x4a0041ac,
.cm_div_m4_dpll_iva = 0x4a0041b8,
.cm_div_m5_dpll_iva = 0x4a0041bc,
.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
.cm_bypclk_dpll_iva = 0x4a0041dc,
.cm_clkmode_dpll_abe = 0x4a0041e0,
.cm_idlest_dpll_abe = 0x4a0041e4,
.cm_autoidle_dpll_abe = 0x4a0041e8,
.cm_clksel_dpll_abe = 0x4a0041ec,
.cm_div_m2_dpll_abe = 0x4a0041f0,
.cm_div_m3_dpll_abe = 0x4a0041f4,
.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
.cm_clkmode_dpll_ddrphy = 0x4a004220,
.cm_idlest_dpll_ddrphy = 0x4a004224,
.cm_autoidle_dpll_ddrphy = 0x4a004228,
.cm_clksel_dpll_ddrphy = 0x4a00422c,
.cm_div_m2_dpll_ddrphy = 0x4a004230,
.cm_div_m4_dpll_ddrphy = 0x4a004238,
.cm_div_m5_dpll_ddrphy = 0x4a00423c,
.cm_div_m6_dpll_ddrphy = 0x4a004240,
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
.cm_shadow_freq_config1 = 0x4a004260,
.cm_mpu_mpu_clkctrl = 0x4a004320,
/* cm1.dsp */
.cm_dsp_clkstctrl = 0x4a004400,
.cm_dsp_dsp_clkctrl = 0x4a004420,
/* cm1.abe */
.cm1_abe_clkstctrl = 0x4a004500,
.cm1_abe_l4abe_clkctrl = 0x4a004520,
.cm1_abe_aess_clkctrl = 0x4a004528,
.cm1_abe_pdm_clkctrl = 0x4a004530,
.cm1_abe_dmic_clkctrl = 0x4a004538,
.cm1_abe_mcasp_clkctrl = 0x4a004540,
.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
.cm1_abe_slimbus_clkctrl = 0x4a004560,
.cm1_abe_timer5_clkctrl = 0x4a004568,
.cm1_abe_timer6_clkctrl = 0x4a004570,
.cm1_abe_timer7_clkctrl = 0x4a004578,
.cm1_abe_timer8_clkctrl = 0x4a004580,
.cm1_abe_wdt3_clkctrl = 0x4a004588,
/* cm2.ckgen */
.cm_clksel_mpu_m3_iss_root = 0x4a008100,
.cm_clksel_usb_60mhz = 0x4a008104,
.cm_scale_fclk = 0x4a008108,
.cm_core_dvfs_perf1 = 0x4a008110,
.cm_core_dvfs_perf2 = 0x4a008114,
.cm_core_dvfs_perf3 = 0x4a008118,
.cm_core_dvfs_perf4 = 0x4a00811c,
.cm_core_dvfs_current = 0x4a008124,
.cm_iva_dvfs_perf_tesla = 0x4a008128,
.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
.cm_iva_dvfs_perf_abe = 0x4a008130,
.cm_iva_dvfs_current = 0x4a008138,
.cm_clkmode_dpll_per = 0x4a008140,
.cm_idlest_dpll_per = 0x4a008144,
.cm_autoidle_dpll_per = 0x4a008148,
.cm_clksel_dpll_per = 0x4a00814c,
.cm_div_m2_dpll_per = 0x4a008150,
.cm_div_m3_dpll_per = 0x4a008154,
.cm_div_m4_dpll_per = 0x4a008158,
.cm_div_m5_dpll_per = 0x4a00815c,
.cm_div_m6_dpll_per = 0x4a008160,
.cm_div_m7_dpll_per = 0x4a008164,
.cm_ssc_deltamstep_dpll_per = 0x4a008168,
.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
.cm_emu_override_dpll_per = 0x4a008170,
.cm_clkmode_dpll_usb = 0x4a008180,
.cm_idlest_dpll_usb = 0x4a008184,
.cm_autoidle_dpll_usb = 0x4a008188,
.cm_clksel_dpll_usb = 0x4a00818c,
.cm_div_m2_dpll_usb = 0x4a008190,
.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
.cm_clkmode_dpll_unipro = 0x4a0081c0,
.cm_idlest_dpll_unipro = 0x4a0081c4,
.cm_autoidle_dpll_unipro = 0x4a0081c8,
.cm_clksel_dpll_unipro = 0x4a0081cc,
.cm_div_m2_dpll_unipro = 0x4a0081d0,
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
/* cm2.core */
.cm_l3_1_clkstctrl = 0x4a008700,
.cm_l3_1_dynamicdep = 0x4a008708,
.cm_l3_1_l3_1_clkctrl = 0x4a008720,
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
.cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
.cm_mpu_m3_dynamicdep = 0x4a008908,
.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
.cm_sdma_clkstctrl = 0x4a008a00,
.cm_sdma_staticdep = 0x4a008a04,
.cm_sdma_dynamicdep = 0x4a008a08,
.cm_sdma_sdma_clkctrl = 0x4a008a20,
.cm_memif_clkstctrl = 0x4a008b00,
.cm_memif_dmm_clkctrl = 0x4a008b20,
.cm_memif_emif_fw_clkctrl = 0x4a008b28,
.cm_memif_emif_1_clkctrl = 0x4a008b30,
.cm_memif_emif_2_clkctrl = 0x4a008b38,
.cm_memif_dll_clkctrl = 0x4a008b40,
.cm_memif_emif_h1_clkctrl = 0x4a008b50,
.cm_memif_emif_h2_clkctrl = 0x4a008b58,
.cm_memif_dll_h_clkctrl = 0x4a008b60,
.cm_c2c_clkstctrl = 0x4a008c00,
.cm_c2c_staticdep = 0x4a008c04,
.cm_c2c_dynamicdep = 0x4a008c08,
.cm_c2c_sad2d_clkctrl = 0x4a008c20,
.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
.cm_l4cfg_clkstctrl = 0x4a008d00,
.cm_l4cfg_dynamicdep = 0x4a008d08,
.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
.cm_l3instr_clkstctrl = 0x4a008e00,
.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
.cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
.cm_ivahd_clkstctrl = 0x4a008f00,
/* cm2.ivahd */
.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
.cm_ivahd_sl2_clkctrl = 0x4a008f28,
/* cm2.cam */
.cm_cam_clkstctrl = 0x4a009000,
.cm_cam_iss_clkctrl = 0x4a009020,
.cm_cam_fdif_clkctrl = 0x4a009028,
/* cm2.dss */
.cm_dss_clkstctrl = 0x4a009100,
.cm_dss_dss_clkctrl = 0x4a009120,
/* cm2.sgx */
.cm_sgx_clkstctrl = 0x4a009200,
.cm_sgx_sgx_clkctrl = 0x4a009220,
/* cm2.l3init */
.cm_l3init_clkstctrl = 0x4a009300,
.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
.cm_l3init_hsi_clkctrl = 0x4a009338,
.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
.cm_l3init_p1500_clkctrl = 0x4a009378,
.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
.cm_l3init_usbphy_clkctrl = 0x4a0093e0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009400,
.cm_l4per_dynamicdep = 0x4a009408,
.cm_l4per_adc_clkctrl = 0x4a009420,
.cm_l4per_gptimer10_clkctrl = 0x4a009428,
.cm_l4per_gptimer11_clkctrl = 0x4a009430,
.cm_l4per_gptimer2_clkctrl = 0x4a009438,
.cm_l4per_gptimer3_clkctrl = 0x4a009440,
.cm_l4per_gptimer4_clkctrl = 0x4a009448,
.cm_l4per_gptimer9_clkctrl = 0x4a009450,
.cm_l4per_elm_clkctrl = 0x4a009458,
.cm_l4per_gpio2_clkctrl = 0x4a009460,
.cm_l4per_gpio3_clkctrl = 0x4a009468,
.cm_l4per_gpio4_clkctrl = 0x4a009470,
.cm_l4per_gpio5_clkctrl = 0x4a009478,
.cm_l4per_gpio6_clkctrl = 0x4a009480,
.cm_l4per_hdq1w_clkctrl = 0x4a009488,
.cm_l4per_hecc1_clkctrl = 0x4a009490,
.cm_l4per_hecc2_clkctrl = 0x4a009498,
.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
.cm_l4per_l4per_clkctrl = 0x4a0094c0,
.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
.cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
.cm_l4per_mgate_clkctrl = 0x4a0094e8,
.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
.cm_l4per_mcspi3_clkctrl = 0x4a009500,
.cm_l4per_mcspi4_clkctrl = 0x4a009508,
.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
.cm_l4per_msprohg_clkctrl = 0x4a009530,
.cm_l4per_slimbus2_clkctrl = 0x4a009538,
.cm_l4per_uart1_clkctrl = 0x4a009540,
.cm_l4per_uart2_clkctrl = 0x4a009548,
.cm_l4per_uart3_clkctrl = 0x4a009550,
.cm_l4per_uart4_clkctrl = 0x4a009558,
.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
.cm_l4per_i2c5_clkctrl = 0x4a009568,
.cm_l4sec_clkstctrl = 0x4a009580,
.cm_l4sec_staticdep = 0x4a009584,
.cm_l4sec_dynamicdep = 0x4a009588,
.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
.cm_l4sec_rng_clkctrl = 0x4a0095c0,
.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4a30610c,
.cm_sys_clksel = 0x4a306110,
.cm_wkup_clkstctrl = 0x4a307800,
.cm_wkup_l4wkup_clkctrl = 0x4a307820,
.cm_wkup_wdtimer1_clkctrl = 0x4a307828,
.cm_wkup_wdtimer2_clkctrl = 0x4a307830,
.cm_wkup_gpio1_clkctrl = 0x4a307838,
.cm_wkup_gptimer1_clkctrl = 0x4a307840,
.cm_wkup_gptimer12_clkctrl = 0x4a307848,
.cm_wkup_synctimer_clkctrl = 0x4a307850,
.cm_wkup_usim_clkctrl = 0x4a307858,
.cm_wkup_sarram_clkctrl = 0x4a307860,
.cm_wkup_keyboard_clkctrl = 0x4a307878,
.cm_wkup_rtc_clkctrl = 0x4a307880,
.cm_wkup_bandgap_clkctrl = 0x4a307888,
.prm_vc_val_bypass = 0x4a307ba0,
.prm_vc_cfg_channel = 0x4a307ba4,
.prm_vc_cfg_i2c_mode = 0x4a307ba8,
.prm_vc_cfg_i2c_clk = 0x4a307bac,
};
struct omap_sys_ctrl_regs const omap4_ctrl = {
.control_status = 0x4A0022C4,
.control_std_fuse_die_id_0 = 0x4A002200,
.control_std_fuse_die_id_1 = 0x4A002208,
.control_std_fuse_die_id_2 = 0x4A00220C,
.control_std_fuse_die_id_3 = 0x4A002210,
.control_std_fuse_opp_bgap = 0x4a002260,
.control_status = 0x4a0022c4,
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
.control_ldosram_core_voltage_ctrl = 0x4A002328,
.control_usbotghs_ctrl = 0x4A00233C,
.control_padconf_core_base = 0x4A100000,
.control_pbiaslite = 0x4A100600,
.control_lpddr2io1_0 = 0x4A100638,
.control_lpddr2io1_1 = 0x4A10063C,
.control_lpddr2io1_2 = 0x4A100640,
.control_lpddr2io1_3 = 0x4A100644,
.control_lpddr2io2_0 = 0x4A100648,
.control_lpddr2io2_1 = 0x4A10064C,
.control_lpddr2io2_2 = 0x4A100650,
.control_lpddr2io2_3 = 0x4A100654,
.control_efuse_1 = 0x4A100700,
.control_efuse_2 = 0x4A100704,
.control_padconf_wkup_base = 0x4A31E000,
};

323
arch/arm/mach-omap2/omap4/sdram_elpida.c
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@ -1,323 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Timing and Organization details of the Elpida parts used in OMAP4
* SDPs and Panda
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
*/
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
/*
* This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
* SDP and Panda. Since the parts used and geometry are identical for
* SDP and Panda for a given OMAP4 revision, this information is kept
* here instead of being in board directory. However the key functions
* exported are weakly linked so that they can be over-ridden in the board
* directory if there is a OMAP4 board in the future that uses a different
* memory device or geometry.
*
* For any new board with different memory devices over-ride one or more
* of the following functions as per the CONFIG flags you intend to enable:
* - emif_get_reg_dump()
* - emif_get_dmm_regs()
* - emif_get_device_details()
* - emif_get_device_timings()
*/
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
.sdram_config_init = 0x80000eb9,
.sdram_config = 0x80001ab9,
.ref_ctrl = 0x0000030c,
.sdram_tim1 = 0x08648311,
.sdram_tim2 = 0x101b06ca,
.sdram_tim3 = 0x0048a19f,
.read_idle_ctrl = 0x000501ff,
.zq_config = 0x500b3214,
.temp_alert_config = 0xd8016893,
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
.emif_ddr_phy_ctlr_1 = 0x049ff808
};
const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
.sdram_config_init = 0x80000eb1,
.sdram_config = 0x80001ab1,
.ref_ctrl = 0x000005cd,
.sdram_tim1 = 0x10cb0622,
.sdram_tim2 = 0x20350d52,
.sdram_tim3 = 0x00b1431f,
.read_idle_ctrl = 0x000501ff,
.zq_config = 0x500b3214,
.temp_alert_config = 0x58016893,
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
.sdram_config_init = 0x80800eb2,
.sdram_config = 0x80801ab2,
.ref_ctrl = 0x00000618,
.sdram_tim1 = 0x10eb0662,
.sdram_tim2 = 0x20370dd2,
.sdram_tim3 = 0x00b1c33f,
.read_idle_ctrl = 0x000501ff,
.zq_config = 0x500b3215,
.temp_alert_config = 0x58016893,
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.sdram_config_init = 0x80000eb9,
.sdram_config = 0x80001ab9,
.ref_ctrl = 0x00000618,
.sdram_tim1 = 0x10eb0662,
.sdram_tim2 = 0x20370dd2,
.sdram_tim3 = 0x00b1c33f,
.read_idle_ctrl = 0x000501ff,
.zq_config = 0xd00b3214,
.temp_alert_config = 0xd8016893,
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80540300,
.is_ma_present = 0x0
};
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80640300,
.is_ma_present = 0x0
};
const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80640300,
.is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
u32 omap4_rev = omap_revision();
/* Same devices and geometry on both EMIFs */
if (omap4_rev == OMAP4430_ES1_0)
*regs = &emif_regs_elpida_380_mhz_1cs;
else if (omap4_rev == OMAP4430_ES2_0)
*regs = &emif_regs_elpida_200_mhz_2cs;
else if (omap4_rev < OMAP4470_ES1_0)
*regs = &emif_regs_elpida_400_mhz_2cs;
else
*regs = &emif_regs_elpida_400_mhz_1cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
**dmm_lisa_regs)
{
u32 omap_rev = omap_revision();
if (omap_rev == OMAP4430_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
else if (omap_rev < OMAP4460_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
else
*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
#else
const struct lpddr2_device_details elpida_2G_S4_details = {
.type = LPDDR2_TYPE_S4,
.density = LPDDR2_DENSITY_2Gb,
.io_width = LPDDR2_IO_WIDTH_32,
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
const struct lpddr2_device_details elpida_4G_S4_details = {
.type = LPDDR2_TYPE_S4,
.density = LPDDR2_DENSITY_4Gb,
.io_width = LPDDR2_IO_WIDTH_32,
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
u32 omap_rev = omap_revision();
/* EMIF1 & EMIF2 have identical configuration */
if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
&& (cs == CS1)) {
/* Nothing connected on CS1 for 4430/4470 ES1.0 */
return NULL;
} else if (omap_rev < OMAP4470_ES1_0) {
/* In all other 4430/4460 cases Elpida 2G device */
*lpddr2_dev_details = elpida_2G_S4_details;
} else {
/* 4470: 4G device */
*lpddr2_dev_details = elpida_4G_S4_details;
}
return lpddr2_dev_details;
}
struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
__attribute__((weak, alias("emif_get_device_details_sdp")));
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
.max_freq = 400000000,
.RL = 6,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 15,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
.max_freq = 333000000,
.RL = 5,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 15,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
.max_freq = 200000000,
.RL = 3,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 20,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
static const struct lpddr2_min_tck min_tck_elpida = {
.tRL = 3,
.tRP_AB = 3,
.tRCD = 3,
.tWR = 3,
.tRAS_MIN = 3,
.tRRD = 2,
.tWTR = 2,
.tXP = 2,
.tRTP = 2,
.tCKE = 3,
.tCKESR = 3,
.tFAW = 8
};
static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_elpida_200_mhz,
&timings_elpida_333_mhz,
&timings_elpida_400_mhz
};
const struct lpddr2_device_timings elpida_2G_S4_timings = {
.ac_timings = elpida_ac_timings,
.min_tck = &min_tck_elpida,
};
void emif_get_device_timings_sdp(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
u32 omap_rev = omap_revision();
/* Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &elpida_2G_S4_timings;
if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
*cs1_device_timings = NULL;
else
*cs1_device_timings = &elpida_2G_S4_timings;
}
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
__attribute__((weak, alias("emif_get_device_timings_sdp")));
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
const struct lpddr2_mr_regs mr_regs = {
.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
.mr2 = 0x4,
.mr3 = -1,
.mr10 = MR10_ZQ_ZQINIT,
.mr16 = MR16_REF_FULL_ARRAY
};
void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
*regs = &mr_regs;
}
__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
{
return 0;
}

12
board/beagle/beagle/Kconfig
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@ -1,12 +0,0 @@
if TARGET_OMAP3_BEAGLE
config SYS_BOARD
default "beagle"
config SYS_VENDOR
default "beagle"
config SYS_CONFIG_NAME
default "omap3_beagle"
endif

6
board/beagle/beagle/MAINTAINERS
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@ -1,6 +0,0 @@
BEAGLE BOARD
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/beagle/beagle/
F: include/configs/omap3_beagle.h
F: configs/omap3_beagle_defconfig

7
board/beagle/beagle/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := beagle.o
obj-$(CONFIG_LED_STATUS) += led.o

503
board/beagle/beagle/beagle.c
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@ -1,503 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2004-2011
* Texas Instruments, <www.ti.com>
*
* Author :
* Sunil Kumar <sunilsaini05@gmail.com>
* Shashi Ranjan <shashiranjanmca05@gmail.com>
*
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
*/
#include <config.h>
#include <bootstage.h>
#include <dm.h>
#include <env.h>
#include <init.h>
#include <net.h>
#include <ns16550.h>
#include <serial.h>
#ifdef CONFIG_LED_STATUS
#include <status_led.h>
#endif
#include <twl4030.h>
#include <asm/global_data.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <asm/omap_musb.h>
#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include "beagle.h"
#include <command.h>
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 1
#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
#define TINCANTOOLS_ZIPPY 0x01000100
#define TINCANTOOLS_ZIPPY2 0x02000100
#define TINCANTOOLS_TRAINER 0x04000100
#define TINCANTOOLS_SHOWDOG 0x03000100
#define KBADC_BEAGLEFPGA 0x01000600
#define LW_BEAGLETOUCH 0x01000700
#define BRAINMUX_LCDOG 0x01000800
#define BRAINMUX_LCDOGTOUCH 0x02000800
#define BBTOYS_WIFI 0x01000B00
#define BBTOYS_VGA 0x02000B00
#define BBTOYS_LCD 0x03000B00
#define BCT_BRETTL3 0x01000F00
#define BCT_BRETTL4 0x02000F00
#define LSR_COM6L_ADPT 0x01001300
#define BEAGLE_NO_EEPROM 0xffffffff
DECLARE_GLOBAL_DATA_PTR;
static struct {
unsigned int device_vendor;
unsigned char revision;
unsigned char content;
char fab_revision[8];
char env_var[16];
char env_setting[64];
} expansion_config;
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
#endif
return 0;
}
#if defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
return 0;
}
#endif /* CONFIG_SPL_OS_BOOT */
/*
* Routine: get_board_revision
* Description: Detect if we are running on a Beagle revision Ax/Bx,
* C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
* the level of GPIO173, GPIO172 and GPIO171. This should
* result in
* GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
* GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
* GPIO173, GPIO172, GPIO171: 1 0 1 => C4
* GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
* GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
*/
static int get_board_revision(void)
{
static int revision = -1;
if (revision == -1) {
if (!gpio_request(171, "rev0") &&
!gpio_request(172, "rev1") &&
!gpio_request(173, "rev2")) {
gpio_direction_input(171);
gpio_direction_input(172);
gpio_direction_input(173);
revision = gpio_get_value(173) << 2 |
gpio_get_value(172) << 1 |
gpio_get_value(171);
} else {
printf("Error: unable to acquire board revision GPIOs\n");
}
}
return revision;
}
#ifdef CONFIG_SPL_BUILD
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
/*
* We need to identify what PoP memory is on the board so that
* we know what timings to use. If we can't identify it then
* we know it's an xM. To map the ID values please see nand_ids.c
*/
identify_nand_chip(&pop_mfr, &pop_id);
timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_C4:
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */
timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
/* Beagleboard Rev C5, 256MB DDR */
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
}
case REVISION_XM_AB:
case REVISION_XM_C:
if (pop_mfr == 0) {
/* 256MB DDR */
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} else {
/* 512MB DDR */
timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
break;
default:
/* Assume 128MB and Micron/165MHz timings to be safe */
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
#endif
/*
* Routine: get_expansion_id
* Description: This function checks for expansion board by checking I2C
* bus 1 for the availability of an AT24C01B serial EEPROM.
* returns the device_vendor field from the EEPROM
*/
static unsigned int get_expansion_id(void)
{
i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
/* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
i2c_set_bus_num(TWL4030_I2C_BUS);
return BEAGLE_NO_EEPROM;
}
/* read configuration data */
i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
sizeof(expansion_config));
/* retry reading configuration data with 16bit addressing */
if ((expansion_config.device_vendor == 0xFFFFFF00) ||
(expansion_config.device_vendor == 0xFFFFFFFF)) {
printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
sizeof(expansion_config));
}
i2c_set_bus_num(TWL4030_I2C_BUS);
return expansion_config.device_vendor;
}
#ifdef CONFIG_VIDEO_OMAP3
/*
* Configure DSS to display background color on DVID
* Configure VENC to display color bar on S-Video
*/
static void beagle_display_init(void)
{
omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
switch (get_board_revision()) {
case REVISION_AXBX:
case REVISION_CX:
case REVISION_C4:
omap3_dss_panel_config(&dvid_cfg);
break;
case REVISION_XM_AB:
case REVISION_XM_C:
default:
omap3_dss_panel_config(&dvid_cfg_xm);
break;
}
}
/*
* Enable DVI power
*/
static void beagle_dvi_pup(void)
{
uchar val;
switch (get_board_revision()) {
case REVISION_AXBX:
case REVISION_CX:
case REVISION_C4:
gpio_request(170, "dvi");
gpio_direction_output(170, 0);
gpio_set_value(170, 1);
break;
case REVISION_XM_AB:
case REVISION_XM_C:
default:
#define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
#define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6)
i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
val |= 4;
i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
val |= 4;
i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
break;
}
}
#endif
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
bool generate_fake_mac = false;
u32 value;
/* Enable i2c2 pullup resisters */
value = readl(&prog_io_base->io1);
value &= ~(PRG_I2C2_PULLUPRESX);
writel(value, &prog_io_base->io1);
switch (get_board_revision()) {
case REVISION_AXBX:
printf("Beagle Rev Ax/Bx\n");
env_set("beaglerev", "AxBx");
break;
case REVISION_CX:
printf("Beagle Rev C1/C2/C3\n");
env_set("beaglerev", "Cx");
MUX_BEAGLE_C();
break;
case REVISION_C4:
printf("Beagle Rev C4\n");
env_set("beaglerev", "C4");
MUX_BEAGLE_C();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
break;
case REVISION_XM_AB:
printf("Beagle xM Rev A/B\n");
env_set("beaglerev", "xMAB");
MUX_BEAGLE_XM();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
generate_fake_mac = true;
break;
case REVISION_XM_C:
printf("Beagle xM Rev C\n");
env_set("beaglerev", "xMC");
MUX_BEAGLE_XM();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
generate_fake_mac = true;
break;
default:
printf("Beagle unknown 0x%02x\n", get_board_revision());
MUX_BEAGLE_XM();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
generate_fake_mac = true;
}
switch (get_expansion_id()) {
case TINCANTOOLS_ZIPPY:
printf("Recognized Tincantools Zippy board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_TINCANTOOLS_ZIPPY();
env_set("buddy", "zippy");
break;
case TINCANTOOLS_ZIPPY2:
printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_TINCANTOOLS_ZIPPY();
env_set("buddy", "zippy2");
break;
case TINCANTOOLS_TRAINER:
printf("Recognized Tincantools Trainer board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_TINCANTOOLS_ZIPPY();
MUX_TINCANTOOLS_TRAINER();
env_set("buddy", "trainer");
break;
case TINCANTOOLS_SHOWDOG:
printf("Recognized Tincantools Showdow board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
/* Place holder for DSS2 definition for showdog lcd */
env_set("defaultdisplay", "showdoglcd");
env_set("buddy", "showdog");
break;
case KBADC_BEAGLEFPGA:
printf("Recognized KBADC Beagle FPGA board\n");
MUX_KBADC_BEAGLEFPGA();
env_set("buddy", "beaglefpga");
break;
case LW_BEAGLETOUCH:
printf("Recognized Liquidware BeagleTouch board\n");
env_set("buddy", "beagletouch");
break;
case BRAINMUX_LCDOG:
printf("Recognized Brainmux LCDog board\n");
env_set("buddy", "lcdog");
break;
case BRAINMUX_LCDOGTOUCH:
printf("Recognized Brainmux LCDog Touch board\n");
env_set("buddy", "lcdogtouch");
break;
case BBTOYS_WIFI:
printf("Recognized BeagleBoardToys WiFi board\n");
MUX_BBTOYS_WIFI()
env_set("buddy", "bbtoys-wifi");
break;
case BBTOYS_VGA:
printf("Recognized BeagleBoardToys VGA board\n");
break;
case BBTOYS_LCD:
printf("Recognized BeagleBoardToys LCD board\n");
break;
case BCT_BRETTL3:
printf("Recognized bct electronic GmbH brettl3 board\n");
break;
case BCT_BRETTL4:
printf("Recognized bct electronic GmbH brettl4 board\n");
break;
case LSR_COM6L_ADPT:
printf("Recognized LSR COM6L Adapter Board\n");
MUX_BBTOYS_WIFI()
env_set("buddy", "lsr-com6l-adpt");
break;
case BEAGLE_NO_EEPROM:
printf("No EEPROM on expansion board\n");
env_set("buddy", "none");
break;
default:
printf("Unrecognized expansion board: %x\n",
expansion_config.device_vendor);
env_set("buddy", "unknown");
}
if (expansion_config.content == 1)
env_set(expansion_config.env_var, expansion_config.env_setting);
twl4030_power_init();
twl4030_power_mmc_init(0);
switch (get_board_revision()) {
case REVISION_XM_AB:
twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
break;
default:
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
break;
}
/* Set GPIO states before they are made outputs */
writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
&gpio6_base->setdataout);
writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
/* Configure GPIOs to output */
writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
omap_die_id_display();
#ifdef CONFIG_VIDEO_OMAP3
beagle_dvi_pup();
beagle_display_init();
omap3_dss_enable();
#endif
if (generate_fake_mac)
omap_die_id_usbethaddr();
#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
if (strlen(CONFIG_MTDIDS_DEFAULT))
env_set("mtdids", CONFIG_MTDIDS_DEFAULT);
if (strlen(CONFIG_MTDPARTS_DEFAULT))
env_set("mtdparts", CONFIG_MTDPARTS_DEFAULT);
#endif
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_BEAGLE();
}

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board/beagle/beagle/beagle.h
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@ -1,545 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008
* Dirk Behme <dirk.behme@gmail.com>
*/
#ifndef _BEAGLE_H_
#define _BEAGLE_H_
#include <asm/arch/dss.h>
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"OMAP3 Beagle board",
#if defined(CONFIG_ENV_IS_IN_ONENAND)
"OneNAND",
#else
"NAND",
#endif
};
/* BeagleBoard revisions */
#define REVISION_AXBX 0x7
#define REVISION_CX 0x6
#define REVISION_C4 0x5
#define REVISION_XM_AB 0x0
#define REVISION_XM_C 0x2
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_BEAGLE() \
/*SDRC*/\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
/*GPMC*/\
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
/*CAMERA*/\
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
/*Audio Interface */\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
/*Expansion card */\
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
/*Wireless LAN */\
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
/*Bluetooth*/\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
/*Modem Interface */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
/*Serial Interface*/\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
/* USB EHCI (port 2) */\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\
/*Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
#define MUX_BEAGLE_C() \
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/
#define MUX_BEAGLE_XM() \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\
MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4)) /*GPIO_63*/\
MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_129*/\
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
#define MUX_TINCANTOOLS_ZIPPY() \
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\
MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/
#define MUX_TINCANTOOLS_TRAINER() \
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) /*GPIO_140*/\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/
#define MUX_KBADC_BEAGLEFPGA() \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
#define MUX_BBTOYS_WIFI() \
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) /*GPIO_136 FM_EN/BT_WU*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 WLAN_IRQ*/\
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\
MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/
/*
* Display Configuration
*/
#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
#define VENC_HEIGHT 0x00ef
#define VENC_WIDTH 0x027f
/*
* Configure VENC in DSS for Beagle to generate Color Bar
*
* Kindly refer to OMAP TRM for definition of these values.
*/
static const struct venc_regs venc_config_std_tv = {
.status = 0x0000001B,
.f_control = 0x00000040,
.vidout_ctrl = 0x00000000,
.sync_ctrl = 0x00008000,
.llen = 0x00008359,
.flens = 0x0000020C,
.hfltr_ctrl = 0x00000000,
.cc_carr_wss_carr = 0x043F2631,
.c_phase = 0x00000024,
.gain_u = 0x00000130,
.gain_v = 0x00000198,
.gain_y = 0x000001C0,
.black_level = 0x0000006A,
.blank_level = 0x0000005C,
.x_color = 0x00000000,
.m_control = 0x00000001,
.bstamp_wss_data = 0x0000003F,
.s_carr = 0x21F07C1F,
.line21 = 0x00000000,
.ln_sel = 0x00000015,
.l21__wc_ctl = 0x00001400,
.htrigger_vtrigger = 0x00000000,
.savid__eavid = 0x069300F4,
.flen__fal = 0x0016020C,
.lal__phase_reset = 0x00060107,
.hs_int_start_stop_x = 0x008D034E,
.hs_ext_start_stop_x = 0x000F0359,
.vs_int_start_x = 0x01A00000,
.vs_int_stop_x__vs_int_start_y = 0x020501A0,
.vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
.vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
.vs_ext_stop_y = 0x00000006,
.avid_start_stop_x = 0x03480079,
.avid_start_stop_y = 0x02040024,
.fid_int_start_x__fid_int_start_y = 0x0001008A,
.fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
.fid_ext_start_y__fid_ext_offset_y = 0x01060006,
.tvdetgp_int_start_stop_x = 0x00140001,
.tvdetgp_int_start_stop_y = 0x00010001,
.gen_ctrl = 0x00FF0000,
.output_control = 0x0000000D,
.dac_b__dac_c = 0x00000000
};
/*
* Configure Timings for DVI D
*/
static const struct panel_config dvid_cfg = {
.timing_h = 0x0ff03f31, /* Horizontal timing */
.timing_v = 0x01400504, /* Vertical timing */
.pol_freq = 0x00007028, /* Pol Freq */
.divisor = 0x00010006, /* 72Mhz Pixel Clock */
.lcd_size = 0x02ff03ff, /* 1024x768 */
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
.gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
static const struct panel_config dvid_cfg_xm = {
.timing_h = 0x1a4024c9, /* Horizontal timing */
.timing_v = 0x02c00509, /* Vertical timing */
.pol_freq = 0x00007028, /* Pol Freq */
.divisor = 0x00010001, /* 96MHz Pixel Clock */
.lcd_size = 0x02ff03ff, /* 1024x768 */
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
.gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
#endif

70
board/beagle/beagle/led.c
View File

@ -1,70 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2010 Texas Instruments, Inc.
* Jason Kridner <jkridner@beagleboard.org>
*/
#include <status_led.h>
#include <asm/arch/cpu.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
/* GPIO pins for the LEDs */
#define BEAGLE_LED_USR0 150
#define BEAGLE_LED_USR1 149
#ifdef CONFIG_LED_STATUS_GREEN
void green_led_off(void)
{
__led_set(CONFIG_LED_STATUS_GREEN, 0);
}
void green_led_on(void)
{
__led_set(CONFIG_LED_STATUS_GREEN, 1);
}
#endif
static int get_led_gpio(led_id_t mask)
{
#ifdef CONFIG_LED_STATUS0
if (CONFIG_LED_STATUS_BIT & mask)
return BEAGLE_LED_USR0;
#endif
#ifdef CONFIG_LED_STATUS1
if (CONFIG_LED_STATUS_BIT1 & mask)
return BEAGLE_LED_USR1;
#endif
return 0;
}
void __led_init (led_id_t mask, int state)
{
int toggle_gpio;
toggle_gpio = get_led_gpio(mask);
if (toggle_gpio && !gpio_request(toggle_gpio, "led"))
__led_set(mask, state);
}
void __led_toggle (led_id_t mask)
{
int state, toggle_gpio;
toggle_gpio = get_led_gpio(mask);
if (toggle_gpio) {
state = gpio_get_value(toggle_gpio);
gpio_direction_output(toggle_gpio, !state);
}
}
void __led_set (led_id_t mask, int state)
{
int toggle_gpio;
toggle_gpio = get_led_gpio(mask);
if (toggle_gpio)
gpio_direction_output(toggle_gpio, state);
}

3
board/keymile/Kconfig
View File

@ -11,9 +11,6 @@ if VENDOR_KM
menu "KM Board Setup" menu "KM Board Setup"
config SYS_I2C_INIT_BOARD
def_bool y if ARM
config HUSH_INIT_VAR config HUSH_INIT_VAR
def_bool y def_bool y

12
board/keymile/common/common.c
View File

@ -129,7 +129,6 @@ void check_for_uboot_update(void)
} }
#endif #endif
#if defined(CONFIG_SYS_I2C_INIT_BOARD)
static void i2c_write_start_seq(void) static void i2c_write_start_seq(void)
{ {
set_sda(1); set_sda(1);
@ -187,17 +186,6 @@ int i2c_make_abort(void)
return ret; return ret;
} }
/**
* i2c_init_board - reset i2c bus. When the board is powercycled during a
* bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
*/
void i2c_init_board(void)
{
/* Now run the AbortSequence() */
i2c_make_abort();
}
#endif
#if defined(CONFIG_KM_COMMON_ETH_INIT) #if defined(CONFIG_KM_COMMON_ETH_INIT)
int board_eth_init(struct bd_info *bis) int board_eth_init(struct bd_info *bis)
{ {

3
board/keymile/common/common.h
View File

@ -138,13 +138,12 @@ void early_bootcount_store(ulong ebootcount);
void check_for_uboot_update(void); void check_for_uboot_update(void);
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ #define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) #define DELAY_HALF_PERIOD (500 / (I2C_SPEED_STANDARD_RATE / 1000))
void set_sda(int state); void set_sda(int state);
void set_scl(int state); void set_scl(int state);
int get_sda(void); int get_sda(void);
int get_scl(void); int get_scl(void);
int i2c_soft_read_pin(void);
int i2c_make_abort(void); int i2c_make_abort(void);
#endif /* __KEYMILE_COMMON_H */ #endif /* __KEYMILE_COMMON_H */

18
board/keymile/common/ivm.c
View File

@ -342,9 +342,8 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset) int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
{ {
int ret;
#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *eedev = NULL; struct udevice *eedev = NULL;
int ret;
ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS, ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS,
CONFIG_SYS_IVM_EEPROM_ADR, 1, &eedev); CONFIG_SYS_IVM_EEPROM_ADR, 1, &eedev);
@ -354,22 +353,17 @@ int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
return 1; return 1;
} }
#if CONFIG_IS_ENABLED(ARCH_LS1021A)
/* add deblocking here */
i2c_make_abort();
#endif
ret = dm_i2c_read(eedev, 0, buf, len); ret = dm_i2c_read(eedev, 0, buf, len);
if (ret != 0) { if (ret != 0) {
printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n", printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n",
CONFIG_SYS_IVM_EEPROM_ADR, 0); CONFIG_SYS_IVM_EEPROM_ADR, 0);
return 1; return 1;
} }
#else
i2c_set_bus_num(CONFIG_KM_IVM_BUS);
/* add deblocking here */
i2c_make_abort();
ret = i2c_read(CONFIG_SYS_IVM_EEPROM_ADR, 0, 1, buf, len);
if (ret != 0) {
printf("Error reading EEprom\n");
return -2;
}
#endif
return ivm_populate_env(buf, len, mac_address_offset); return ivm_populate_env(buf, len, mac_address_offset);
} }

8
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
View File

@ -5,7 +5,6 @@
#include <config.h> #include <config.h>
#include <event.h> #include <event.h>
#include <i2c.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/immap_ls102xa.h> #include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
@ -107,6 +106,13 @@ int board_early_init_f(void)
arch_soc_init(); arch_soc_init();
/*
* Reset I2C bus. When the board is powercycled during a bus
* transfer it might hang; for details see doc/I2C_Edge_Conditions.
* Now run the AbortSequence()
*/
i2c_make_abort();
return 0; return 0;
} }

14
board/ti/panda/Kconfig
View File

@ -1,14 +0,0 @@
if TARGET_OMAP4_PANDA
config SYS_BOARD
default "panda"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "omap4_panda"
source "board/ti/common/Kconfig"
endif

6
board/ti/panda/MAINTAINERS
View File

@ -1,6 +0,0 @@
PANDA BOARD
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/panda/
F: include/configs/omap4_panda.h
F: configs/omap4_panda_defconfig

6
board/ti/panda/Makefile
View File

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := panda.o

322
board/ti/panda/panda.c
View File

@ -1,322 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Texas Instruments Incorporated, <www.ti.com>
* Steve Sakoman <steve@sakoman.com>
*/
#include <init.h>
#include <log.h>
#include <net.h>
#include <serial.h>
#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <env.h>
#include <twl6030.h>
#include "panda_mux_data.h"
#define PANDA_ULPI_PHY_TYPE_GPIO 182
#define PANDA_BOARD_ID_1_GPIO 101
#define PANDA_ES_BOARD_ID_1_GPIO 48
#define PANDA_BOARD_ID_2_GPIO 171
#define PANDA_ES_BOARD_ID_3_GPIO 3
#define PANDA_ES_BOARD_ID_4_GPIO 2
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
"Board: OMAP4 Panda\n"
};
struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
/**
* @brief board_init
*
* Return: 0
*/
int board_init(void)
{
gpmc_init();
gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
return 0;
}
#if defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
return 0;
}
#endif /* CONFIG_SPL_OS_BOOT */
int board_eth_init(struct bd_info *bis)
{
return 0;
}
/*
* Routine: get_board_revision
* Description: Detect if we are running on a panda revision A1-A6,
* or an ES panda board. This can be done by reading
* the level of GPIOs and checking the processor revisions.
* This should result in:
* Panda 4430:
* GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
* GPIO171, GPIO101, GPIO182: 1 0 1 => A6
* Panda ES:
* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
*/
int get_board_revision(void)
{
int board_id0, board_id1, board_id2;
int board_id3, board_id4;
int board_id;
int processor_rev = omap_revision();
/* Setup the mux for the common board ID pins (gpio 171 and 182) */
writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
if ((processor_rev >= OMAP4460_ES1_0 &&
processor_rev <= OMAP4460_ES1_1)) {
/*
* Setup the mux for the ES specific board ID pins (gpio 101,
* 2 and 3.
*/
writew((IEN | M3), (*ctrl)->control_padconf_core_base +
GPMC_A24);
writew((IEN | M3), (*ctrl)->control_padconf_core_base +
UNIPRO_RY0);
writew((IEN | M3), (*ctrl)->control_padconf_core_base +
UNIPRO_RX1);
board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "panda-es");
#endif
board_id = ((board_id4 << 4) | (board_id3 << 3) |
(board_id2 << 2) | (board_id1 << 1) | (board_id0));
} else {
/* Setup the mux for the Ax specific board ID pins (gpio 101) */
writew((IEN | M3), (*ctrl)->control_padconf_core_base +
FREF_CLK2_OUT);
board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
env_set("board_name", "panda-a4");
#endif
}
return board_id;
}
/**
* is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
*
*
* Detect if we are running on B3 version of ES panda board,
* This can be done by reading the level of GPIO 171 and checking the
* processor revisions.
* GPIO171: 1 => Panda ES Rev B3
*
* Return : return 1 if Panda ES Rev B3 , else return 0
*/
u8 is_panda_es_rev_b3(void)
{
int processor_rev = omap_revision();
int ret = 0;
if ((processor_rev >= OMAP4460_ES1_0 &&
processor_rev <= OMAP4460_ES1_1)) {
/* Setup the mux for the common board ID pins (gpio 171) */
writew((IEN | M3),
(*ctrl)->control_padconf_core_base + UNIPRO_TX0);
/* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
}
return ret;
}
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
/*
* emif_get_reg_dump() - emif_get_reg_dump strong function
*
* @emif_nr - emif base
* @regs - reg dump of timing values
*
* Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
*/
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
u32 omap4_rev = omap_revision();
/* Same devices and geometry on both EMIFs */
if (omap4_rev == OMAP4430_ES1_0)
*regs = &emif_regs_elpida_380_mhz_1cs;
else if (omap4_rev == OMAP4430_ES2_0)
*regs = &emif_regs_elpida_200_mhz_2cs;
else if (omap4_rev == OMAP4430_ES2_3)
*regs = &emif_regs_elpida_400_mhz_1cs;
else if (omap4_rev < OMAP4470_ES1_0) {
if(is_panda_es_rev_b3())
*regs = &emif_regs_elpida_400_mhz_1cs;
else
*regs = &emif_regs_elpida_400_mhz_2cs;
}
else
*regs = &emif_regs_elpida_400_mhz_1cs;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs)
{
u32 omap_rev = omap_revision();
if (omap_rev == OMAP4430_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
else if (omap_rev == OMAP4430_ES2_3)
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
else if (omap_rev < OMAP4460_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
else
*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
}
#endif
/**
* @brief misc_init_r - Configure Panda board specific configurations
* such as power configurations, ethernet initialization as phase2 of
* boot sequence
*
* Return: 0
*/
int misc_init_r(void)
{
int phy_type;
u32 auxclk, altclksrc;
/* EHCI is not supported on ES1.0 */
if (omap_revision() == OMAP4430_ES1_0)
return 0;
get_board_revision();
gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
if (phy_type == 1) {
/* ULPI PHY supplied by auxclk3 derived from sys_clk */
debug("ULPI PHY supplied by auxclk3\n");
auxclk = readl(&scrm->auxclk3);
/* Select sys_clk */
auxclk &= ~AUXCLK_SRCSELECT_MASK;
auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
/* Set the divisor to 2 */
auxclk &= ~AUXCLK_CLKDIV_MASK;
auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
/* Request auxilary clock #3 */
auxclk |= AUXCLK_ENABLE_MASK;
writel(auxclk, &scrm->auxclk3);
} else {
/* ULPI PHY supplied by auxclk1 derived from PER dpll */
debug("ULPI PHY supplied by auxclk1\n");
auxclk = readl(&scrm->auxclk1);
/* Select per DPLL */
auxclk &= ~AUXCLK_SRCSELECT_MASK;
auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
/* Set the divisor to 16 */
auxclk &= ~AUXCLK_CLKDIV_MASK;
auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
/* Request auxilary clock #3 */
auxclk |= AUXCLK_ENABLE_MASK;
writel(auxclk, &scrm->auxclk1);
}
altclksrc = readl(&scrm->altclksrc);
/* Activate alternate system clock supplier */
altclksrc &= ~ALTCLKSRC_MODE_MASK;
altclksrc |= ALTCLKSRC_MODE_ACTIVE;
/* enable clocks */
altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
writel(altclksrc, &scrm->altclksrc);
omap_die_id_usbethaddr();
return 0;
}
void set_muxconf_regs(void)
{
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
if (omap_revision() >= OMAP4460_ES1_0)
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential_4460,
sizeof(wkup_padconf_array_essential_4460) /
sizeof(struct pad_conf_entry));
}
#if defined(CONFIG_MMC)
int board_mmc_init(struct bd_info *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#if !defined(CONFIG_SPL_BUILD)
void board_mmc_power_init(void)
{
twl6030_power_mmc_init(0);
}
#endif
#endif
#ifdef CONFIG_REVISION_TAG
/*
* get_board_rev() - get board revision
*/
u32 get_board_rev(void)
{
return 0x20;
}
#endif

85
board/ti/panda/panda_mux_data.h
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@ -1,85 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Texas Instruments Incorporated, <www.ti.com>
*
* Balaji Krishnamoorthy <balajitk@ti.com>
* Aneesh V <aneesh@ti.com>
*/
#ifndef _PANDA_MUX_DATA_H_
#define _PANDA_MUX_DATA_H_
#include <asm/arch/mux_omap4.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
{UART3_TX_IRTX, (M0)}, /* uart3_tx */
{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
{UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
{GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
{FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
};
const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
};
#endif /* _PANDA_MUX_DATA_H_ */

17
board/ti/sdp4430/Kconfig
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@ -1,17 +0,0 @@
if TARGET_OMAP4_SDP4430
config SYS_BOARD
default "sdp4430"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "omap4_sdp4430"
config CMD_BAT
bool "Enable board-specific battery command"
source "board/ti/common/Kconfig"
endif

6
board/ti/sdp4430/MAINTAINERS
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@ -1,6 +0,0 @@
SDP4430 BOARD
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/sdp4430/
F: include/configs/omap4_sdp4430.h
F: configs/omap4_sdp4430_defconfig

10
board/ti/sdp4430/Makefile
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@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := sdp.o
ifndef CONFIG_SPL_BUILD
obj-y += cmd_bat.o
endif

40
board/ti/sdp4430/cmd_bat.c
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@ -1,40 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 Texas Instruments
*/
#include <command.h>
#ifdef CONFIG_CMD_BAT
#include <twl6030.h>
int do_vbat(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
if (argc == 2) {
if (strncmp(argv[1], "startcharge", 12) == 0)
twl6030_start_usb_charging();
else if (strncmp(argv[1], "stopcharge", 11) == 0)
twl6030_stop_usb_charging();
else if (strncmp(argv[1], "status", 7) == 0) {
twl6030_get_battery_voltage();
twl6030_get_battery_current();
} else {
goto bat_cmd_usage;
}
} else {
goto bat_cmd_usage;
}
return 0;
bat_cmd_usage:
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
bat, 2, 1, do_vbat,
"battery charging, voltage/current measurements",
"status - display battery voltage and current\n"
"bat startcharge - start charging via USB\n"
"bat stopcharge - stop charging\n"
);
#endif /* CONFIG_CMD_BAT */

114
board/ti/sdp4430/sdp.c
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@ -1,114 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Texas Instruments Incorporated, <www.ti.com>
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*/
#include <init.h>
#include <net.h>
#include <twl6030.h>
#include <serial.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/global_data.h>
#include "sdp4430_mux_data.h"
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
"Board: OMAP4430 SDP\n"
};
/**
* @brief board_init
*
* Return: 0
*/
int board_init(void)
{
gpmc_init();
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
return 0;
}
int board_eth_init(struct bd_info *bis)
{
return 0;
}
/**
* @brief misc_init_r - Configure SDP board specific configurations
* such as power configurations, ethernet initialization as phase2 of
* boot sequence
*
* Return: 0
*/
int misc_init_r(void)
{
#ifdef CONFIG_TWL6030_POWER
twl6030_init_battery_charging();
#endif
return 0;
}
void set_muxconf_regs(void)
{
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
if ((omap_revision() >= OMAP4460_ES1_0) &&
(omap_revision() < OMAP4470_ES1_0))
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential_4460,
sizeof(wkup_padconf_array_essential_4460) /
sizeof(struct pad_conf_entry));
}
#if defined(CONFIG_MMC)
int board_mmc_init(struct bd_info *bis)
{
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#if !defined(CONFIG_SPL_BUILD)
void board_mmc_power_init(void)
{
twl6030_power_mmc_init(0);
twl6030_power_mmc_init(1);
}
#endif
#endif
#if defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
return 0;
}
#endif /* CONFIG_SPL_OS_BOOT */
#ifdef CONFIG_REVISION_TAG
/*
* get_board_rev() - get board revision
*/
u32 get_board_rev(void)
{
return 0x20;
}
#endif

67
board/ti/sdp4430/sdp4430_mux_data.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Texas Instruments Incorporated, <www.ti.com>
*
* Balaji Krishnamoorthy <balajitk@ti.com>
* Aneesh V <aneesh@ti.com>
*/
#ifndef _SDP4430_MUX_DATA_H
#define _SDP4430_MUX_DATA_H
#include <asm/arch/mux_omap4.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
{UART3_TX_IRTX, (M0)}, /* uart3_tx */
{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
};
const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
};
#endif /* _SDP4430_MUX_DATA_H */

12
board/timll/devkit3250/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_DEVKIT3250
config SYS_BOARD
default "devkit3250"
config SYS_VENDOR
default "timll"
config SYS_CONFIG_NAME
default "devkit3250"
endif

6
board/timll/devkit3250/MAINTAINERS
View File

@ -1,6 +0,0 @@
DEVKIT3250 BOARD
M: Vladimir Zapolskiy <vz@mleia.com>
S: Maintained
F: board/timll/devkit3250/
F: include/configs/devkit3250.h
F: configs/devkit3250_defconfig

7
board/timll/devkit3250/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
obj-y := devkit3250.o
obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o

83
board/timll/devkit3250/devkit3250.c
View File

@ -1,83 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Embest/Timll DevKit3250 board support
*
* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*/
#include <config.h>
#include <init.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
#include <asm/arch/emc.h>
#include <asm/arch/wdt.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
void reset_periph(void)
{
/* This function resets peripherals by triggering RESOUT_N */
setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
udelay(300);
writel(0, &wdt->mctrl);
clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
/* Such a long delay is needed to initialize SMSC phy */
udelay(10000);
}
int board_early_init_f(void)
{
lpc32xx_uart_init(CONFIG_CONS_INDEX);
lpc32xx_i2c_init(1);
lpc32xx_i2c_init(2);
lpc32xx_ssp_init();
lpc32xx_mac_init();
/*
* nWP may be controlled by GPO19, but unpopulated by default R23
* makes no sense to configure this GPIO level, nWP is always high
*/
lpc32xx_slc_nand_init();
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_SYS_FLASH_CFI
/* Use 16-bit memory interface for NOR Flash */
emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
/* Change the NOR timings to optimum value to get maximum bandwidth */
emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

66
board/timll/devkit3250/devkit3250_spl.c
View File

@ -1,66 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Timll DevKit3250 board support, SPL board configuration
*
* (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
*/
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <asm/arch/emc.h>
#include <asm/arch-lpc32xx/gpio.h>
#include <spl.h>
static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
/*
* SDRAM K4S561632N-LC60 settings are selected in assumption that
* SDRAM clock may be set up to 166 MHz, however at the moment
* it is 104 MHz. Most delay values are converted to be a multiple of
* base clock, and precise pinned values are not needed here.
*/
struct emc_dram_settings dram_64mb = {
.cmddelay = 0x0001C000,
.config0 = 0x00005682,
.rascas0 = 0x00000302,
.rdconfig = 0x00000011, /* undocumented but crucial value */
.trp = 83333333,
.tras = 23809524,
.tsrex = 12500000,
.twr = 83000000, /* tWR = tRDL = 2 CLK */
.trc = 15384616,
.trfc = 15384616,
.txsr = 12500000,
.trrd = 1,
.tmrd = 1,
.tcdlr = 0,
.refresh = 130000, /* 800 clock cycles */
.mode = 0x00018000,
.emode = 0x02000000,
};
void spl_board_init(void)
{
/* First of all silence buzzer controlled by GPO_20 */
writel((1 << 20), &gpio->p3_outp_clr);
lpc32xx_uart_init(CONFIG_CONS_INDEX);
preloader_console_init();
ddr_init(&dram_64mb);
/*
* NAND initialization is done by nand_init(),
* here just enable NAND SLC clocks
*/
lpc32xx_slc_nand_init();
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_NAND;
}

4
common/spl/Kconfig
View File

@ -500,7 +500,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
ARCH_MX6 || ARCH_MX7 || \ ARCH_MX6 || ARCH_MX7 || \
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP44XX || OMAP54XX || AM33XX || AM43XX || \ OMAP54XX || AM33XX || AM43XX || \
TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
select SPL_LOAD_BLOCK if SPL_MMC select SPL_LOAD_BLOCK if SPL_MMC
select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
@ -517,7 +517,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
default 0x100 if ARCH_UNIPHIER default 0x100 if ARCH_UNIPHIER
default 0x0 if ARCH_MVEBU default 0x0 if ARCH_MVEBU
default 0x200 if ARCH_SOCFPGA || ARCH_AT91 default 0x200 if ARCH_SOCFPGA || ARCH_AT91
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \ default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP54XX || AM33XX || AM43XX || ARCH_K3 OMAP54XX || AM33XX || AM43XX || ARCH_K3
default 0x4000 if ARCH_ROCKCHIP default 0x4000 if ARCH_ROCKCHIP
default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED

93
configs/devkit3250_defconfig
View File

@ -1,93 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_LPC32XX=y
CONFIG_TEXT_BASE=0x83F00000
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f20
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xA0000
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SYS_MONITOR_LEN=393216
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xfff8
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp; tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; setenv bootargs ${bootargs} ${nfsargs} ${userargs}; bootm ${loadaddr} - ${dtbaddr}"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SOFTECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_DMA_LPC32XX=y
CONFIG_LPC32XX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_LPC32XX=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=71
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_LPC32XX_SLC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=31
CONFIG_PHY_SMSC=y
CONFIG_RMII=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=5
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
CONFIG_SYS_USB_OHCI_SLOT_NAME="lpc32xx-ohci"
CONFIG_USB_OHCI_LPC32XX=y
CONFIG_OF_LIBFDT=y

115
configs/omap3_beagle_defconfig
View File

@ -1,115 +0,0 @@
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_SYS_PBSIZE=1055
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SYS_PROMPT="BeagleBoard # "
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x280000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=1
CONFIG_LED_STATUS_STATE=2
CONFIG_LED_STATUS1=y
CONFIG_LED_STATUS_BIT1=2
CONFIG_LED_STATUS_STATE1=2
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=1
CONFIG_LED_STATUS_GREEN_ENABLE=y
CONFIG_LED_STATUS_GREEN=2
CONFIG_LED_STATUS_CMD=y
CONFIG_TWL4030_LED=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
CONFIG_BCH=y

54
configs/omap4_panda_defconfig
View File

@ -1,54 +0,0 @@
CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030df00
CONFIG_DEFAULT_DEVICE_TREE="omap4-panda"
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_PANDA=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="omap4-panda.dtb"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xbc00
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_TWL6030_POWER=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OMAP3=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y

51
configs/omap4_sdp4430_defconfig
View File

@ -1,51 +0,0 @@
CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030df00
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="omap4-sdp"
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_SDP4430=y
CONFIG_CMD_BAT=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="omap4-sdp.dtb"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xbc00
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_I2C is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_TWL6030_POWER=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_OMAP3=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
# CONFIG_REGEX is not set
# CONFIG_EFI_LOADER is not set

8
configs/pg_wcom_expu1_defconfig
View File

@ -8,9 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1" CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@ -78,7 +76,9 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BOOTCOUNT_BE=y
CONFIG_DDR_CLK_FREQ=50000000 CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_I2C_LEGACY=y CONFIG_DM_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set # CONFIG_MMC is not set
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_NOR_FLASH=y

8
configs/pg_wcom_expu1_update_defconfig
View File

@ -8,9 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1"
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1" CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@ -76,7 +74,9 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BOOTCOUNT_BE=y
CONFIG_DDR_CLK_FREQ=50000000 CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_I2C_LEGACY=y CONFIG_DM_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set # CONFIG_MMC is not set
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_NOR_FLASH=y

8
configs/pg_wcom_seli8_defconfig
View File

@ -8,9 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8"
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8" CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@ -78,7 +76,9 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BOOTCOUNT_BE=y
CONFIG_DDR_CLK_FREQ=50000000 CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_I2C_LEGACY=y CONFIG_DM_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set # CONFIG_MMC is not set
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_NOR_FLASH=y

8
configs/pg_wcom_seli8_update_defconfig
View File

@ -8,9 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8"
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8" CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@ -76,7 +74,9 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BOOTCOUNT_BE=y
CONFIG_DDR_CLK_FREQ=50000000 CONFIG_DDR_CLK_FREQ=50000000
CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_I2C_LEGACY=y CONFIG_DM_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set # CONFIG_MMC is not set
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_NOR_FLASH=y

3
configs/pxm2_defconfig
View File

@ -89,7 +89,8 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_I2C_LEGACY=y CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SPEED=400000 CONFIG_SYS_I2C_SPEED=400000
# CONFIG_SPL_DM_MMC is not set # CONFIG_SPL_DM_MMC is not set

2
drivers/i2c/Kconfig
View File

@ -771,7 +771,7 @@ config SYS_I2C_BUS_MAX
int "Max I2C busses" int "Max I2C busses"
depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
default 3 if OMAP34XX || AM33XX || AM43XX default 3 if OMAP34XX || AM33XX || AM43XX
default 4 if ARCH_SOCFPGA || OMAP44XX default 4 if ARCH_SOCFPGA
default 5 if OMAP54XX default 5 if OMAP54XX
help help
Define the maximum number of available I2C buses. Define the maximum number of available I2C buses.

2
drivers/mmc/Kconfig
View File

@ -406,7 +406,7 @@ config MMC_OMAP36XX_PINS
config HSMMC2_8BIT config HSMMC2_8BIT
bool "Enable 8-bit interface for eMMC (interface #2)" bool "Enable 8-bit interface for eMMC (interface #2)"
depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \ depends on MMC_OMAP_HS && (OMAP54XX || DRA7XX || AM33XX || \
AM43XX || ARCH_KEYSTONE) AM43XX || ARCH_KEYSTONE)
config SH_MMCIF config SH_MMCIF

13
drivers/mmc/omap_hsmmc.c
View File

@ -30,7 +30,7 @@
#include <mmc.h> #include <mmc.h>
#include <part.h> #include <part.h>
#include <i2c.h> #include <i2c.h>
#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) #if defined(CONFIG_OMAP54XX)
#include <palmas.h> #include <palmas.h>
#endif #endif
#include <asm/cache.h> #include <asm/cache.h>
@ -270,8 +270,7 @@ static unsigned char mmc_board_init(struct mmc *mmc)
&prcm_base->iclken1_core); &prcm_base->iclken1_core);
#endif #endif
#if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\ #if defined(CONFIG_OMAP54XX) && !CONFIG_IS_ENABLED(DM_REGULATOR)
!CONFIG_IS_ENABLED(DM_REGULATOR)
/* PBIAS config needed for MMC1 only */ /* PBIAS config needed for MMC1 only */
if (mmc_get_blk_desc(mmc)->devnum == 0) if (mmc_get_blk_desc(mmc)->devnum == 0)
vmmc_pbias_config(LDO_VOLT_3V3); vmmc_pbias_config(LDO_VOLT_3V3);
@ -541,8 +540,7 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
#if CONFIG_IS_ENABLED(DM_REGULATOR) #if CONFIG_IS_ENABLED(DM_REGULATOR)
return omap_hsmmc_set_io_regulator(mmc, mv); return omap_hsmmc_set_io_regulator(mmc, mv);
#elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \ #elif defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
defined(CONFIG_PALMAS_POWER)
if (mmc_get_blk_desc(mmc)->devnum == 0) if (mmc_get_blk_desc(mmc)->devnum == 0)
vmmc_pbias_config(palmas_ldo_volt); vmmc_pbias_config(palmas_ldo_volt);
return 0; return 0;
@ -905,8 +903,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
* 3. Wait until the SRC (SRD) bit returns to 0x0 * 3. Wait until the SRC (SRD) bit returns to 0x0
* (reset procedure is completed). * (reset procedure is completed).
*/ */
#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ #if defined(CONFIG_OMAP54XX) || defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
if (!(readl(&mmc_base->sysctl) & bit)) { if (!(readl(&mmc_base->sysctl) & bit)) {
start = get_timer(0); start = get_timer(0);
while (!(readl(&mmc_base->sysctl) & bit)) { while (!(readl(&mmc_base->sysctl) & bit)) {
@ -1556,7 +1553,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
#ifdef OMAP_HSMMC2_BASE #ifdef OMAP_HSMMC2_BASE
case 1: case 1:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ #if (defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \ defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT) defined(CONFIG_HSMMC2_8BIT)

4
drivers/power/Kconfig
View File

@ -443,10 +443,6 @@ config TWL4030_POWER
The TWL4030 in a combination audio CODEC/power management with The TWL4030 in a combination audio CODEC/power management with
GPIO and it is commonly used with the OMAP3 family of processors GPIO and it is commonly used with the OMAP3 family of processors
config TWL6030_POWER
depends on OMAP44XX
bool "Enable driver for TI TWL6030 power management chip"
config POWER_MT6323 config POWER_MT6323
bool "Poweroff driver for mediatek mt6323" bool "Poweroff driver for mediatek mt6323"
select CMD_POWEROFF select CMD_POWEROFF

1
drivers/power/Makefile
View File

@ -22,7 +22,6 @@ obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_SY8106A_POWER) += sy8106a.o obj-$(CONFIG_SY8106A_POWER) += sy8106a.o
obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
obj-$(CONFIG_TWL4030_POWER) += twl4030.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o
obj-$(CONFIG_TWL6030_POWER) += twl6030.o
obj-$(CONFIG_PALMAS_POWER) += palmas.o obj-$(CONFIG_PALMAS_POWER) += palmas.o
obj-$(CONFIG_$(SPL_TPL_)POWER_LEGACY) += power_core.o obj-$(CONFIG_$(SPL_TPL_)POWER_LEGACY) += power_core.o
obj-$(CONFIG_DIALOG_POWER) += power_dialog.o obj-$(CONFIG_DIALOG_POWER) += power_dialog.o

310
drivers/power/twl6030.c
View File

@ -1,310 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*/
#include <config.h>
#include <linux/delay.h>
#include <linux/printk.h>
#include <twl6030.h>
static struct twl6030_data *twl;
static struct twl6030_data twl6030_info = {
.chip_type = chip_TWL6030,
.adc_rbase = GPCH0_LSB,
.adc_ctrl = CTRL_P2,
.adc_enable = CTRL_P2_SP2,
.vbat_mult = TWL6030_VBAT_MULT,
.vbat_shift = TWL6030_VBAT_SHIFT,
};
static struct twl6030_data twl6032_info = {
.chip_type = chip_TWL6032,
.adc_rbase = TWL6032_GPCH0_LSB,
.adc_ctrl = TWL6032_CTRL_P1,
.adc_enable = CTRL_P1_SP1,
.vbat_mult = TWL6032_VBAT_MULT,
.vbat_shift = TWL6032_VBAT_SHIFT,
};
static int twl6030_gpadc_read_channel(u8 channel_no)
{
u8 lsb = 0;
u8 msb = 0;
int ret = 0;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
twl->adc_rbase + channel_no * 2, &lsb);
if (ret)
return ret;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
twl->adc_rbase + 1 + channel_no * 2, &msb);
if (ret)
return ret;
return (msb << 8) | lsb;
}
static int twl6030_gpadc_sw2_trigger(void)
{
u8 val;
int ret = 0;
ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
twl->adc_ctrl, twl->adc_enable);
if (ret)
return ret;
/* Waiting until the SW1 conversion ends*/
val = CTRL_P2_BUSY;
while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
twl->adc_ctrl, &val);
if (ret)
return ret;
udelay(1000);
}
return 0;
}
void twl6030_power_off(void)
{
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_PHOENIX_DEV_ON,
TWL6030_PHOENIX_APP_DEVOFF | TWL6030_PHOENIX_CON_DEVOFF |
TWL6030_PHOENIX_MOD_DEVOFF);
}
void twl6030_stop_usb_charging(void)
{
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1, 0);
return;
}
void twl6030_start_usb_charging(void)
{
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
CHARGERUSB_VICHRG, CHARGERUSB_VICHRG_1500);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
CHARGERUSB_CINLIMIT, CHARGERUSB_CIN_LIMIT_NONE);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
CONTROLLER_INT_MASK, MBAT_TEMP);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
CHARGERUSB_INT_MASK, MASK_MCHARGERUSB_THMREG);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
CHARGERUSB_VOREG, CHARGERUSB_VOREG_4P0);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
CHARGERUSB_CTRL2, CHARGERUSB_CTRL2_VITERM_400);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL1, TERM);
/* Enable USB charging */
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
CONTROLLER_CTRL1, CONTROLLER_CTRL1_EN_CHARGER);
return;
}
int twl6030_get_battery_current(void)
{
int battery_current = 0;
u8 msb = 0;
u8 lsb = 0;
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_11, &msb);
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_10, &lsb);
battery_current = ((msb << 8) | lsb);
/* convert 10 bit signed number to 16 bit signed number */
if (battery_current >= 0x2000)
battery_current = (battery_current - 0x4000);
battery_current = battery_current * 3000 / 4096;
printf("Battery Current: %d mA\n", battery_current);
return battery_current;
}
int twl6030_get_battery_voltage(void)
{
int battery_volt = 0;
int ret = 0;
u8 vbatch;
if (twl->chip_type == chip_TWL6030) {
vbatch = TWL6030_GPADC_VBAT_CHNL;
} else {
ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
TWL6032_GPSELECT_ISB,
TWL6032_GPADC_VBAT_CHNL);
if (ret)
return ret;
vbatch = 0;
}
/* Start GPADC SW conversion */
ret = twl6030_gpadc_sw2_trigger();
if (ret) {
printf("Failed to convert battery voltage\n");
return ret;
}
/* measure Vbat voltage */
battery_volt = twl6030_gpadc_read_channel(vbatch);
if (battery_volt < 0) {
printf("Failed to read battery voltage\n");
return ret;
}
battery_volt = (battery_volt * twl->vbat_mult) >> twl->vbat_shift;
printf("Battery Voltage: %d mV\n", battery_volt);
return battery_volt;
}
void twl6030_init_battery_charging(void)
{
u8 val = 0;
int battery_volt = 0;
int ret = 0;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_USB, USB_PRODUCT_ID_LSB, &val);
if (ret) {
puts("twl6030_init_battery_charging(): could not determine chip!\n");
return;
}
if (val == 0x30) {
twl = &twl6030_info;
} else if (val == 0x32) {
twl = &twl6032_info;
} else {
puts("twl6030_init_battery_charging(): unsupported chip type\n");
return;
}
/* Enable VBAT measurement */
if (twl->chip_type == chip_TWL6030) {
twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
TWL6030_GPADC_CTRL,
GPADC_CTRL_SCALER_DIV4);
} else {
twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
TWL6032_GPADC_CTRL2,
GPADC_CTRL2_CH18_SCALER_EN);
}
/* Enable GPADC module */
ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS);
if (ret) {
printf("Failed to enable GPADC\n");
return;
}
battery_volt = twl6030_get_battery_voltage();
if (battery_volt < 0)
return;
if (battery_volt < 3000)
printf("Main battery voltage too low!\n");
/* Check for the presence of USB charger */
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &val);
/* check for battery presence indirectly via Fuel gauge */
if ((val & VBUS_DET) && (battery_volt < 3300))
twl6030_start_usb_charging();
return;
}
void twl6030_power_mmc_init(int dev_index)
{
u8 value = 0;
if (dev_index == 0) {
/* 3.0V voltage output for VMMC */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VMMC_CFG_VOLTAGE,
TWL6030_CFG_VOLTAGE_30);
/* Enable P1 output for VMMC */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VMMC_CFG_STATE,
TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON);
} else if (dev_index == 1) {
twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_PH_STS_BOOT,
&value);
/* BOOT2 indicates 1.8V/2.8V VAUX1 for eMMC */
if (value & TWL6030_PH_STS_BOOT2) {
/* 1.8V voltage output for VAUX1 */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VAUX1_CFG_VOLTAGE,
TWL6030_CFG_VOLTAGE_18);
} else {
/* 2.8V voltage output for VAUX1 */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VAUX1_CFG_VOLTAGE,
TWL6030_CFG_VOLTAGE_28);
}
/* Enable P1 output for VAUX */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VAUX1_CFG_STATE,
TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON);
}
}
void twl6030_usb_device_settings()
{
u8 value = 0;
/* 3.3V voltage output for VUSB */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VUSB_CFG_VOLTAGE,
TWL6030_CFG_VOLTAGE_33);
/* Enable P1 output for VUSB */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VUSB_CFG_STATE,
TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON);
/* Select the input supply for VUSB regulator */
twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_MISC2, &value);
value |= TWL6030_MISC2_VUSB_IN_VSYS;
value &= ~TWL6030_MISC2_VUSB_IN_PMID;
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_MISC2, value);
}
#if CONFIG_IS_ENABLED(DM_I2C)
int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev);
if (ret) {
pr_err("unable to get I2C bus. ret %d\n", ret);
return ret;
}
ret = dm_i2c_reg_write(dev, reg, val);
if (ret) {
pr_err("writing to twl6030 failed. ret %d\n", ret);
return ret;
}
return 0;
}
int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev);
if (ret) {
pr_err("unable to get I2C bus. ret %d\n", ret);
return ret;
}
ret = dm_i2c_reg_read(dev, reg);
if (ret < 0) {
pr_err("reading from twl6030 failed. ret %d\n", ret);
return ret;
}
*valp = (u8)ret;
return 0;
}
#endif

3
drivers/serial/ns16550.c
View File

@ -227,8 +227,7 @@ static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
void ns16550_init(struct ns16550 *com_port, int baud_divisor) void ns16550_init(struct ns16550 *com_port, int baud_divisor)
{ {
#if (defined(CONFIG_SPL_BUILD) && \ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX)
(defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
/* /*
* On some OMAP3/OMAP4 devices when UART3 is configured for boot mode * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
* before SPL starts only THRE bit is set. We have to empty the * before SPL starts only THRE bit is set. We have to empty the

4
drivers/usb/musb-new/linux-compat.h
View File

@ -19,8 +19,4 @@
#define CFG_SOC_OMAP3430 #define CFG_SOC_OMAP3430
#endif #endif
#ifdef CONFIG_OMAP44XX
#define CFG_ARCH_OMAP4
#endif
#endif /* __LINUX_COMPAT_H__ */ #endif /* __LINUX_COMPAT_H__ */

2
drivers/usb/musb-new/musb_core.c
View File

@ -1520,7 +1520,7 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
#if defined(CONFIG_SOC_OMAP2430) || defined(CFG_SOC_OMAP3430) || \ #if defined(CONFIG_SOC_OMAP2430) || defined(CFG_SOC_OMAP3430) || \
defined(CFG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) defined(CONFIG_ARCH_U8500)
static irqreturn_t generic_interrupt(int irq, void *__hci) static irqreturn_t generic_interrupt(int irq, void *__hci)
{ {

2
drivers/usb/musb-new/musb_core.h
View File

@ -150,7 +150,7 @@ enum musb_g_ep0_state {
*/ */
#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \ #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
|| defined(CFG_SOC_OMAP3430) || defined(CFG_ARCH_OMAP4) || defined(CFG_SOC_OMAP3430)
/* REVISIT indexed access seemed to /* REVISIT indexed access seemed to
* misbehave (on DaVinci) for at least peripheral IN ... * misbehave (on DaVinci) for at least peripheral IN ...
*/ */

12
drivers/usb/musb-new/omap2430.c
View File

@ -21,7 +21,6 @@
#include <asm/omap_common.h> #include <asm/omap_common.h>
#include <asm/omap_musb.h> #include <asm/omap_musb.h>
#include <twl4030.h> #include <twl4030.h>
#include <twl6030.h>
#include "linux-compat.h" #include "linux-compat.h"
#include "musb_core.h" #include "musb_core.h"
#include "omap2430.h" #include "omap2430.h"
@ -104,17 +103,6 @@ static int omap2430_musb_enable(struct musb *musb)
__PRETTY_FUNCTION__); __PRETTY_FUNCTION__);
} }
#endif #endif
#ifdef CONFIG_TWL6030_POWER
twl6030_usb_device_settings();
#endif
#ifdef CONFIG_OMAP44XX
u32 *usbotghs_control = (u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = USBOTGHS_CONTROL_AVALID |
USBOTGHS_CONTROL_VBUSVALID | USBOTGHS_CONTROL_IDDIG;
#endif
return 0; return 0;
} }

15
drivers/usb/musb/omap3.c
View File

@ -19,7 +19,6 @@
#include <serial.h> #include <serial.h>
#include <asm/omap_common.h> #include <asm/omap_common.h>
#include <twl4030.h> #include <twl4030.h>
#include <twl6030.h>
#include "omap3.h" #include "omap3.h"
static int platform_needs_initialization = 1; static int platform_needs_initialization = 1;
@ -54,12 +53,7 @@ static struct omap3_otg_regs *otg;
#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001 #define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001
/* OMAP4430 has an internal PHY, use it */
#ifdef CONFIG_OMAP44XX
#define OMAP3_OTG_INTERFSEL_OMAP 0x0000
#else
#define OMAP3_OTG_INTERFSEL_OMAP 0x0001 #define OMAP3_OTG_INTERFSEL_OMAP 0x0001
#endif
#define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001 #define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001
@ -99,10 +93,6 @@ int musb_platform_init(void)
} }
#endif #endif
#ifdef CONFIG_TWL6030_POWER
twl6030_usb_device_settings();
#endif
otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE; otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE;
/* Set OTG to always be on */ /* Set OTG to always be on */
@ -121,11 +111,6 @@ int musb_platform_init(void)
musb_cfg.extvbus = omap3_evm_need_extvbus(); musb_cfg.extvbus = omap3_evm_need_extvbus();
#endif #endif
#ifdef CONFIG_OMAP44XX
u32 *usbotghs_control =
(u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = 0x15;
#endif
platform_needs_initialization = 0; platform_needs_initialization = 0;
} }

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