From f72d3d6b04d21a7b2ba7ba9ee551dd6f1a9b93e4 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 9 Nov 2020 15:55:49 +0800 Subject: [PATCH 1/3] x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit() Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"), the maximum number of variable range MTRRs was increased from 8 to 10. On the BayTrail platform there are only 8 variable range MTRRs. In mtrr_commit() it still uses MTRR_MAX_COUNT which caused a #GP during VESA video driver probe. It should have been updated to use dynamically probed number. This fixes the boot failure seen on Intel Minnow Max board. Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs") Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/mtrr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 5180eb06fcd..6f095c53a57 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -158,7 +158,7 @@ int mtrr_commit(bool do_caches) /* Clear the ones that are unused */ debug("clear\n"); - for (; i < MTRR_MAX_COUNT; i++) + for (; i < mtrr_get_var_count(); i++) wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); debug("close\n"); mtrr_close(&state, do_caches); From 6486eaa0243826e46ee629599146c205e57590e2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 9 Nov 2020 06:41:38 -0700 Subject: [PATCH 2/3] x86: coral: Correct max98357 file This somehow ended up as an empty file. Fix it. Signed-off-by: Simon Glass Acked-by: Bin Meng --- .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b0b5b9ba648c4546f98e15e42356a5fc4af6bb27 100644 GIT binary patch literal 116 zcmZQzU|?WnWOx?=qy_%}|BnyXGahJUU??~MR0;$VT+Bccgqa+G1PJi6vnv28CMf>T R&%gk}Aix2{5 Date: Mon, 9 Nov 2020 07:12:23 -0700 Subject: [PATCH 3/3] x86: coral: Update smbios tables to latest definition The accepted binding uses multiple nodes, one for each table type. Update coral accordingly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/dts/chromebook_coral.dts | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 43f4b33da1b..d66e128ae62 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -55,12 +55,27 @@ write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; smbios { - manufacturer = "Google"; - product = "Coral"; - version = "rev2"; - serial = "123456789"; - sku = "sku3"; - family = "Google_Coral"; + /* Type 1 table */ + system { + manufacturer = "Google"; + product = "Coral"; + version = "rev2"; + serial = "123456789"; + sku = "sku3"; + family = "Google_Coral"; + }; + + /* Type 2 table */ + baseboard { + manufacturer = "Google"; + product = "Coral"; + asset-tag = "ABC123"; + }; + + /* Type 3 table */ + chassis { + manufacturer = "Google"; + }; }; };