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include/dt-bindings: Remove identical headers

Browse Source 
As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and are currently identical to the versions in dts/upstream.
We can remove these now to prevent future conflicts.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2025-05-27 16:18:34 -06:00
parent ceeda322e7
commit f335f5265b
90 changed files with 0 additions and 6768 deletions
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15
include/dt-bindings/arm/ux500_pm_domains.h
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@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 Linaro Ltd.
*
* Author: Ulf Hansson <ulf.hansson@linaro.org>
*/
#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
#define DOMAIN_VAPE 0
/* Number of PM domains. */
#define NR_DOMAINS (DOMAIN_VAPE + 1)
#endif

16
include/dt-bindings/bus/moxtet.h
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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Constant for device tree bindings for Turris Mox module configuration bus
*
* Copyright (C) 2019 Marek Behún <kabel@kernel.org>
*/
#ifndef _DT_BINDINGS_BUS_MOXTET_H
#define _DT_BINDINGS_BUS_MOXTET_H
#define MOXTET_IRQ_PCI 0
#define MOXTET_IRQ_USB3 4
#define MOXTET_IRQ_PERIDOT(n) (8 + (n))
#define MOXTET_IRQ_TOPAZ 12
#endif /* _DT_BINDINGS_BUS_MOXTET_H */

118
include/dt-bindings/clock/actions,s700-cmu.h
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@ -1,118 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Device Tree binding constants for Actions Semi S700 Clock Management Unit
*
* Copyright (c) 2014 Actions Semi Inc.
* Author: David Liu <liuwei@actions-semi.com>
*
* Author: Pathiban Nallathambi <pn@denx.de>
* Author: Saravanan Sekar <sravanhome@gmail.com>
*/
#ifndef __DT_BINDINGS_CLOCK_S700_H
#define __DT_BINDINGS_CLOCK_S700_H
#define CLK_NONE 0
/* pll clocks */
#define CLK_CORE_PLL 1
#define CLK_DEV_PLL 2
#define CLK_DDR_PLL 3
#define CLK_NAND_PLL 4
#define CLK_DISPLAY_PLL 5
#define CLK_TVOUT_PLL 6
#define CLK_CVBS_PLL 7
#define CLK_AUDIO_PLL 8
#define CLK_ETHERNET_PLL 9
/* system clock */
#define CLK_CPU 10
#define CLK_DEV 11
#define CLK_AHB 12
#define CLK_APB 13
#define CLK_DMAC 14
#define CLK_NOC0_CLK_MUX 15
#define CLK_NOC1_CLK_MUX 16
#define CLK_HP_CLK_MUX 17
#define CLK_HP_CLK_DIV 18
#define CLK_NOC1_CLK_DIV 19
#define CLK_NOC0 20
#define CLK_NOC1 21
#define CLK_SENOR_SRC 22
/* peripheral device clock */
#define CLK_GPIO 23
#define CLK_TIMER 24
#define CLK_DSI 25
#define CLK_CSI 26
#define CLK_SI 27
#define CLK_DE 28
#define CLK_HDE 29
#define CLK_VDE 30
#define CLK_VCE 31
#define CLK_NAND 32
#define CLK_SD0 33
#define CLK_SD1 34
#define CLK_SD2 35
#define CLK_UART0 36
#define CLK_UART1 37
#define CLK_UART2 38
#define CLK_UART3 39
#define CLK_UART4 40
#define CLK_UART5 41
#define CLK_UART6 42
#define CLK_PWM0 43
#define CLK_PWM1 44
#define CLK_PWM2 45
#define CLK_PWM3 46
#define CLK_PWM4 47
#define CLK_PWM5 48
#define CLK_GPU3D 49
#define CLK_I2C0 50
#define CLK_I2C1 51
#define CLK_I2C2 52
#define CLK_I2C3 53
#define CLK_SPI0 54
#define CLK_SPI1 55
#define CLK_SPI2 56
#define CLK_SPI3 57
#define CLK_USB3_480MPLL0 58
#define CLK_USB3_480MPHY0 59
#define CLK_USB3_5GPHY 60
#define CLK_USB3_CCE 61
#define CLK_USB3_MAC 62
#define CLK_LCD 63
#define CLK_HDMI_AUDIO 64
#define CLK_I2SRX 65
#define CLK_I2STX 66
#define CLK_SENSOR0 67
#define CLK_SENSOR1 68
#define CLK_HDMI_DEV 69
#define CLK_ETHERNET 70
#define CLK_RMII_REF 71
#define CLK_USB2H0_PLLEN 72
#define CLK_USB2H0_PHY 73
#define CLK_USB2H0_CCE 74
#define CLK_USB2H1_PLLEN 75
#define CLK_USB2H1_PHY 76
#define CLK_USB2H1_CCE 77
#define CLK_TVOUT 78
#define CLK_THERMAL_SENSOR 79
#define CLK_IRC_SWITCH 80
#define CLK_PCM1 81
#define CLK_NR_CLKS (CLK_PCM1 + 1)
#endif /* __DT_BINDINGS_CLOCK_S700_H */

129
include/dt-bindings/clock/actions,s900-cmu.h
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@ -1,129 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Device Tree binding constants for Actions Semi S900 Clock Management Unit
//
// Copyright (c) 2014 Actions Semi Inc.
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
#define __DT_BINDINGS_CLOCK_S900_CMU_H
#define CLK_NONE 0
/* fixed rate clocks */
#define CLK_LOSC 1
#define CLK_HOSC 2
/* pll clocks */
#define CLK_CORE_PLL 3
#define CLK_DEV_PLL 4
#define CLK_DDR_PLL 5
#define CLK_NAND_PLL 6
#define CLK_DISPLAY_PLL 7
#define CLK_DSI_PLL 8
#define CLK_ASSIST_PLL 9
#define CLK_AUDIO_PLL 10
/* system clock */
#define CLK_CPU 15
#define CLK_DEV 16
#define CLK_NOC 17
#define CLK_NOC_MUX 18
#define CLK_NOC_DIV 19
#define CLK_AHB 20
#define CLK_APB 21
#define CLK_DMAC 22
/* peripheral device clock */
#define CLK_GPIO 23
#define CLK_BISP 24
#define CLK_CSI0 25
#define CLK_CSI1 26
#define CLK_DE0 27
#define CLK_DE1 28
#define CLK_DE2 29
#define CLK_DE3 30
#define CLK_DSI 32
#define CLK_GPU 33
#define CLK_GPU_CORE 34
#define CLK_GPU_MEM 35
#define CLK_GPU_SYS 36
#define CLK_HDE 37
#define CLK_I2C0 38
#define CLK_I2C1 39
#define CLK_I2C2 40
#define CLK_I2C3 41
#define CLK_I2C4 42
#define CLK_I2C5 43
#define CLK_I2SRX 44
#define CLK_I2STX 45
#define CLK_IMX 46
#define CLK_LCD 47
#define CLK_NAND0 48
#define CLK_NAND1 49
#define CLK_PWM0 50
#define CLK_PWM1 51
#define CLK_PWM2 52
#define CLK_PWM3 53
#define CLK_PWM4 54
#define CLK_PWM5 55
#define CLK_SD0 56
#define CLK_SD1 57
#define CLK_SD2 58
#define CLK_SD3 59
#define CLK_SENSOR 60
#define CLK_SPEED_SENSOR 61
#define CLK_SPI0 62
#define CLK_SPI1 63
#define CLK_SPI2 64
#define CLK_SPI3 65
#define CLK_THERMAL_SENSOR 66
#define CLK_UART0 67
#define CLK_UART1 68
#define CLK_UART2 69
#define CLK_UART3 70
#define CLK_UART4 71
#define CLK_UART5 72
#define CLK_UART6 73
#define CLK_VCE 74
#define CLK_VDE 75
#define CLK_USB3_480MPLL0 76
#define CLK_USB3_480MPHY0 77
#define CLK_USB3_5GPHY 78
#define CLK_USB3_CCE 79
#define CLK_USB3_MAC 80
#define CLK_TIMER 83
#define CLK_HDMI_AUDIO 84
#define CLK_24M 85
#define CLK_EDP 86
#define CLK_24M_EDP 87
#define CLK_EDP_PLL 88
#define CLK_EDP_LINK 89
#define CLK_USB2H0_PLLEN 90
#define CLK_USB2H0_PHY 91
#define CLK_USB2H0_CCE 92
#define CLK_USB2H1_PLLEN 93
#define CLK_USB2H1_PHY 94
#define CLK_USB2H1_CCE 95
#define CLK_DDR0 96
#define CLK_DDR1 97
#define CLK_DMM 98
#define CLK_ETH_MAC 99
#define CLK_RMII_REF 100
#define CLK_NR_CLKS (CLK_RMII_REF + 1)
#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */

51
include/dt-bindings/clock/bcm-nsp.h
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@ -1,51 +0,0 @@
/*
* BSD LICENSE
*
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CLOCK_BCM_NSP_H
#define _CLOCK_BCM_NSP_H
/* GENPLL clock channel ID */
#define BCM_NSP_GENPLL 0
#define BCM_NSP_GENPLL_PHY_CLK 1
#define BCM_NSP_GENPLL_ENET_SW_CLK 2
#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
#define BCM_NSP_GENPLL_SATA1_CLK 5
#define BCM_NSP_GENPLL_SATA2_CLK 6
/* LCPLL0 clock channel ID */
#define BCM_NSP_LCPLL0 0
#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
#define BCM_NSP_LCPLL0_SDIO_CLK 2
#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
#endif /* _CLOCK_BCM_NSP_H */

9
include/dt-bindings/clock/bcm2835-aux.h
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 Broadcom Corporation
*/
#define BCM2835_AUX_CLOCK_UART 0
#define BCM2835_AUX_CLOCK_SPI1 1
#define BCM2835_AUX_CLOCK_SPI2 2
#define BCM2835_AUX_CLOCK_COUNT 3

62
include/dt-bindings/clock/bcm2835.h
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@ -1,62 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 Broadcom Corporation
*/
#define BCM2835_PLLA 0
#define BCM2835_PLLB 1
#define BCM2835_PLLC 2
#define BCM2835_PLLD 3
#define BCM2835_PLLH 4
#define BCM2835_PLLA_CORE 5
#define BCM2835_PLLA_PER 6
#define BCM2835_PLLB_ARM 7
#define BCM2835_PLLC_CORE0 8
#define BCM2835_PLLC_CORE1 9
#define BCM2835_PLLC_CORE2 10
#define BCM2835_PLLC_PER 11
#define BCM2835_PLLD_CORE 12
#define BCM2835_PLLD_PER 13
#define BCM2835_PLLH_RCAL 14
#define BCM2835_PLLH_AUX 15
#define BCM2835_PLLH_PIX 16
#define BCM2835_CLOCK_TIMER 17
#define BCM2835_CLOCK_OTP 18
#define BCM2835_CLOCK_UART 19
#define BCM2835_CLOCK_VPU 20
#define BCM2835_CLOCK_V3D 21
#define BCM2835_CLOCK_ISP 22
#define BCM2835_CLOCK_H264 23
#define BCM2835_CLOCK_VEC 24
#define BCM2835_CLOCK_HSM 25
#define BCM2835_CLOCK_SDRAM 26
#define BCM2835_CLOCK_TSENS 27
#define BCM2835_CLOCK_EMMC 28
#define BCM2835_CLOCK_PERI_IMAGE 29
#define BCM2835_CLOCK_PWM 30
#define BCM2835_CLOCK_PCM 31
#define BCM2835_PLLA_DSI0 32
#define BCM2835_PLLA_CCP2 33
#define BCM2835_PLLD_DSI0 34
#define BCM2835_PLLD_DSI1 35
#define BCM2835_CLOCK_AVEO 36
#define BCM2835_CLOCK_DFT 37
#define BCM2835_CLOCK_GP0 38
#define BCM2835_CLOCK_GP1 39
#define BCM2835_CLOCK_GP2 40
#define BCM2835_CLOCK_SLIM 41
#define BCM2835_CLOCK_SMI 42
#define BCM2835_CLOCK_TEC 43
#define BCM2835_CLOCK_DPI 44
#define BCM2835_CLOCK_CAM0 45
#define BCM2835_CLOCK_CAM1 46
#define BCM2835_CLOCK_DSI0E 47
#define BCM2835_CLOCK_DSI1E 48
#define BCM2835_CLOCK_DSI0P 49
#define BCM2835_CLOCK_DSI1P 50
#define BCM2711_CLOCK_EMMC2 51

15
include/dt-bindings/clock/fsl,qoriq-clockgen.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
#define QORIQ_CLK_SYSCLK 0
#define QORIQ_CLK_CMUX 1
#define QORIQ_CLK_HWACCEL 2
#define QORIQ_CLK_FMAN 3
#define QORIQ_CLK_PLATFORM_PLL 4
#define QORIQ_CLK_CORECLK 5
#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */

214
include/dt-bindings/clock/hi3660-clock.h
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@ -1,214 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2016-2017 Linaro Ltd.
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*/
#ifndef __DTS_HI3660_CLOCK_H
#define __DTS_HI3660_CLOCK_H
/* fixed rate clocks */
#define HI3660_CLKIN_SYS 0
#define HI3660_CLKIN_REF 1
#define HI3660_CLK_FLL_SRC 2
#define HI3660_CLK_PPLL0 3
#define HI3660_CLK_PPLL1 4
#define HI3660_CLK_PPLL2 5
#define HI3660_CLK_PPLL3 6
#define HI3660_CLK_SCPLL 7
#define HI3660_PCLK 8
#define HI3660_CLK_UART0_DBG 9
#define HI3660_CLK_UART6 10
#define HI3660_OSC32K 11
#define HI3660_OSC19M 12
#define HI3660_CLK_480M 13
#define HI3660_CLK_INV 14
/* clk in crgctrl */
#define HI3660_FACTOR_UART3 15
#define HI3660_CLK_FACTOR_MMC 16
#define HI3660_CLK_GATE_I2C0 17
#define HI3660_CLK_GATE_I2C1 18
#define HI3660_CLK_GATE_I2C2 19
#define HI3660_CLK_GATE_I2C6 20
#define HI3660_CLK_DIV_SYSBUS 21
#define HI3660_CLK_DIV_320M 22
#define HI3660_CLK_DIV_A53 23
#define HI3660_CLK_GATE_SPI0 24
#define HI3660_CLK_GATE_SPI2 25
#define HI3660_PCIEPHY_REF 26
#define HI3660_CLK_ABB_USB 27
#define HI3660_HCLK_GATE_SDIO0 28
#define HI3660_HCLK_GATE_SD 29
#define HI3660_CLK_GATE_AOMM 30
#define HI3660_PCLK_GPIO0 31
#define HI3660_PCLK_GPIO1 32
#define HI3660_PCLK_GPIO2 33
#define HI3660_PCLK_GPIO3 34
#define HI3660_PCLK_GPIO4 35
#define HI3660_PCLK_GPIO5 36
#define HI3660_PCLK_GPIO6 37
#define HI3660_PCLK_GPIO7 38
#define HI3660_PCLK_GPIO8 39
#define HI3660_PCLK_GPIO9 40
#define HI3660_PCLK_GPIO10 41
#define HI3660_PCLK_GPIO11 42
#define HI3660_PCLK_GPIO12 43
#define HI3660_PCLK_GPIO13 44
#define HI3660_PCLK_GPIO14 45
#define HI3660_PCLK_GPIO15 46
#define HI3660_PCLK_GPIO16 47
#define HI3660_PCLK_GPIO17 48
#define HI3660_PCLK_GPIO18 49
#define HI3660_PCLK_GPIO19 50
#define HI3660_PCLK_GPIO20 51
#define HI3660_PCLK_GPIO21 52
#define HI3660_CLK_GATE_SPI3 53
#define HI3660_CLK_GATE_I2C7 54
#define HI3660_CLK_GATE_I2C3 55
#define HI3660_CLK_GATE_SPI1 56
#define HI3660_CLK_GATE_UART1 57
#define HI3660_CLK_GATE_UART2 58
#define HI3660_CLK_GATE_UART4 59
#define HI3660_CLK_GATE_UART5 60
#define HI3660_CLK_GATE_I2C4 61
#define HI3660_CLK_GATE_DMAC 62
#define HI3660_PCLK_GATE_DSS 63
#define HI3660_ACLK_GATE_DSS 64
#define HI3660_CLK_GATE_LDI1 65
#define HI3660_CLK_GATE_LDI0 66
#define HI3660_CLK_GATE_VIVOBUS 67
#define HI3660_CLK_GATE_EDC0 68
#define HI3660_CLK_GATE_TXDPHY0_CFG 69
#define HI3660_CLK_GATE_TXDPHY0_REF 70
#define HI3660_CLK_GATE_TXDPHY1_CFG 71
#define HI3660_CLK_GATE_TXDPHY1_REF 72
#define HI3660_ACLK_GATE_USB3OTG 73
#define HI3660_CLK_GATE_SPI4 74
#define HI3660_CLK_GATE_SD 75
#define HI3660_CLK_GATE_SDIO0 76
#define HI3660_CLK_GATE_UFS_SUBSYS 77
#define HI3660_PCLK_GATE_DSI0 78
#define HI3660_PCLK_GATE_DSI1 79
#define HI3660_ACLK_GATE_PCIE 80
#define HI3660_PCLK_GATE_PCIE_SYS 81
#define HI3660_CLK_GATE_PCIEAUX 82
#define HI3660_PCLK_GATE_PCIE_PHY 83
#define HI3660_CLK_ANDGT_LDI0 84
#define HI3660_CLK_ANDGT_LDI1 85
#define HI3660_CLK_ANDGT_EDC0 86
#define HI3660_CLK_GATE_UFSPHY_GT 87
#define HI3660_CLK_ANDGT_MMC 88
#define HI3660_CLK_ANDGT_SD 89
#define HI3660_CLK_A53HPM_ANDGT 90
#define HI3660_CLK_ANDGT_SDIO 91
#define HI3660_CLK_ANDGT_UART0 92
#define HI3660_CLK_ANDGT_UART1 93
#define HI3660_CLK_ANDGT_UARTH 94
#define HI3660_CLK_ANDGT_SPI 95
#define HI3660_CLK_VIVOBUS_ANDGT 96
#define HI3660_CLK_AOMM_ANDGT 97
#define HI3660_CLK_320M_PLL_GT 98
#define HI3660_AUTODIV_EMMC0BUS 99
#define HI3660_AUTODIV_SYSBUS 100
#define HI3660_CLK_GATE_UFSPHY_CFG 101
#define HI3660_CLK_GATE_UFSIO_REF 102
#define HI3660_CLK_MUX_SYSBUS 103
#define HI3660_CLK_MUX_UART0 104
#define HI3660_CLK_MUX_UART1 105
#define HI3660_CLK_MUX_UARTH 106
#define HI3660_CLK_MUX_SPI 107
#define HI3660_CLK_MUX_I2C 108
#define HI3660_CLK_MUX_MMC_PLL 109
#define HI3660_CLK_MUX_LDI1 110
#define HI3660_CLK_MUX_LDI0 111
#define HI3660_CLK_MUX_SD_PLL 112
#define HI3660_CLK_MUX_SD_SYS 113
#define HI3660_CLK_MUX_EDC0 114
#define HI3660_CLK_MUX_SDIO_SYS 115
#define HI3660_CLK_MUX_SDIO_PLL 116
#define HI3660_CLK_MUX_VIVOBUS 117
#define HI3660_CLK_MUX_A53HPM 118
#define HI3660_CLK_MUX_320M 119
#define HI3660_CLK_MUX_IOPERI 120
#define HI3660_CLK_DIV_UART0 121
#define HI3660_CLK_DIV_UART1 122
#define HI3660_CLK_DIV_UARTH 123
#define HI3660_CLK_DIV_MMC 124
#define HI3660_CLK_DIV_SD 125
#define HI3660_CLK_DIV_EDC0 126
#define HI3660_CLK_DIV_LDI0 127
#define HI3660_CLK_DIV_SDIO 128
#define HI3660_CLK_DIV_LDI1 129
#define HI3660_CLK_DIV_SPI 130
#define HI3660_CLK_DIV_VIVOBUS 131
#define HI3660_CLK_DIV_I2C 132
#define HI3660_CLK_DIV_UFSPHY 133
#define HI3660_CLK_DIV_CFGBUS 134
#define HI3660_CLK_DIV_MMC0BUS 135
#define HI3660_CLK_DIV_MMC1BUS 136
#define HI3660_CLK_DIV_UFSPERI 137
#define HI3660_CLK_DIV_AOMM 138
#define HI3660_CLK_DIV_IOPERI 139
#define HI3660_VENC_VOLT_HOLD 140
#define HI3660_PERI_VOLT_HOLD 141
#define HI3660_CLK_GATE_VENC 142
#define HI3660_CLK_GATE_VDEC 143
#define HI3660_CLK_ANDGT_VENC 144
#define HI3660_CLK_ANDGT_VDEC 145
#define HI3660_CLK_MUX_VENC 146
#define HI3660_CLK_MUX_VDEC 147
#define HI3660_CLK_DIV_VENC 148
#define HI3660_CLK_DIV_VDEC 149
#define HI3660_CLK_FAC_ISP_SNCLK 150
#define HI3660_CLK_GATE_ISP_SNCLK0 151
#define HI3660_CLK_GATE_ISP_SNCLK1 152
#define HI3660_CLK_GATE_ISP_SNCLK2 153
#define HI3660_CLK_ANGT_ISP_SNCLK 154
#define HI3660_CLK_MUX_ISP_SNCLK 155
#define HI3660_CLK_DIV_ISP_SNCLK 156
/* clk in pmuctrl */
#define HI3660_GATE_ABB_192 0
/* clk in pctrl */
#define HI3660_GATE_UFS_TCXO_EN 0
#define HI3660_GATE_USB_TCXO_EN 1
/* clk in sctrl */
#define HI3660_PCLK_AO_GPIO0 0
#define HI3660_PCLK_AO_GPIO1 1
#define HI3660_PCLK_AO_GPIO2 2
#define HI3660_PCLK_AO_GPIO3 3
#define HI3660_PCLK_AO_GPIO4 4
#define HI3660_PCLK_AO_GPIO5 5
#define HI3660_PCLK_AO_GPIO6 6
#define HI3660_PCLK_GATE_MMBUF 7
#define HI3660_CLK_GATE_DSS_AXI_MM 8
#define HI3660_PCLK_MMBUF_ANDGT 9
#define HI3660_CLK_MMBUF_PLL_ANDGT 10
#define HI3660_CLK_FLL_MMBUF_ANDGT 11
#define HI3660_CLK_SYS_MMBUF_ANDGT 12
#define HI3660_CLK_GATE_PCIEPHY_GT 13
#define HI3660_ACLK_MUX_MMBUF 14
#define HI3660_CLK_SW_MMBUF 15
#define HI3660_CLK_DIV_AOBUS 16
#define HI3660_PCLK_DIV_MMBUF 17
#define HI3660_ACLK_DIV_MMBUF 18
#define HI3660_CLK_DIV_PCIEPHY 19
/* clk in iomcu */
#define HI3660_CLK_I2C0_IOMCU 0
#define HI3660_CLK_I2C1_IOMCU 1
#define HI3660_CLK_I2C2_IOMCU 2
#define HI3660_CLK_I2C6_IOMCU 3
#define HI3660_CLK_IOMCU_PERI0 4
/* clk in stub clock */
#define HI3660_CLK_STUB_CLUSTER0 0
#define HI3660_CLK_STUB_CLUSTER1 1
#define HI3660_CLK_STUB_GPU 2
#define HI3660_CLK_STUB_DDR 3
#define HI3660_CLK_STUB_NUM 4
#endif /* __DTS_HI3660_CLOCK_H */

58
include/dt-bindings/clock/lpc32xx-clock.h
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/*
* Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
*
* This code is released using a dual license strategy: BSD/GPL
* You can choose the licence that better fits your requirements.
*
* Released under the terms of 3-clause BSD License
* Released under the terms of GNU General Public License Version 2.0
*
*/
#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
#define __DT_BINDINGS_LPC32XX_CLOCK_H
/* LPC32XX System Control Block clocks */
#define LPC32XX_CLK_RTC 1
#define LPC32XX_CLK_DMA 2
#define LPC32XX_CLK_MLC 3
#define LPC32XX_CLK_SLC 4
#define LPC32XX_CLK_LCD 5
#define LPC32XX_CLK_MAC 6
#define LPC32XX_CLK_SD 7
#define LPC32XX_CLK_DDRAM 8
#define LPC32XX_CLK_SSP0 9
#define LPC32XX_CLK_SSP1 10
#define LPC32XX_CLK_UART3 11
#define LPC32XX_CLK_UART4 12
#define LPC32XX_CLK_UART5 13
#define LPC32XX_CLK_UART6 14
#define LPC32XX_CLK_IRDA 15
#define LPC32XX_CLK_I2C1 16
#define LPC32XX_CLK_I2C2 17
#define LPC32XX_CLK_TIMER0 18
#define LPC32XX_CLK_TIMER1 19
#define LPC32XX_CLK_TIMER2 20
#define LPC32XX_CLK_TIMER3 21
#define LPC32XX_CLK_TIMER4 22
#define LPC32XX_CLK_TIMER5 23
#define LPC32XX_CLK_WDOG 24
#define LPC32XX_CLK_I2S0 25
#define LPC32XX_CLK_I2S1 26
#define LPC32XX_CLK_SPI1 27
#define LPC32XX_CLK_SPI2 28
#define LPC32XX_CLK_MCPWM 29
#define LPC32XX_CLK_HSTIMER 30
#define LPC32XX_CLK_KEY 31
#define LPC32XX_CLK_PWM1 32
#define LPC32XX_CLK_PWM2 33
#define LPC32XX_CLK_ADC 34
#define LPC32XX_CLK_HCLK_PLL 35
#define LPC32XX_CLK_PERIPH 36
/* LPC32XX USB clocks */
#define LPC32XX_USB_CLK_I2C 1
#define LPC32XX_USB_CLK_DEVICE 2
#define LPC32XX_USB_CLK_HOST 3
#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */

112
include/dt-bindings/clock/r7s72100-clock.h
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2014 Renesas Solutions Corp.
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
*/
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
#define __DT_BINDINGS_CLOCK_R7S72100_H__
#define R7S72100_CLK_PLL 0
#define R7S72100_CLK_I 1
#define R7S72100_CLK_G 2
/* MSTP2 */
#define R7S72100_CLK_CORESIGHT 0
/* MSTP3 */
#define R7S72100_CLK_IEBUS 7
#define R7S72100_CLK_IRDA 6
#define R7S72100_CLK_LIN0 5
#define R7S72100_CLK_LIN1 4
#define R7S72100_CLK_MTU2 3
#define R7S72100_CLK_CAN 2
#define R7S72100_CLK_ADCPWR 1
#define R7S72100_CLK_PWM 0
/* MSTP4 */
#define R7S72100_CLK_SCIF0 7
#define R7S72100_CLK_SCIF1 6
#define R7S72100_CLK_SCIF2 5
#define R7S72100_CLK_SCIF3 4
#define R7S72100_CLK_SCIF4 3
#define R7S72100_CLK_SCIF5 2
#define R7S72100_CLK_SCIF6 1
#define R7S72100_CLK_SCIF7 0
/* MSTP5 */
#define R7S72100_CLK_SCI0 7
#define R7S72100_CLK_SCI1 6
#define R7S72100_CLK_SG0 5
#define R7S72100_CLK_SG1 4
#define R7S72100_CLK_SG2 3
#define R7S72100_CLK_SG3 2
#define R7S72100_CLK_OSTM0 1
#define R7S72100_CLK_OSTM1 0
/* MSTP6 */
#define R7S72100_CLK_ADC 7
#define R7S72100_CLK_CEU 6
#define R7S72100_CLK_DOC0 5
#define R7S72100_CLK_DOC1 4
#define R7S72100_CLK_DRC0 3
#define R7S72100_CLK_DRC1 2
#define R7S72100_CLK_JCU 1
#define R7S72100_CLK_RTC 0
/* MSTP7 */
#define R7S72100_CLK_VDEC0 7
#define R7S72100_CLK_VDEC1 6
#define R7S72100_CLK_ETHER 4
#define R7S72100_CLK_NAND 3
#define R7S72100_CLK_USB0 1
#define R7S72100_CLK_USB1 0
/* MSTP8 */
#define R7S72100_CLK_IMR0 7
#define R7S72100_CLK_IMR1 6
#define R7S72100_CLK_IMRDISP 5
#define R7S72100_CLK_MMCIF 4
#define R7S72100_CLK_MLB 3
#define R7S72100_CLK_ETHAVB 2
#define R7S72100_CLK_SCUX 1
/* MSTP9 */
#define R7S72100_CLK_I2C0 7
#define R7S72100_CLK_I2C1 6
#define R7S72100_CLK_I2C2 5
#define R7S72100_CLK_I2C3 4
#define R7S72100_CLK_SPIBSC0 3
#define R7S72100_CLK_SPIBSC1 2
#define R7S72100_CLK_VDC50 1 /* and LVDS */
#define R7S72100_CLK_VDC51 0
/* MSTP10 */
#define R7S72100_CLK_SPI0 7
#define R7S72100_CLK_SPI1 6
#define R7S72100_CLK_SPI2 5
#define R7S72100_CLK_SPI3 4
#define R7S72100_CLK_SPI4 3
#define R7S72100_CLK_CDROM 2
#define R7S72100_CLK_SPDIF 1
#define R7S72100_CLK_RGPVG2 0
/* MSTP11 */
#define R7S72100_CLK_SSI0 5
#define R7S72100_CLK_SSI1 4
#define R7S72100_CLK_SSI2 3
#define R7S72100_CLK_SSI3 2
#define R7S72100_CLK_SSI4 1
#define R7S72100_CLK_SSI5 0
/* MSTP12 */
#define R7S72100_CLK_SDHI00 3
#define R7S72100_CLK_SDHI01 2
#define R7S72100_CLK_SDHI10 1
#define R7S72100_CLK_SDHI11 0
/* MSTP13 */
#define R7S72100_CLK_PIX1 2
#define R7S72100_CLK_PIX0 1
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */

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include/dt-bindings/clock/r9a06g032-sysctrl.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* R9A06G032 sysctrl IDs
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
*/
#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
#define R9A06G032_CLK_PLL_USB 1
#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
#define R9A06G032_CLK_25_PG4 26
#define R9A06G032_CLK_25_PG5 27
#define R9A06G032_CLK_25_PG6 28
#define R9A06G032_CLK_25_PG7 29
#define R9A06G032_CLK_25_PG8 30
#define R9A06G032_CLK_ADC 31
#define R9A06G032_CLK_ECAT100 32
#define R9A06G032_CLK_HSR100 33
#define R9A06G032_CLK_I2C0 34
#define R9A06G032_CLK_I2C1 35
#define R9A06G032_CLK_MII_REF 36
#define R9A06G032_CLK_NAND 37
#define R9A06G032_CLK_NOUSBP2_PG6 38
#define R9A06G032_CLK_P1_PG2 39
#define R9A06G032_CLK_P1_PG3 40
#define R9A06G032_CLK_P1_PG4 41
#define R9A06G032_CLK_P4_PG3 42
#define R9A06G032_CLK_P4_PG4 43
#define R9A06G032_CLK_P6_PG1 44
#define R9A06G032_CLK_P6_PG2 45
#define R9A06G032_CLK_P6_PG3 46
#define R9A06G032_CLK_P6_PG4 47
#define R9A06G032_CLK_PCI_USB 48
#define R9A06G032_CLK_QSPI0 49
#define R9A06G032_CLK_QSPI1 50
#define R9A06G032_CLK_RGMII_REF 51
#define R9A06G032_CLK_RMII_REF 52
#define R9A06G032_CLK_SDIO0 53
#define R9A06G032_CLK_SDIO1 54
#define R9A06G032_CLK_SERCOS100 55
#define R9A06G032_CLK_SLCD 56
#define R9A06G032_CLK_SPI0 57
#define R9A06G032_CLK_SPI1 58
#define R9A06G032_CLK_SPI2 59
#define R9A06G032_CLK_SPI3 60
#define R9A06G032_CLK_SPI4 61
#define R9A06G032_CLK_SPI5 62
#define R9A06G032_CLK_SWITCH 63
#define R9A06G032_HCLK_ECAT125 65
#define R9A06G032_HCLK_PINCONFIG 66
#define R9A06G032_HCLK_SERCOS 67
#define R9A06G032_HCLK_SGPIO2 68
#define R9A06G032_HCLK_SGPIO3 69
#define R9A06G032_HCLK_SGPIO4 70
#define R9A06G032_HCLK_TIMER0 71
#define R9A06G032_HCLK_TIMER1 72
#define R9A06G032_HCLK_USBF 73
#define R9A06G032_HCLK_USBH 74
#define R9A06G032_HCLK_USBPM 75
#define R9A06G032_CLK_48_PG_F 76
#define R9A06G032_CLK_48_PG4 77
#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */
#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
#define R9A06G032_HCLK_CAN0 85
#define R9A06G032_HCLK_CAN1 86
#define R9A06G032_HCLK_DELTASIGMA 87
#define R9A06G032_HCLK_PWMPTO 88
#define R9A06G032_HCLK_RSV 89
#define R9A06G032_HCLK_SGPIO0 90
#define R9A06G032_HCLK_SGPIO1 91
#define R9A06G032_RTOS_MDC 92
#define R9A06G032_CLK_CM3 93
#define R9A06G032_CLK_DDRC 94
#define R9A06G032_CLK_ECAT25 95
#define R9A06G032_CLK_HSR50 96
#define R9A06G032_CLK_HW_RTOS 97
#define R9A06G032_CLK_SERCOS50 98
#define R9A06G032_HCLK_ADC 99
#define R9A06G032_HCLK_CM3 100
#define R9A06G032_HCLK_CRYPTO_EIP150 101
#define R9A06G032_HCLK_CRYPTO_EIP93 102
#define R9A06G032_HCLK_DDRC 103
#define R9A06G032_HCLK_DMA0 104
#define R9A06G032_HCLK_DMA1 105
#define R9A06G032_HCLK_GMAC0 106
#define R9A06G032_HCLK_GMAC1 107
#define R9A06G032_HCLK_GPIO0 108
#define R9A06G032_HCLK_GPIO1 109
#define R9A06G032_HCLK_GPIO2 110
#define R9A06G032_HCLK_HSR 111
#define R9A06G032_HCLK_I2C0 112
#define R9A06G032_HCLK_I2C1 113
#define R9A06G032_HCLK_LCD 114
#define R9A06G032_HCLK_MSEBI_M 115
#define R9A06G032_HCLK_MSEBI_S 116
#define R9A06G032_HCLK_NAND 117
#define R9A06G032_HCLK_PG_I 118
#define R9A06G032_HCLK_PG19 119
#define R9A06G032_HCLK_PG20 120
#define R9A06G032_HCLK_PG3 121
#define R9A06G032_HCLK_PG4 122
#define R9A06G032_HCLK_QSPI0 123
#define R9A06G032_HCLK_QSPI1 124
#define R9A06G032_HCLK_ROM 125
#define R9A06G032_HCLK_RTC 126
#define R9A06G032_HCLK_SDIO0 127
#define R9A06G032_HCLK_SDIO1 128
#define R9A06G032_HCLK_SEMAP 129
#define R9A06G032_HCLK_SPI0 130
#define R9A06G032_HCLK_SPI1 131
#define R9A06G032_HCLK_SPI2 132
#define R9A06G032_HCLK_SPI3 133
#define R9A06G032_HCLK_SPI4 134
#define R9A06G032_HCLK_SPI5 135
#define R9A06G032_HCLK_SWITCH 136
#define R9A06G032_HCLK_SWITCH_RG 137
#define R9A06G032_HCLK_UART0 138
#define R9A06G032_HCLK_UART1 139
#define R9A06G032_HCLK_UART2 140
#define R9A06G032_HCLK_UART3 141
#define R9A06G032_HCLK_UART4 142
#define R9A06G032_HCLK_UART5 143
#define R9A06G032_HCLK_UART6 144
#define R9A06G032_HCLK_UART7 145
#define R9A06G032_CLK_UART0 146
#define R9A06G032_CLK_UART1 147
#define R9A06G032_CLK_UART2 148
#define R9A06G032_CLK_UART3 149
#define R9A06G032_CLK_UART4 150
#define R9A06G032_CLK_UART5 151
#define R9A06G032_CLK_UART6 152
#define R9A06G032_CLK_UART7 153
#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */

24
include/dt-bindings/clock/sifive-fu740-prci.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2019 SiFive, Inc.
* Wesley Terpstra
* Paul Walmsley
* Zong Li
*/
#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
/* Clock indexes for use by Device Tree data and the PRCI driver */
#define FU740_PRCI_CLK_COREPLL 0
#define FU740_PRCI_CLK_DDRPLL 1
#define FU740_PRCI_CLK_GEMGXLPLL 2
#define FU740_PRCI_CLK_DVFSCOREPLL 3
#define FU740_PRCI_CLK_HFPCLKPLL 4
#define FU740_PRCI_CLK_CLTXPLL 5
#define FU740_PRCI_CLK_TLCLK 6
#define FU740_PRCI_CLK_PCLK 7
#define FU740_PRCI_CLK_PCIE_AUX 8
#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */

176
include/dt-bindings/clock/sophgo,cv1800.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2023 Sophgo Ltd.
*/
#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
#define CLK_MPLL 0
#define CLK_TPLL 1
#define CLK_FPLL 2
#define CLK_MIPIMPLL 3
#define CLK_A0PLL 4
#define CLK_DISPPLL 5
#define CLK_CAM0PLL 6
#define CLK_CAM1PLL 7
#define CLK_MIPIMPLL_D3 8
#define CLK_CAM0PLL_D2 9
#define CLK_CAM0PLL_D3 10
#define CLK_TPU 11
#define CLK_TPU_FAB 12
#define CLK_AHB_ROM 13
#define CLK_DDR_AXI_REG 14
#define CLK_RTC_25M 15
#define CLK_SRC_RTC_SYS_0 16
#define CLK_TEMPSEN 17
#define CLK_SARADC 18
#define CLK_EFUSE 19
#define CLK_APB_EFUSE 20
#define CLK_DEBUG 21
#define CLK_AP_DEBUG 22
#define CLK_XTAL_MISC 23
#define CLK_AXI4_EMMC 24
#define CLK_EMMC 25
#define CLK_EMMC_100K 26
#define CLK_AXI4_SD0 27
#define CLK_SD0 28
#define CLK_SD0_100K 29
#define CLK_AXI4_SD1 30
#define CLK_SD1 31
#define CLK_SD1_100K 32
#define CLK_SPI_NAND 33
#define CLK_ETH0_500M 34
#define CLK_AXI4_ETH0 35
#define CLK_ETH1_500M 36
#define CLK_AXI4_ETH1 37
#define CLK_APB_GPIO 38
#define CLK_APB_GPIO_INTR 39
#define CLK_GPIO_DB 40
#define CLK_AHB_SF 41
#define CLK_AHB_SF1 42
#define CLK_A24M 43
#define CLK_AUDSRC 44
#define CLK_APB_AUDSRC 45
#define CLK_SDMA_AXI 46
#define CLK_SDMA_AUD0 47
#define CLK_SDMA_AUD1 48
#define CLK_SDMA_AUD2 49
#define CLK_SDMA_AUD3 50
#define CLK_I2C 51
#define CLK_APB_I2C 52
#define CLK_APB_I2C0 53
#define CLK_APB_I2C1 54
#define CLK_APB_I2C2 55
#define CLK_APB_I2C3 56
#define CLK_APB_I2C4 57
#define CLK_APB_WDT 58
#define CLK_PWM_SRC 59
#define CLK_PWM 60
#define CLK_SPI 61
#define CLK_APB_SPI0 62
#define CLK_APB_SPI1 63
#define CLK_APB_SPI2 64
#define CLK_APB_SPI3 65
#define CLK_1M 66
#define CLK_CAM0_200 67
#define CLK_PM 68
#define CLK_TIMER0 69
#define CLK_TIMER1 70
#define CLK_TIMER2 71
#define CLK_TIMER3 72
#define CLK_TIMER4 73
#define CLK_TIMER5 74
#define CLK_TIMER6 75
#define CLK_TIMER7 76
#define CLK_UART0 77
#define CLK_APB_UART0 78
#define CLK_UART1 79
#define CLK_APB_UART1 80
#define CLK_UART2 81
#define CLK_APB_UART2 82
#define CLK_UART3 83
#define CLK_APB_UART3 84
#define CLK_UART4 85
#define CLK_APB_UART4 86
#define CLK_APB_I2S0 87
#define CLK_APB_I2S1 88
#define CLK_APB_I2S2 89
#define CLK_APB_I2S3 90
#define CLK_AXI4_USB 91
#define CLK_APB_USB 92
#define CLK_USB_125M 93
#define CLK_USB_33K 94
#define CLK_USB_12M 95
#define CLK_AXI4 96
#define CLK_AXI6 97
#define CLK_DSI_ESC 98
#define CLK_AXI_VIP 99
#define CLK_SRC_VIP_SYS_0 100
#define CLK_SRC_VIP_SYS_1 101
#define CLK_SRC_VIP_SYS_2 102
#define CLK_SRC_VIP_SYS_3 103
#define CLK_SRC_VIP_SYS_4 104
#define CLK_CSI_BE_VIP 105
#define CLK_CSI_MAC0_VIP 106
#define CLK_CSI_MAC1_VIP 107
#define CLK_CSI_MAC2_VIP 108
#define CLK_CSI0_RX_VIP 109
#define CLK_CSI1_RX_VIP 110
#define CLK_ISP_TOP_VIP 111
#define CLK_IMG_D_VIP 112
#define CLK_IMG_V_VIP 113
#define CLK_SC_TOP_VIP 114
#define CLK_SC_D_VIP 115
#define CLK_SC_V1_VIP 116
#define CLK_SC_V2_VIP 117
#define CLK_SC_V3_VIP 118
#define CLK_DWA_VIP 119
#define CLK_BT_VIP 120
#define CLK_DISP_VIP 121
#define CLK_DSI_MAC_VIP 122
#define CLK_LVDS0_VIP 123
#define CLK_LVDS1_VIP 124
#define CLK_PAD_VI_VIP 125
#define CLK_PAD_VI1_VIP 126
#define CLK_PAD_VI2_VIP 127
#define CLK_CFG_REG_VIP 128
#define CLK_VIP_IP0 129
#define CLK_VIP_IP1 130
#define CLK_VIP_IP2 131
#define CLK_VIP_IP3 132
#define CLK_IVE_VIP 133
#define CLK_RAW_VIP 134
#define CLK_OSDC_VIP 135
#define CLK_CAM0_VIP 136
#define CLK_AXI_VIDEO_CODEC 137
#define CLK_VC_SRC0 138
#define CLK_VC_SRC1 139
#define CLK_VC_SRC2 140
#define CLK_H264C 141
#define CLK_APB_H264C 142
#define CLK_H265C 143
#define CLK_APB_H265C 144
#define CLK_JPEG 145
#define CLK_APB_JPEG 146
#define CLK_CAM0 147
#define CLK_CAM1 148
#define CLK_WGN 149
#define CLK_WGN0 150
#define CLK_WGN1 151
#define CLK_WGN2 152
#define CLK_KEYSCAN 153
#define CLK_CFG_REG_VC 154
#define CLK_C906_0 155
#define CLK_C906_1 156
#define CLK_A53 157
#define CLK_CPU_AXI0 158
#define CLK_CPU_GIC 159
#define CLK_XTAL_AP 160
// Only for CV181x
#define CLK_DISP_SRC_VIP 161
#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */

12
include/dt-bindings/clock/ste-ab8500.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __STE_CLK_AB8500_H__
#define __STE_CLK_AB8500_H__
#define AB8500_SYSCLK_BUF2 0
#define AB8500_SYSCLK_BUF3 1
#define AB8500_SYSCLK_BUF4 2
#define AB8500_SYSCLK_ULP 3
#define AB8500_SYSCLK_INT 4
#define AB8500_SYSCLK_AUDIO 5
#endif

158
include/dt-bindings/clock/sun20i-d1-ccu.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2020 huangzhenwei@allwinnertech.com
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
#define CLK_PLL_CPUX 0
#define CLK_PLL_DDR0 1
#define CLK_PLL_PERIPH0_4X 2
#define CLK_PLL_PERIPH0_2X 3
#define CLK_PLL_PERIPH0_800M 4
#define CLK_PLL_PERIPH0 5
#define CLK_PLL_PERIPH0_DIV3 6
#define CLK_PLL_VIDEO0_4X 7
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_VIDEO0 9
#define CLK_PLL_VIDEO1_4X 10
#define CLK_PLL_VIDEO1_2X 11
#define CLK_PLL_VIDEO1 12
#define CLK_PLL_VE 13
#define CLK_PLL_AUDIO0_4X 14
#define CLK_PLL_AUDIO0_2X 15
#define CLK_PLL_AUDIO0 16
#define CLK_PLL_AUDIO1 17
#define CLK_PLL_AUDIO1_DIV2 18
#define CLK_PLL_AUDIO1_DIV5 19
#define CLK_CPUX 20
#define CLK_CPUX_AXI 21
#define CLK_CPUX_APB 22
#define CLK_PSI_AHB 23
#define CLK_APB0 24
#define CLK_APB1 25
#define CLK_MBUS 26
#define CLK_DE 27
#define CLK_BUS_DE 28
#define CLK_DI 29
#define CLK_BUS_DI 30
#define CLK_G2D 31
#define CLK_BUS_G2D 32
#define CLK_CE 33
#define CLK_BUS_CE 34
#define CLK_VE 35
#define CLK_BUS_VE 36
#define CLK_BUS_DMA 37
#define CLK_BUS_MSGBOX0 38
#define CLK_BUS_MSGBOX1 39
#define CLK_BUS_MSGBOX2 40
#define CLK_BUS_SPINLOCK 41
#define CLK_BUS_HSTIMER 42
#define CLK_AVS 43
#define CLK_BUS_DBG 44
#define CLK_BUS_PWM 45
#define CLK_BUS_IOMMU 46
#define CLK_DRAM 47
#define CLK_MBUS_DMA 48
#define CLK_MBUS_VE 49
#define CLK_MBUS_CE 50
#define CLK_MBUS_TVIN 51
#define CLK_MBUS_CSI 52
#define CLK_MBUS_G2D 53
#define CLK_MBUS_RISCV 54
#define CLK_BUS_DRAM 55
#define CLK_MMC0 56
#define CLK_MMC1 57
#define CLK_MMC2 58
#define CLK_BUS_MMC0 59
#define CLK_BUS_MMC1 60
#define CLK_BUS_MMC2 61
#define CLK_BUS_UART0 62
#define CLK_BUS_UART1 63
#define CLK_BUS_UART2 64
#define CLK_BUS_UART3 65
#define CLK_BUS_UART4 66
#define CLK_BUS_UART5 67
#define CLK_BUS_I2C0 68
#define CLK_BUS_I2C1 69
#define CLK_BUS_I2C2 70
#define CLK_BUS_I2C3 71
#define CLK_SPI0 72
#define CLK_SPI1 73
#define CLK_BUS_SPI0 74
#define CLK_BUS_SPI1 75
#define CLK_EMAC_25M 76
#define CLK_BUS_EMAC 77
#define CLK_IR_TX 78
#define CLK_BUS_IR_TX 79
#define CLK_BUS_GPADC 80
#define CLK_BUS_THS 81
#define CLK_I2S0 82
#define CLK_I2S1 83
#define CLK_I2S2 84
#define CLK_I2S2_ASRC 85
#define CLK_BUS_I2S0 86
#define CLK_BUS_I2S1 87
#define CLK_BUS_I2S2 88
#define CLK_SPDIF_TX 89
#define CLK_SPDIF_RX 90
#define CLK_BUS_SPDIF 91
#define CLK_DMIC 92
#define CLK_BUS_DMIC 93
#define CLK_AUDIO_DAC 94
#define CLK_AUDIO_ADC 95
#define CLK_BUS_AUDIO 96
#define CLK_USB_OHCI0 97
#define CLK_USB_OHCI1 98
#define CLK_BUS_OHCI0 99
#define CLK_BUS_OHCI1 100
#define CLK_BUS_EHCI0 101
#define CLK_BUS_EHCI1 102
#define CLK_BUS_OTG 103
#define CLK_BUS_LRADC 104
#define CLK_BUS_DPSS_TOP 105
#define CLK_HDMI_24M 106
#define CLK_HDMI_CEC_32K 107
#define CLK_HDMI_CEC 108
#define CLK_BUS_HDMI 109
#define CLK_MIPI_DSI 110
#define CLK_BUS_MIPI_DSI 111
#define CLK_TCON_LCD0 112
#define CLK_BUS_TCON_LCD0 113
#define CLK_TCON_TV 114
#define CLK_BUS_TCON_TV 115
#define CLK_TVE 116
#define CLK_BUS_TVE_TOP 117
#define CLK_BUS_TVE 118
#define CLK_TVD 119
#define CLK_BUS_TVD_TOP 120
#define CLK_BUS_TVD 121
#define CLK_LEDC 122
#define CLK_BUS_LEDC 123
#define CLK_CSI_TOP 124
#define CLK_CSI_MCLK 125
#define CLK_BUS_CSI 126
#define CLK_TPADC 127
#define CLK_BUS_TPADC 128
#define CLK_BUS_TZMA 129
#define CLK_DSP 130
#define CLK_BUS_DSP_CFG 131
#define CLK_RISCV 132
#define CLK_RISCV_AXI 133
#define CLK_BUS_RISCV_CFG 134
#define CLK_FANOUT_24M 135
#define CLK_FANOUT_12M 136
#define CLK_FANOUT_16M 137
#define CLK_FANOUT_25M 138
#define CLK_FANOUT_32K 139
#define CLK_FANOUT_27M 140
#define CLK_FANOUT_PCLK 141
#define CLK_FANOUT0 142
#define CLK_FANOUT1 143
#define CLK_FANOUT2 144
#define CLK_BUS_CAN0 145
#define CLK_BUS_CAN1 146
#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */

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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
#define CLK_R_AHB 0
#define CLK_BUS_R_TIMER 2
#define CLK_BUS_R_TWD 3
#define CLK_BUS_R_PPU 4
#define CLK_R_IR_RX 5
#define CLK_BUS_R_IR_RX 6
#define CLK_BUS_R_RTC 7
#define CLK_BUS_R_CPUCFG 8
#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */

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/*
* Copyright (C) 2017 Priit Laes <plaes@plaes.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
#define _DT_BINDINGS_CLK_SUN4I_A10_H_
#define CLK_HOSC 1
#define CLK_PLL_VIDEO0_2X 9
#define CLK_PLL_VIDEO1_2X 18
#define CLK_CPU 20
/* AHB Gates */
#define CLK_AHB_OTG 26
#define CLK_AHB_EHCI0 27
#define CLK_AHB_OHCI0 28
#define CLK_AHB_EHCI1 29
#define CLK_AHB_OHCI1 30
#define CLK_AHB_SS 31
#define CLK_AHB_DMA 32
#define CLK_AHB_BIST 33
#define CLK_AHB_MMC0 34
#define CLK_AHB_MMC1 35
#define CLK_AHB_MMC2 36
#define CLK_AHB_MMC3 37
#define CLK_AHB_MS 38
#define CLK_AHB_NAND 39
#define CLK_AHB_SDRAM 40
#define CLK_AHB_ACE 41
#define CLK_AHB_EMAC 42
#define CLK_AHB_TS 43
#define CLK_AHB_SPI0 44
#define CLK_AHB_SPI1 45
#define CLK_AHB_SPI2 46
#define CLK_AHB_SPI3 47
#define CLK_AHB_PATA 48
#define CLK_AHB_SATA 49
#define CLK_AHB_GPS 50
#define CLK_AHB_HSTIMER 51
#define CLK_AHB_VE 52
#define CLK_AHB_TVD 53
#define CLK_AHB_TVE0 54
#define CLK_AHB_TVE1 55
#define CLK_AHB_LCD0 56
#define CLK_AHB_LCD1 57
#define CLK_AHB_CSI0 58
#define CLK_AHB_CSI1 59
#define CLK_AHB_HDMI0 60
#define CLK_AHB_HDMI1 61
#define CLK_AHB_DE_BE0 62
#define CLK_AHB_DE_BE1 63
#define CLK_AHB_DE_FE0 64
#define CLK_AHB_DE_FE1 65
#define CLK_AHB_GMAC 66
#define CLK_AHB_MP 67
#define CLK_AHB_GPU 68
/* APB0 Gates */
#define CLK_APB0_CODEC 69
#define CLK_APB0_SPDIF 70
#define CLK_APB0_I2S0 71
#define CLK_APB0_AC97 72
#define CLK_APB0_I2S1 73
#define CLK_APB0_PIO 74
#define CLK_APB0_IR0 75
#define CLK_APB0_IR1 76
#define CLK_APB0_I2S2 77
#define CLK_APB0_KEYPAD 78
/* APB1 Gates */
#define CLK_APB1_I2C0 79
#define CLK_APB1_I2C1 80
#define CLK_APB1_I2C2 81
#define CLK_APB1_I2C3 82
#define CLK_APB1_CAN 83
#define CLK_APB1_SCR 84
#define CLK_APB1_PS20 85
#define CLK_APB1_PS21 86
#define CLK_APB1_I2C4 87
#define CLK_APB1_UART0 88
#define CLK_APB1_UART1 89
#define CLK_APB1_UART2 90
#define CLK_APB1_UART3 91
#define CLK_APB1_UART4 92
#define CLK_APB1_UART5 93
#define CLK_APB1_UART6 94
#define CLK_APB1_UART7 95
/* IP clocks */
#define CLK_NAND 96
#define CLK_MS 97
#define CLK_MMC0 98
#define CLK_MMC0_OUTPUT 99
#define CLK_MMC0_SAMPLE 100
#define CLK_MMC1 101
#define CLK_MMC1_OUTPUT 102
#define CLK_MMC1_SAMPLE 103
#define CLK_MMC2 104
#define CLK_MMC2_OUTPUT 105
#define CLK_MMC2_SAMPLE 106
#define CLK_MMC3 107
#define CLK_MMC3_OUTPUT 108
#define CLK_MMC3_SAMPLE 109
#define CLK_TS 110
#define CLK_SS 111
#define CLK_SPI0 112
#define CLK_SPI1 113
#define CLK_SPI2 114
#define CLK_PATA 115
#define CLK_IR0 116
#define CLK_IR1 117
#define CLK_I2S0 118
#define CLK_AC97 119
#define CLK_SPDIF 120
#define CLK_KEYPAD 121
#define CLK_SATA 122
#define CLK_USB_OHCI0 123
#define CLK_USB_OHCI1 124
#define CLK_USB_PHY 125
#define CLK_GPS 126
#define CLK_SPI3 127
#define CLK_I2S1 128
#define CLK_I2S2 129
/* DRAM Gates */
#define CLK_DRAM_VE 130
#define CLK_DRAM_CSI0 131
#define CLK_DRAM_CSI1 132
#define CLK_DRAM_TS 133
#define CLK_DRAM_TVD 134
#define CLK_DRAM_TVE0 135
#define CLK_DRAM_TVE1 136
#define CLK_DRAM_OUT 137
#define CLK_DRAM_DE_FE1 138
#define CLK_DRAM_DE_FE0 139
#define CLK_DRAM_DE_BE0 140
#define CLK_DRAM_DE_BE1 141
#define CLK_DRAM_MP 142
#define CLK_DRAM_ACE 143
/* Display Engine Clocks */
#define CLK_DE_BE0 144
#define CLK_DE_BE1 145
#define CLK_DE_FE0 146
#define CLK_DE_FE1 147
#define CLK_DE_MP 148
#define CLK_TCON0_CH0 149
#define CLK_TCON1_CH0 150
#define CLK_CSI_SCLK 151
#define CLK_TVD_SCLK2 152
#define CLK_TVD 153
#define CLK_TCON0_CH1_SCLK2 154
#define CLK_TCON0_CH1 155
#define CLK_TCON1_CH1_SCLK2 156
#define CLK_TCON1_CH1 157
#define CLK_CSI0 158
#define CLK_CSI1 159
#define CLK_CODEC 160
#define CLK_VE 161
#define CLK_AVS 162
#define CLK_ACE 163
#define CLK_HDMI 164
#define CLK_GPU 165
#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */

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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
#define _DT_BINDINGS_CLK_SUN50I_H6_H_
#define CLK_PLL_PERIPH0 3
#define CLK_CPUX 21
#define CLK_APB1 26
#define CLK_DE 29
#define CLK_BUS_DE 30
#define CLK_DEINTERLACE 31
#define CLK_BUS_DEINTERLACE 32
#define CLK_GPU 33
#define CLK_BUS_GPU 34
#define CLK_CE 35
#define CLK_BUS_CE 36
#define CLK_VE 37
#define CLK_BUS_VE 38
#define CLK_EMCE 39
#define CLK_BUS_EMCE 40
#define CLK_VP9 41
#define CLK_BUS_VP9 42
#define CLK_BUS_DMA 43
#define CLK_BUS_MSGBOX 44
#define CLK_BUS_SPINLOCK 45
#define CLK_BUS_HSTIMER 46
#define CLK_AVS 47
#define CLK_BUS_DBG 48
#define CLK_BUS_PSI 49
#define CLK_BUS_PWM 50
#define CLK_BUS_IOMMU 51
#define CLK_MBUS_DMA 53
#define CLK_MBUS_VE 54
#define CLK_MBUS_CE 55
#define CLK_MBUS_TS 56
#define CLK_MBUS_NAND 57
#define CLK_MBUS_CSI 58
#define CLK_MBUS_DEINTERLACE 59
#define CLK_NAND0 61
#define CLK_NAND1 62
#define CLK_BUS_NAND 63
#define CLK_MMC0 64
#define CLK_MMC1 65
#define CLK_MMC2 66
#define CLK_BUS_MMC0 67
#define CLK_BUS_MMC1 68
#define CLK_BUS_MMC2 69
#define CLK_BUS_UART0 70
#define CLK_BUS_UART1 71
#define CLK_BUS_UART2 72
#define CLK_BUS_UART3 73
#define CLK_BUS_I2C0 74
#define CLK_BUS_I2C1 75
#define CLK_BUS_I2C2 76
#define CLK_BUS_I2C3 77
#define CLK_BUS_SCR0 78
#define CLK_BUS_SCR1 79
#define CLK_SPI0 80
#define CLK_SPI1 81
#define CLK_BUS_SPI0 82
#define CLK_BUS_SPI1 83
#define CLK_BUS_EMAC 84
#define CLK_TS 85
#define CLK_BUS_TS 86
#define CLK_IR_TX 87
#define CLK_BUS_IR_TX 88
#define CLK_BUS_THS 89
#define CLK_I2S3 90
#define CLK_I2S0 91
#define CLK_I2S1 92
#define CLK_I2S2 93
#define CLK_BUS_I2S0 94
#define CLK_BUS_I2S1 95
#define CLK_BUS_I2S2 96
#define CLK_BUS_I2S3 97
#define CLK_SPDIF 98
#define CLK_BUS_SPDIF 99
#define CLK_DMIC 100
#define CLK_BUS_DMIC 101
#define CLK_AUDIO_HUB 102
#define CLK_BUS_AUDIO_HUB 103
#define CLK_USB_OHCI0 104
#define CLK_USB_PHY0 105
#define CLK_USB_PHY1 106
#define CLK_USB_OHCI3 107
#define CLK_USB_PHY3 108
#define CLK_USB_HSIC_12M 109
#define CLK_USB_HSIC 110
#define CLK_BUS_OHCI0 111
#define CLK_BUS_OHCI3 112
#define CLK_BUS_EHCI0 113
#define CLK_BUS_XHCI 114
#define CLK_BUS_EHCI3 115
#define CLK_BUS_OTG 116
#define CLK_PCIE_REF_100M 117
#define CLK_PCIE_REF 118
#define CLK_PCIE_REF_OUT 119
#define CLK_PCIE_MAXI 120
#define CLK_PCIE_AUX 121
#define CLK_BUS_PCIE 122
#define CLK_HDMI 123
#define CLK_HDMI_SLOW 124
#define CLK_HDMI_CEC 125
#define CLK_BUS_HDMI 126
#define CLK_BUS_TCON_TOP 127
#define CLK_TCON_LCD0 128
#define CLK_BUS_TCON_LCD0 129
#define CLK_TCON_TV0 130
#define CLK_BUS_TCON_TV0 131
#define CLK_CSI_CCI 132
#define CLK_CSI_TOP 133
#define CLK_CSI_MCLK 134
#define CLK_BUS_CSI 135
#define CLK_HDCP 136
#define CLK_BUS_HDCP 137
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
#define CLK_AR100 0
#define CLK_R_APB1 2
#define CLK_R_APB1_TIMER 4
#define CLK_R_APB1_TWD 5
#define CLK_R_APB1_PWM 6
#define CLK_R_APB2_UART 7
#define CLK_R_APB2_I2C 8
#define CLK_R_APB1_IR 9
#define CLK_R_APB1_W1 10
#define CLK_IR 11
#define CLK_W1 12
#define CLK_R_APB2_RSB 13
#define CLK_R_APB1_RTC 14
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */

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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*/
#ifndef _DT_BINDINGS_CLK_SUN5I_H_
#define _DT_BINDINGS_CLK_SUN5I_H_
#define CLK_HOSC 1
#define CLK_PLL_VIDEO0_2X 9
#define CLK_PLL_VIDEO1_2X 16
#define CLK_CPU 17
#define CLK_AHB_OTG 23
#define CLK_AHB_EHCI 24
#define CLK_AHB_OHCI 25
#define CLK_AHB_SS 26
#define CLK_AHB_DMA 27
#define CLK_AHB_BIST 28
#define CLK_AHB_MMC0 29
#define CLK_AHB_MMC1 30
#define CLK_AHB_MMC2 31
#define CLK_AHB_NAND 32
#define CLK_AHB_SDRAM 33
#define CLK_AHB_EMAC 34
#define CLK_AHB_TS 35
#define CLK_AHB_SPI0 36
#define CLK_AHB_SPI1 37
#define CLK_AHB_SPI2 38
#define CLK_AHB_GPS 39
#define CLK_AHB_HSTIMER 40
#define CLK_AHB_VE 41
#define CLK_AHB_TVE 42
#define CLK_AHB_LCD 43
#define CLK_AHB_CSI 44
#define CLK_AHB_HDMI 45
#define CLK_AHB_DE_BE 46
#define CLK_AHB_DE_FE 47
#define CLK_AHB_IEP 48
#define CLK_AHB_GPU 49
#define CLK_APB0_CODEC 50
#define CLK_APB0_SPDIF 51
#define CLK_APB0_I2S 52
#define CLK_APB0_PIO 53
#define CLK_APB0_IR 54
#define CLK_APB0_KEYPAD 55
#define CLK_APB1_I2C0 56
#define CLK_APB1_I2C1 57
#define CLK_APB1_I2C2 58
#define CLK_APB1_UART0 59
#define CLK_APB1_UART1 60
#define CLK_APB1_UART2 61
#define CLK_APB1_UART3 62
#define CLK_NAND 63
#define CLK_MMC0 64
#define CLK_MMC1 65
#define CLK_MMC2 66
#define CLK_TS 67
#define CLK_SS 68
#define CLK_SPI0 69
#define CLK_SPI1 70
#define CLK_SPI2 71
#define CLK_IR 72
#define CLK_I2S 73
#define CLK_SPDIF 74
#define CLK_KEYPAD 75
#define CLK_USB_OHCI 76
#define CLK_USB_PHY0 77
#define CLK_USB_PHY1 78
#define CLK_GPS 79
#define CLK_DRAM_VE 80
#define CLK_DRAM_CSI 81
#define CLK_DRAM_TS 82
#define CLK_DRAM_TVE 83
#define CLK_DRAM_DE_FE 84
#define CLK_DRAM_DE_BE 85
#define CLK_DRAM_ACE 86
#define CLK_DRAM_IEP 87
#define CLK_DE_BE 88
#define CLK_DE_FE 89
#define CLK_TCON_CH0 90
#define CLK_TCON_CH1 92
#define CLK_CSI 93
#define CLK_VE 94
#define CLK_CODEC 95
#define CLK_AVS 96
#define CLK_HDMI 97
#define CLK_GPU 98
#define CLK_MBUS 99
#define CLK_IEP 100
#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */

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/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
#define _DT_BINDINGS_CLK_SUN6I_A31_H_
#define CLK_PLL_VIDEO0_2X 7
#define CLK_PLL_PERIPH 10
#define CLK_PLL_VIDEO1_2X 13
#define CLK_PLL_MIPI 15
#define CLK_CPU 18
#define CLK_AHB1_MIPIDSI 23
#define CLK_AHB1_SS 24
#define CLK_AHB1_DMA 25
#define CLK_AHB1_MMC0 26
#define CLK_AHB1_MMC1 27
#define CLK_AHB1_MMC2 28
#define CLK_AHB1_MMC3 29
#define CLK_AHB1_NAND1 30
#define CLK_AHB1_NAND0 31
#define CLK_AHB1_SDRAM 32
#define CLK_AHB1_EMAC 33
#define CLK_AHB1_TS 34
#define CLK_AHB1_HSTIMER 35
#define CLK_AHB1_SPI0 36
#define CLK_AHB1_SPI1 37
#define CLK_AHB1_SPI2 38
#define CLK_AHB1_SPI3 39
#define CLK_AHB1_OTG 40
#define CLK_AHB1_EHCI0 41
#define CLK_AHB1_EHCI1 42
#define CLK_AHB1_OHCI0 43
#define CLK_AHB1_OHCI1 44
#define CLK_AHB1_OHCI2 45
#define CLK_AHB1_VE 46
#define CLK_AHB1_LCD0 47
#define CLK_AHB1_LCD1 48
#define CLK_AHB1_CSI 49
#define CLK_AHB1_HDMI 50
#define CLK_AHB1_BE0 51
#define CLK_AHB1_BE1 52
#define CLK_AHB1_FE0 53
#define CLK_AHB1_FE1 54
#define CLK_AHB1_MP 55
#define CLK_AHB1_GPU 56
#define CLK_AHB1_DEU0 57
#define CLK_AHB1_DEU1 58
#define CLK_AHB1_DRC0 59
#define CLK_AHB1_DRC1 60
#define CLK_APB1_CODEC 61
#define CLK_APB1_SPDIF 62
#define CLK_APB1_DIGITAL_MIC 63
#define CLK_APB1_PIO 64
#define CLK_APB1_DAUDIO0 65
#define CLK_APB1_DAUDIO1 66
#define CLK_APB2_I2C0 67
#define CLK_APB2_I2C1 68
#define CLK_APB2_I2C2 69
#define CLK_APB2_I2C3 70
#define CLK_APB2_UART0 71
#define CLK_APB2_UART1 72
#define CLK_APB2_UART2 73
#define CLK_APB2_UART3 74
#define CLK_APB2_UART4 75
#define CLK_APB2_UART5 76
#define CLK_NAND0 77
#define CLK_NAND1 78
#define CLK_MMC0 79
#define CLK_MMC0_SAMPLE 80
#define CLK_MMC0_OUTPUT 81
#define CLK_MMC1 82
#define CLK_MMC1_SAMPLE 83
#define CLK_MMC1_OUTPUT 84
#define CLK_MMC2 85
#define CLK_MMC2_SAMPLE 86
#define CLK_MMC2_OUTPUT 87
#define CLK_MMC3 88
#define CLK_MMC3_SAMPLE 89
#define CLK_MMC3_OUTPUT 90
#define CLK_TS 91
#define CLK_SS 92
#define CLK_SPI0 93
#define CLK_SPI1 94
#define CLK_SPI2 95
#define CLK_SPI3 96
#define CLK_DAUDIO0 97
#define CLK_DAUDIO1 98
#define CLK_SPDIF 99
#define CLK_USB_PHY0 100
#define CLK_USB_PHY1 101
#define CLK_USB_PHY2 102
#define CLK_USB_OHCI0 103
#define CLK_USB_OHCI1 104
#define CLK_USB_OHCI2 105
#define CLK_DRAM_VE 110
#define CLK_DRAM_CSI_ISP 111
#define CLK_DRAM_TS 112
#define CLK_DRAM_DRC0 113
#define CLK_DRAM_DRC1 114
#define CLK_DRAM_DEU0 115
#define CLK_DRAM_DEU1 116
#define CLK_DRAM_FE0 117
#define CLK_DRAM_FE1 118
#define CLK_DRAM_BE0 119
#define CLK_DRAM_BE1 120
#define CLK_DRAM_MP 121
#define CLK_BE0 122
#define CLK_BE1 123
#define CLK_FE0 124
#define CLK_FE1 125
#define CLK_MP 126
#define CLK_LCD0_CH0 127
#define CLK_LCD1_CH0 128
#define CLK_LCD0_CH1 129
#define CLK_LCD1_CH1 130
#define CLK_CSI0_SCLK 131
#define CLK_CSI0_MCLK 132
#define CLK_CSI1_MCLK 133
#define CLK_VE 134
#define CLK_CODEC 135
#define CLK_AVS 136
#define CLK_DIGITAL_MIC 137
#define CLK_HDMI 138
#define CLK_HDMI_DDC 139
#define CLK_PS 140
#define CLK_MIPI_DSI 143
#define CLK_MIPI_DSI_DPHY 144
#define CLK_MIPI_CSI_DPHY 145
#define CLK_IEP_DRC0 146
#define CLK_IEP_DRC1 147
#define CLK_IEP_DEU0 148
#define CLK_IEP_DEU1 149
#define CLK_GPU_CORE 150
#define CLK_GPU_MEMORY 151
#define CLK_GPU_HYD 152
#define CLK_ATS 153
#define CLK_TRACE 154
#define CLK_OUT_A 155
#define CLK_OUT_B 156
#define CLK_OUT_C 157
#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */

10
include/dt-bindings/clock/sun6i-rtc.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
#define CLK_OSC32K 0
#define CLK_OSC32K_FANOUT 1
#define CLK_IOSC 2
#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */

53
include/dt-bindings/clock/sun7i-a20-ccu.h
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@ -1,53 +0,0 @@
/*
* Copyright (C) 2017 Priit Laes <plaes@plaes.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
#define _DT_BINDINGS_CLK_SUN7I_A20_H_
#include <dt-bindings/clock/sun4i-a10-ccu.h>
#define CLK_MBUS 166
#define CLK_HDMI1_SLOW 167
#define CLK_HDMI1 168
#define CLK_OUT_A 169
#define CLK_OUT_B 170
#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */

129
include/dt-bindings/clock/sun8i-a23-a33-ccu.h
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@ -1,129 +0,0 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define CLK_PLL_MIPI 13
#define CLK_CPUX 18
#define CLK_BUS_MIPI_DSI 23
#define CLK_BUS_SS 24
#define CLK_BUS_DMA 25
#define CLK_BUS_MMC0 26
#define CLK_BUS_MMC1 27
#define CLK_BUS_MMC2 28
#define CLK_BUS_NAND 29
#define CLK_BUS_DRAM 30
#define CLK_BUS_HSTIMER 31
#define CLK_BUS_SPI0 32
#define CLK_BUS_SPI1 33
#define CLK_BUS_OTG 34
#define CLK_BUS_EHCI 35
#define CLK_BUS_OHCI 36
#define CLK_BUS_VE 37
#define CLK_BUS_LCD 38
#define CLK_BUS_CSI 39
#define CLK_BUS_DE_BE 40
#define CLK_BUS_DE_FE 41
#define CLK_BUS_GPU 42
#define CLK_BUS_MSGBOX 43
#define CLK_BUS_SPINLOCK 44
#define CLK_BUS_DRC 45
#define CLK_BUS_SAT 46
#define CLK_BUS_CODEC 47
#define CLK_BUS_PIO 48
#define CLK_BUS_I2S0 49
#define CLK_BUS_I2S1 50
#define CLK_BUS_I2C0 51
#define CLK_BUS_I2C1 52
#define CLK_BUS_I2C2 53
#define CLK_BUS_UART0 54
#define CLK_BUS_UART1 55
#define CLK_BUS_UART2 56
#define CLK_BUS_UART3 57
#define CLK_BUS_UART4 58
#define CLK_NAND 59
#define CLK_MMC0 60
#define CLK_MMC0_SAMPLE 61
#define CLK_MMC0_OUTPUT 62
#define CLK_MMC1 63
#define CLK_MMC1_SAMPLE 64
#define CLK_MMC1_OUTPUT 65
#define CLK_MMC2 66
#define CLK_MMC2_SAMPLE 67
#define CLK_MMC2_OUTPUT 68
#define CLK_SS 69
#define CLK_SPI0 70
#define CLK_SPI1 71
#define CLK_I2S0 72
#define CLK_I2S1 73
#define CLK_USB_PHY0 74
#define CLK_USB_PHY1 75
#define CLK_USB_HSIC 76
#define CLK_USB_HSIC_12M 77
#define CLK_USB_OHCI 78
#define CLK_DRAM_VE 80
#define CLK_DRAM_CSI 81
#define CLK_DRAM_DRC 82
#define CLK_DRAM_DE_FE 83
#define CLK_DRAM_DE_BE 84
#define CLK_DE_BE 85
#define CLK_DE_FE 86
#define CLK_LCD_CH0 87
#define CLK_LCD_CH1 88
#define CLK_CSI_SCLK 89
#define CLK_CSI_MCLK 90
#define CLK_VE 91
#define CLK_AC_DIG 92
#define CLK_AC_DIG_4X 93
#define CLK_AVS 94
#define CLK_DSI_SCLK 96
#define CLK_DSI_DPHY 97
#define CLK_DRC 98
#define CLK_GPU 99
#define CLK_ATS 100
#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */

140
include/dt-bindings/clock/sun8i-a83t-ccu.h
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@ -1,140 +0,0 @@
/*
* Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
#define CLK_PLL_PERIPH 6
#define CLK_PLL_DE 9
#define CLK_C0CPUX 11
#define CLK_C1CPUX 12
#define CLK_BUS_MIPI_DSI 19
#define CLK_BUS_SS 20
#define CLK_BUS_DMA 21
#define CLK_BUS_MMC0 22
#define CLK_BUS_MMC1 23
#define CLK_BUS_MMC2 24
#define CLK_BUS_NAND 25
#define CLK_BUS_DRAM 26
#define CLK_BUS_EMAC 27
#define CLK_BUS_HSTIMER 28
#define CLK_BUS_SPI0 29
#define CLK_BUS_SPI1 30
#define CLK_BUS_OTG 31
#define CLK_BUS_EHCI0 32
#define CLK_BUS_EHCI1 33
#define CLK_BUS_OHCI0 34
#define CLK_BUS_VE 35
#define CLK_BUS_TCON0 36
#define CLK_BUS_TCON1 37
#define CLK_BUS_CSI 38
#define CLK_BUS_HDMI 39
#define CLK_BUS_DE 40
#define CLK_BUS_GPU 41
#define CLK_BUS_MSGBOX 42
#define CLK_BUS_SPINLOCK 43
#define CLK_BUS_SPDIF 44
#define CLK_BUS_PIO 45
#define CLK_BUS_I2S0 46
#define CLK_BUS_I2S1 47
#define CLK_BUS_I2S2 48
#define CLK_BUS_TDM 49
#define CLK_BUS_I2C0 50
#define CLK_BUS_I2C1 51
#define CLK_BUS_I2C2 52
#define CLK_BUS_UART0 53
#define CLK_BUS_UART1 54
#define CLK_BUS_UART2 55
#define CLK_BUS_UART3 56
#define CLK_BUS_UART4 57
#define CLK_NAND 59
#define CLK_MMC0 60
#define CLK_MMC0_SAMPLE 61
#define CLK_MMC0_OUTPUT 62
#define CLK_MMC1 63
#define CLK_MMC1_SAMPLE 64
#define CLK_MMC1_OUTPUT 65
#define CLK_MMC2 66
#define CLK_MMC2_SAMPLE 67
#define CLK_MMC2_OUTPUT 68
#define CLK_SS 69
#define CLK_SPI0 70
#define CLK_SPI1 71
#define CLK_I2S0 72
#define CLK_I2S1 73
#define CLK_I2S2 74
#define CLK_TDM 75
#define CLK_SPDIF 76
#define CLK_USB_PHY0 77
#define CLK_USB_PHY1 78
#define CLK_USB_HSIC 79
#define CLK_USB_HSIC_12M 80
#define CLK_USB_OHCI0 81
#define CLK_DRAM_VE 83
#define CLK_DRAM_CSI 84
#define CLK_TCON0 85
#define CLK_TCON1 86
#define CLK_CSI_MISC 87
#define CLK_MIPI_CSI 88
#define CLK_CSI_MCLK 89
#define CLK_CSI_SCLK 90
#define CLK_VE 91
#define CLK_AVS 92
#define CLK_HDMI 93
#define CLK_HDMI_SLOW 94
#define CLK_MIPI_DSI0 96
#define CLK_MIPI_DSI1 97
#define CLK_GPU_CORE 98
#define CLK_GPU_MEMORY 99
#define CLK_GPU_HYD 100
#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */

21
include/dt-bindings/clock/sun8i-de2.h
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@ -1,21 +0,0 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
#define CLK_BUS_MIXER0 0
#define CLK_BUS_MIXER1 1
#define CLK_BUS_WB 2
#define CLK_MIXER0 6
#define CLK_MIXER1 7
#define CLK_WB 8
#define CLK_BUS_ROT 9
#define CLK_ROT 10
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */

152
include/dt-bindings/clock/sun8i-h3-ccu.h
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@ -1,152 +0,0 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
#define _DT_BINDINGS_CLK_SUN8I_H3_H_
#define CLK_PLL_VIDEO 6
#define CLK_PLL_PERIPH0 9
#define CLK_CPUX 14
#define CLK_BUS_CE 20
#define CLK_BUS_DMA 21
#define CLK_BUS_MMC0 22
#define CLK_BUS_MMC1 23
#define CLK_BUS_MMC2 24
#define CLK_BUS_NAND 25
#define CLK_BUS_DRAM 26
#define CLK_BUS_EMAC 27
#define CLK_BUS_TS 28
#define CLK_BUS_HSTIMER 29
#define CLK_BUS_SPI0 30
#define CLK_BUS_SPI1 31
#define CLK_BUS_OTG 32
#define CLK_BUS_EHCI0 33
#define CLK_BUS_EHCI1 34
#define CLK_BUS_EHCI2 35
#define CLK_BUS_EHCI3 36
#define CLK_BUS_OHCI0 37
#define CLK_BUS_OHCI1 38
#define CLK_BUS_OHCI2 39
#define CLK_BUS_OHCI3 40
#define CLK_BUS_VE 41
#define CLK_BUS_TCON0 42
#define CLK_BUS_TCON1 43
#define CLK_BUS_DEINTERLACE 44
#define CLK_BUS_CSI 45
#define CLK_BUS_TVE 46
#define CLK_BUS_HDMI 47
#define CLK_BUS_DE 48
#define CLK_BUS_GPU 49
#define CLK_BUS_MSGBOX 50
#define CLK_BUS_SPINLOCK 51
#define CLK_BUS_CODEC 52
#define CLK_BUS_SPDIF 53
#define CLK_BUS_PIO 54
#define CLK_BUS_THS 55
#define CLK_BUS_I2S0 56
#define CLK_BUS_I2S1 57
#define CLK_BUS_I2S2 58
#define CLK_BUS_I2C0 59
#define CLK_BUS_I2C1 60
#define CLK_BUS_I2C2 61
#define CLK_BUS_UART0 62
#define CLK_BUS_UART1 63
#define CLK_BUS_UART2 64
#define CLK_BUS_UART3 65
#define CLK_BUS_SCR0 66
#define CLK_BUS_EPHY 67
#define CLK_BUS_DBG 68
#define CLK_THS 69
#define CLK_NAND 70
#define CLK_MMC0 71
#define CLK_MMC0_SAMPLE 72
#define CLK_MMC0_OUTPUT 73
#define CLK_MMC1 74
#define CLK_MMC1_SAMPLE 75
#define CLK_MMC1_OUTPUT 76
#define CLK_MMC2 77
#define CLK_MMC2_SAMPLE 78
#define CLK_MMC2_OUTPUT 79
#define CLK_TS 80
#define CLK_CE 81
#define CLK_SPI0 82
#define CLK_SPI1 83
#define CLK_I2S0 84
#define CLK_I2S1 85
#define CLK_I2S2 86
#define CLK_SPDIF 87
#define CLK_USB_PHY0 88
#define CLK_USB_PHY1 89
#define CLK_USB_PHY2 90
#define CLK_USB_PHY3 91
#define CLK_USB_OHCI0 92
#define CLK_USB_OHCI1 93
#define CLK_USB_OHCI2 94
#define CLK_USB_OHCI3 95
#define CLK_DRAM 96
#define CLK_DRAM_VE 97
#define CLK_DRAM_CSI 98
#define CLK_DRAM_DEINTERLACE 99
#define CLK_DRAM_TS 100
#define CLK_DE 101
#define CLK_TCON0 102
#define CLK_TVE 103
#define CLK_DEINTERLACE 104
#define CLK_CSI_MISC 105
#define CLK_CSI_SCLK 106
#define CLK_CSI_MCLK 107
#define CLK_VE 108
#define CLK_AC_DIG 109
#define CLK_AVS 110
#define CLK_HDMI 111
#define CLK_HDMI_DDC 112
#define CLK_MBUS 113
#define CLK_GPU 114
/* New clocks imported in H5 */
#define CLK_BUS_SCR1 115
#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */

59
include/dt-bindings/clock/sun8i-r-ccu.h
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@ -1,59 +0,0 @@
/*
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
#define CLK_AR100 0
#define CLK_APB0_PIO 3
#define CLK_APB0_IR 4
#define CLK_APB0_TIMER 5
#define CLK_APB0_RSB 6
#define CLK_APB0_UART 7
/* 8 is reserved for CLK_APB0_W1 on A31 */
#define CLK_APB0_I2C 9
#define CLK_APB0_TWD 10
#define CLK_IR 11
#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */

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include/dt-bindings/clock/sun8i-r40-ccu.h
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@ -1,191 +0,0 @@
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
#define _DT_BINDINGS_CLK_SUN8I_R40_H_
#define CLK_PLL_VIDEO0 7
#define CLK_PLL_VIDEO1 16
#define CLK_CPU 24
#define CLK_BUS_MIPI_DSI 29
#define CLK_BUS_CE 30
#define CLK_BUS_DMA 31
#define CLK_BUS_MMC0 32
#define CLK_BUS_MMC1 33
#define CLK_BUS_MMC2 34
#define CLK_BUS_MMC3 35
#define CLK_BUS_NAND 36
#define CLK_BUS_DRAM 37
#define CLK_BUS_EMAC 38
#define CLK_BUS_TS 39
#define CLK_BUS_HSTIMER 40
#define CLK_BUS_SPI0 41
#define CLK_BUS_SPI1 42
#define CLK_BUS_SPI2 43
#define CLK_BUS_SPI3 44
#define CLK_BUS_SATA 45
#define CLK_BUS_OTG 46
#define CLK_BUS_EHCI0 47
#define CLK_BUS_EHCI1 48
#define CLK_BUS_EHCI2 49
#define CLK_BUS_OHCI0 50
#define CLK_BUS_OHCI1 51
#define CLK_BUS_OHCI2 52
#define CLK_BUS_VE 53
#define CLK_BUS_MP 54
#define CLK_BUS_DEINTERLACE 55
#define CLK_BUS_CSI0 56
#define CLK_BUS_CSI1 57
#define CLK_BUS_HDMI1 58
#define CLK_BUS_HDMI0 59
#define CLK_BUS_DE 60
#define CLK_BUS_TVE0 61
#define CLK_BUS_TVE1 62
#define CLK_BUS_TVE_TOP 63
#define CLK_BUS_GMAC 64
#define CLK_BUS_GPU 65
#define CLK_BUS_TVD0 66
#define CLK_BUS_TVD1 67
#define CLK_BUS_TVD2 68
#define CLK_BUS_TVD3 69
#define CLK_BUS_TVD_TOP 70
#define CLK_BUS_TCON_LCD0 71
#define CLK_BUS_TCON_LCD1 72
#define CLK_BUS_TCON_TV0 73
#define CLK_BUS_TCON_TV1 74
#define CLK_BUS_TCON_TOP 75
#define CLK_BUS_CODEC 76
#define CLK_BUS_SPDIF 77
#define CLK_BUS_AC97 78
#define CLK_BUS_PIO 79
#define CLK_BUS_IR0 80
#define CLK_BUS_IR1 81
#define CLK_BUS_THS 82
#define CLK_BUS_KEYPAD 83
#define CLK_BUS_I2S0 84
#define CLK_BUS_I2S1 85
#define CLK_BUS_I2S2 86
#define CLK_BUS_I2C0 87
#define CLK_BUS_I2C1 88
#define CLK_BUS_I2C2 89
#define CLK_BUS_I2C3 90
#define CLK_BUS_CAN 91
#define CLK_BUS_SCR 92
#define CLK_BUS_PS20 93
#define CLK_BUS_PS21 94
#define CLK_BUS_I2C4 95
#define CLK_BUS_UART0 96
#define CLK_BUS_UART1 97
#define CLK_BUS_UART2 98
#define CLK_BUS_UART3 99
#define CLK_BUS_UART4 100
#define CLK_BUS_UART5 101
#define CLK_BUS_UART6 102
#define CLK_BUS_UART7 103
#define CLK_BUS_DBG 104
#define CLK_THS 105
#define CLK_NAND 106
#define CLK_MMC0 107
#define CLK_MMC1 108
#define CLK_MMC2 109
#define CLK_MMC3 110
#define CLK_TS 111
#define CLK_CE 112
#define CLK_SPI0 113
#define CLK_SPI1 114
#define CLK_SPI2 115
#define CLK_SPI3 116
#define CLK_I2S0 117
#define CLK_I2S1 118
#define CLK_I2S2 119
#define CLK_AC97 120
#define CLK_SPDIF 121
#define CLK_KEYPAD 122
#define CLK_SATA 123
#define CLK_USB_PHY0 124
#define CLK_USB_PHY1 125
#define CLK_USB_PHY2 126
#define CLK_USB_OHCI0 127
#define CLK_USB_OHCI1 128
#define CLK_USB_OHCI2 129
#define CLK_IR0 130
#define CLK_IR1 131
#define CLK_DRAM_VE 133
#define CLK_DRAM_CSI0 134
#define CLK_DRAM_CSI1 135
#define CLK_DRAM_TS 136
#define CLK_DRAM_TVD 137
#define CLK_DRAM_MP 138
#define CLK_DRAM_DEINTERLACE 139
#define CLK_DE 140
#define CLK_MP 141
#define CLK_TCON_LCD0 142
#define CLK_TCON_LCD1 143
#define CLK_TCON_TV0 144
#define CLK_TCON_TV1 145
#define CLK_DEINTERLACE 146
#define CLK_CSI1_MCLK 147
#define CLK_CSI_SCLK 148
#define CLK_CSI0_MCLK 149
#define CLK_VE 150
#define CLK_CODEC 151
#define CLK_AVS 152
#define CLK_HDMI 153
#define CLK_HDMI_SLOW 154
#define CLK_MBUS 155
#define CLK_DSI_DPHY 156
#define CLK_TVE0 157
#define CLK_TVE1 158
#define CLK_TVD0 159
#define CLK_TVD1 160
#define CLK_TVD2 161
#define CLK_TVD3 162
#define CLK_GPU 163
#define CLK_OUTA 164
#define CLK_OUTB 165
#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */

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include/dt-bindings/clock/sun8i-tcon-top.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
#define CLK_TCON_TOP_TV0 0
#define CLK_TCON_TOP_TV1 1
#define CLK_TCON_TOP_DSI 2
#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */

111
include/dt-bindings/clock/sun8i-v3s-ccu.h
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/*
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on sun8i-h3-ccu.h, which is:
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
#define CLK_CPU 14
#define CLK_BUS_CE 20
#define CLK_BUS_DMA 21
#define CLK_BUS_MMC0 22
#define CLK_BUS_MMC1 23
#define CLK_BUS_MMC2 24
#define CLK_BUS_DRAM 25
#define CLK_BUS_EMAC 26
#define CLK_BUS_HSTIMER 27
#define CLK_BUS_SPI0 28
#define CLK_BUS_OTG 29
#define CLK_BUS_EHCI0 30
#define CLK_BUS_OHCI0 31
#define CLK_BUS_VE 32
#define CLK_BUS_TCON0 33
#define CLK_BUS_CSI 34
#define CLK_BUS_DE 35
#define CLK_BUS_CODEC 36
#define CLK_BUS_PIO 37
#define CLK_BUS_I2C0 38
#define CLK_BUS_I2C1 39
#define CLK_BUS_UART0 40
#define CLK_BUS_UART1 41
#define CLK_BUS_UART2 42
#define CLK_BUS_EPHY 43
#define CLK_BUS_DBG 44
#define CLK_MMC0 45
#define CLK_MMC0_SAMPLE 46
#define CLK_MMC0_OUTPUT 47
#define CLK_MMC1 48
#define CLK_MMC1_SAMPLE 49
#define CLK_MMC1_OUTPUT 50
#define CLK_MMC2 51
#define CLK_MMC2_SAMPLE 52
#define CLK_MMC2_OUTPUT 53
#define CLK_CE 54
#define CLK_SPI0 55
#define CLK_USB_PHY0 56
#define CLK_USB_OHCI0 57
#define CLK_DRAM_VE 59
#define CLK_DRAM_CSI 60
#define CLK_DRAM_EHCI 61
#define CLK_DRAM_OHCI 62
#define CLK_DE 63
#define CLK_TCON0 64
#define CLK_CSI_MISC 65
#define CLK_CSI0_MCLK 66
#define CLK_CSI1_SCLK 67
#define CLK_CSI1_MCLK 68
#define CLK_VE 69
#define CLK_AC_DIG 70
#define CLK_AVS 71
#define CLK_MIPI_CSI 73
/* Clocks not available on V3s */
#define CLK_BUS_I2S0 75
#define CLK_I2S0 76
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */

162
include/dt-bindings/clock/sun9i-a80-ccu.h
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@ -1,162 +0,0 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
#define CLK_PLL_AUDIO 2
#define CLK_PLL_PERIPH0 3
#define CLK_C0CPUX 12
#define CLK_C1CPUX 13
#define CLK_OUT_A 27
#define CLK_OUT_B 28
#define CLK_NAND0_0 29
#define CLK_NAND0_1 30
#define CLK_NAND1_0 31
#define CLK_NAND1_1 32
#define CLK_MMC0 33
#define CLK_MMC0_SAMPLE 34
#define CLK_MMC0_OUTPUT 35
#define CLK_MMC1 36
#define CLK_MMC1_SAMPLE 37
#define CLK_MMC1_OUTPUT 38
#define CLK_MMC2 39
#define CLK_MMC2_SAMPLE 40
#define CLK_MMC2_OUTPUT 41
#define CLK_MMC3 42
#define CLK_MMC3_SAMPLE 43
#define CLK_MMC3_OUTPUT 44
#define CLK_TS 45
#define CLK_SS 46
#define CLK_SPI0 47
#define CLK_SPI1 48
#define CLK_SPI2 49
#define CLK_SPI3 50
#define CLK_I2S0 51
#define CLK_I2S1 52
#define CLK_SPDIF 53
#define CLK_SDRAM 54
#define CLK_DE 55
#define CLK_EDP 56
#define CLK_MP 57
#define CLK_LCD0 58
#define CLK_LCD1 59
#define CLK_MIPI_DSI0 60
#define CLK_MIPI_DSI1 61
#define CLK_HDMI 62
#define CLK_HDMI_SLOW 63
#define CLK_MIPI_CSI 64
#define CLK_CSI_ISP 65
#define CLK_CSI_MISC 66
#define CLK_CSI0_MCLK 67
#define CLK_CSI1_MCLK 68
#define CLK_FD 69
#define CLK_VE 70
#define CLK_AVS 71
#define CLK_GPU_CORE 72
#define CLK_GPU_MEMORY 73
#define CLK_GPU_AXI 74
#define CLK_SATA 75
#define CLK_AC97 76
#define CLK_MIPI_HSI 77
#define CLK_GPADC 78
#define CLK_CIR_TX 79
#define CLK_BUS_FD 80
#define CLK_BUS_VE 81
#define CLK_BUS_GPU_CTRL 82
#define CLK_BUS_SS 83
#define CLK_BUS_MMC 84
#define CLK_BUS_NAND0 85
#define CLK_BUS_NAND1 86
#define CLK_BUS_SDRAM 87
#define CLK_BUS_MIPI_HSI 88
#define CLK_BUS_SATA 89
#define CLK_BUS_TS 90
#define CLK_BUS_SPI0 91
#define CLK_BUS_SPI1 92
#define CLK_BUS_SPI2 93
#define CLK_BUS_SPI3 94
#define CLK_BUS_OTG 95
#define CLK_BUS_USB 96
#define CLK_BUS_GMAC 97
#define CLK_BUS_MSGBOX 98
#define CLK_BUS_SPINLOCK 99
#define CLK_BUS_HSTIMER 100
#define CLK_BUS_DMA 101
#define CLK_BUS_LCD0 102
#define CLK_BUS_LCD1 103
#define CLK_BUS_EDP 104
#define CLK_BUS_CSI 105
#define CLK_BUS_HDMI 106
#define CLK_BUS_DE 107
#define CLK_BUS_MP 108
#define CLK_BUS_MIPI_DSI 109
#define CLK_BUS_SPDIF 110
#define CLK_BUS_PIO 111
#define CLK_BUS_AC97 112
#define CLK_BUS_I2S0 113
#define CLK_BUS_I2S1 114
#define CLK_BUS_LRADC 115
#define CLK_BUS_GPADC 116
#define CLK_BUS_TWD 117
#define CLK_BUS_CIR_TX 118
#define CLK_BUS_I2C0 119
#define CLK_BUS_I2C1 120
#define CLK_BUS_I2C2 121
#define CLK_BUS_I2C3 122
#define CLK_BUS_I2C4 123
#define CLK_BUS_UART0 124
#define CLK_BUS_UART1 125
#define CLK_BUS_UART2 126
#define CLK_BUS_UART3 127
#define CLK_BUS_UART4 128
#define CLK_BUS_UART5 129
#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */

80
include/dt-bindings/clock/sun9i-a80-de.h
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/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
#define CLK_FE0 0
#define CLK_FE1 1
#define CLK_FE2 2
#define CLK_IEP_DEU0 3
#define CLK_IEP_DEU1 4
#define CLK_BE0 5
#define CLK_BE1 6
#define CLK_BE2 7
#define CLK_IEP_DRC0 8
#define CLK_IEP_DRC1 9
#define CLK_MERGE 10
#define CLK_DRAM_FE0 11
#define CLK_DRAM_FE1 12
#define CLK_DRAM_FE2 13
#define CLK_DRAM_DEU0 14
#define CLK_DRAM_DEU1 15
#define CLK_DRAM_BE0 16
#define CLK_DRAM_BE1 17
#define CLK_DRAM_BE2 18
#define CLK_DRAM_DRC0 19
#define CLK_DRAM_DRC1 20
#define CLK_BUS_FE0 21
#define CLK_BUS_FE1 22
#define CLK_BUS_FE2 23
#define CLK_BUS_DEU0 24
#define CLK_BUS_DEU1 25
#define CLK_BUS_BE0 26
#define CLK_BUS_BE1 27
#define CLK_BUS_BE2 28
#define CLK_BUS_DRC0 29
#define CLK_BUS_DRC1 30
#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */

59
include/dt-bindings/clock/sun9i-a80-usb.h
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@ -1,59 +0,0 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
#define CLK_BUS_HCI0 0
#define CLK_USB_OHCI0 1
#define CLK_BUS_HCI1 2
#define CLK_BUS_HCI2 3
#define CLK_USB_OHCI2 4
#define CLK_USB0_PHY 5
#define CLK_USB1_HSIC 6
#define CLK_USB1_PHY 7
#define CLK_USB2_HSIC 8
#define CLK_USB2_PHY 9
#define CLK_USB_HSIC 10
#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */

72
include/dt-bindings/clock/suniv-ccu-f1c100s.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*
* Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
*
*/
#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
#define CLK_CPU 11
#define CLK_BUS_DMA 14
#define CLK_BUS_MMC0 15
#define CLK_BUS_MMC1 16
#define CLK_BUS_DRAM 17
#define CLK_BUS_SPI0 18
#define CLK_BUS_SPI1 19
#define CLK_BUS_OTG 20
#define CLK_BUS_VE 21
#define CLK_BUS_LCD 22
#define CLK_BUS_DEINTERLACE 23
#define CLK_BUS_CSI 24
#define CLK_BUS_TVD 25
#define CLK_BUS_TVE 26
#define CLK_BUS_DE_BE 27
#define CLK_BUS_DE_FE 28
#define CLK_BUS_CODEC 29
#define CLK_BUS_SPDIF 30
#define CLK_BUS_IR 31
#define CLK_BUS_RSB 32
#define CLK_BUS_I2S0 33
#define CLK_BUS_I2C0 34
#define CLK_BUS_I2C1 35
#define CLK_BUS_I2C2 36
#define CLK_BUS_PIO 37
#define CLK_BUS_UART0 38
#define CLK_BUS_UART1 39
#define CLK_BUS_UART2 40
#define CLK_MMC0 41
#define CLK_MMC0_SAMPLE 42
#define CLK_MMC0_OUTPUT 43
#define CLK_MMC1 44
#define CLK_MMC1_SAMPLE 45
#define CLK_MMC1_OUTPUT 46
#define CLK_I2S 47
#define CLK_SPDIF 48
#define CLK_USB_PHY0 49
#define CLK_DRAM_VE 50
#define CLK_DRAM_CSI 51
#define CLK_DRAM_DEINTERLACE 52
#define CLK_DRAM_TVD 53
#define CLK_DRAM_DE_FE 54
#define CLK_DRAM_DE_BE 55
#define CLK_DE_BE 56
#define CLK_DE_FE 57
#define CLK_TCON 58
#define CLK_DEINTERLACE 59
#define CLK_TVE2_CLK 60
#define CLK_TVE1_CLK 61
#define CLK_TVD 62
#define CLK_CSI 63
#define CLK_VE 64
#define CLK_CODEC 65
#define CLK_AVS 66
#define CLK_IR 67
#endif

13
include/dt-bindings/clock/versaclock.h
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/* SPDX-License-Identifier: GPL-2.0 */
/* This file defines field values used by the versaclock 6 family
* for defining output type
*/
#define VC5_LVPECL 0
#define VC5_CMOS 1
#define VC5_HCSL33 2
#define VC5_LVDS 3
#define VC5_CMOS2 4
#define VC5_CMOSD 5
#define VC5_HCSL25 6

202
include/dt-bindings/clock/vf610-clock.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_VF610_H
#define __DT_BINDINGS_CLOCK_VF610_H
#define VF610_CLK_DUMMY 0
#define VF610_CLK_SIRC_128K 1
#define VF610_CLK_SIRC_32K 2
#define VF610_CLK_FIRC 3
#define VF610_CLK_SXOSC 4
#define VF610_CLK_FXOSC 5
#define VF610_CLK_FXOSC_HALF 6
#define VF610_CLK_SLOW_CLK_SEL 7
#define VF610_CLK_FASK_CLK_SEL 8
#define VF610_CLK_AUDIO_EXT 9
#define VF610_CLK_ENET_EXT 10
#define VF610_CLK_PLL1_SYS 11
#define VF610_CLK_PLL1_PFD1 12
#define VF610_CLK_PLL1_PFD2 13
#define VF610_CLK_PLL1_PFD3 14
#define VF610_CLK_PLL1_PFD4 15
#define VF610_CLK_PLL2_BUS 16
#define VF610_CLK_PLL2_PFD1 17
#define VF610_CLK_PLL2_PFD2 18
#define VF610_CLK_PLL2_PFD3 19
#define VF610_CLK_PLL2_PFD4 20
#define VF610_CLK_PLL3_USB_OTG 21
#define VF610_CLK_PLL3_PFD1 22
#define VF610_CLK_PLL3_PFD2 23
#define VF610_CLK_PLL3_PFD3 24
#define VF610_CLK_PLL3_PFD4 25
#define VF610_CLK_PLL4_AUDIO 26
#define VF610_CLK_PLL5_ENET 27
#define VF610_CLK_PLL6_VIDEO 28
#define VF610_CLK_PLL3_MAIN_DIV 29
#define VF610_CLK_PLL4_MAIN_DIV 30
#define VF610_CLK_PLL6_MAIN_DIV 31
#define VF610_CLK_PLL1_PFD_SEL 32
#define VF610_CLK_PLL2_PFD_SEL 33
#define VF610_CLK_SYS_SEL 34
#define VF610_CLK_DDR_SEL 35
#define VF610_CLK_SYS_BUS 36
#define VF610_CLK_PLATFORM_BUS 37
#define VF610_CLK_IPG_BUS 38
#define VF610_CLK_UART0 39
#define VF610_CLK_UART1 40
#define VF610_CLK_UART2 41
#define VF610_CLK_UART3 42
#define VF610_CLK_UART4 43
#define VF610_CLK_UART5 44
#define VF610_CLK_PIT 45
#define VF610_CLK_I2C0 46
#define VF610_CLK_I2C1 47
#define VF610_CLK_I2C2 48
#define VF610_CLK_I2C3 49
#define VF610_CLK_FTM0_EXT_SEL 50
#define VF610_CLK_FTM0_FIX_SEL 51
#define VF610_CLK_FTM0_EXT_FIX_EN 52
#define VF610_CLK_FTM1_EXT_SEL 53
#define VF610_CLK_FTM1_FIX_SEL 54
#define VF610_CLK_FTM1_EXT_FIX_EN 55
#define VF610_CLK_FTM2_EXT_SEL 56
#define VF610_CLK_FTM2_FIX_SEL 57
#define VF610_CLK_FTM2_EXT_FIX_EN 58
#define VF610_CLK_FTM3_EXT_SEL 59
#define VF610_CLK_FTM3_FIX_SEL 60
#define VF610_CLK_FTM3_EXT_FIX_EN 61
#define VF610_CLK_FTM0 62
#define VF610_CLK_FTM1 63
#define VF610_CLK_FTM2 64
#define VF610_CLK_FTM3 65
#define VF610_CLK_ENET_50M 66
#define VF610_CLK_ENET_25M 67
#define VF610_CLK_ENET_SEL 68
#define VF610_CLK_ENET 69
#define VF610_CLK_ENET_TS_SEL 70
#define VF610_CLK_ENET_TS 71
#define VF610_CLK_DSPI0 72
#define VF610_CLK_DSPI1 73
#define VF610_CLK_DSPI2 74
#define VF610_CLK_DSPI3 75
#define VF610_CLK_WDT 76
#define VF610_CLK_ESDHC0_SEL 77
#define VF610_CLK_ESDHC0_EN 78
#define VF610_CLK_ESDHC0_DIV 79
#define VF610_CLK_ESDHC0 80
#define VF610_CLK_ESDHC1_SEL 81
#define VF610_CLK_ESDHC1_EN 82
#define VF610_CLK_ESDHC1_DIV 83
#define VF610_CLK_ESDHC1 84
#define VF610_CLK_DCU0_SEL 85
#define VF610_CLK_DCU0_EN 86
#define VF610_CLK_DCU0_DIV 87
#define VF610_CLK_DCU0 88
#define VF610_CLK_DCU1_SEL 89
#define VF610_CLK_DCU1_EN 90
#define VF610_CLK_DCU1_DIV 91
#define VF610_CLK_DCU1 92
#define VF610_CLK_ESAI_SEL 93
#define VF610_CLK_ESAI_EN 94
#define VF610_CLK_ESAI_DIV 95
#define VF610_CLK_ESAI 96
#define VF610_CLK_SAI0_SEL 97
#define VF610_CLK_SAI0_EN 98
#define VF610_CLK_SAI0_DIV 99
#define VF610_CLK_SAI0 100
#define VF610_CLK_SAI1_SEL 101
#define VF610_CLK_SAI1_EN 102
#define VF610_CLK_SAI1_DIV 103
#define VF610_CLK_SAI1 104
#define VF610_CLK_SAI2_SEL 105
#define VF610_CLK_SAI2_EN 106
#define VF610_CLK_SAI2_DIV 107
#define VF610_CLK_SAI2 108
#define VF610_CLK_SAI3_SEL 109
#define VF610_CLK_SAI3_EN 110
#define VF610_CLK_SAI3_DIV 111
#define VF610_CLK_SAI3 112
#define VF610_CLK_USBC0 113
#define VF610_CLK_USBC1 114
#define VF610_CLK_QSPI0_SEL 115
#define VF610_CLK_QSPI0_EN 116
#define VF610_CLK_QSPI0_X4_DIV 117
#define VF610_CLK_QSPI0_X2_DIV 118
#define VF610_CLK_QSPI0_X1_DIV 119
#define VF610_CLK_QSPI1_SEL 120
#define VF610_CLK_QSPI1_EN 121
#define VF610_CLK_QSPI1_X4_DIV 122
#define VF610_CLK_QSPI1_X2_DIV 123
#define VF610_CLK_QSPI1_X1_DIV 124
#define VF610_CLK_QSPI0 125
#define VF610_CLK_QSPI1 126
#define VF610_CLK_NFC_SEL 127
#define VF610_CLK_NFC_EN 128
#define VF610_CLK_NFC_PRE_DIV 129
#define VF610_CLK_NFC_FRAC_DIV 130
#define VF610_CLK_NFC_INV 131
#define VF610_CLK_NFC 132
#define VF610_CLK_VADC_SEL 133
#define VF610_CLK_VADC_EN 134
#define VF610_CLK_VADC_DIV 135
#define VF610_CLK_VADC_DIV_HALF 136
#define VF610_CLK_VADC 137
#define VF610_CLK_ADC0 138
#define VF610_CLK_ADC1 139
#define VF610_CLK_DAC0 140
#define VF610_CLK_DAC1 141
#define VF610_CLK_FLEXCAN0 142
#define VF610_CLK_FLEXCAN1 143
#define VF610_CLK_ASRC 144
#define VF610_CLK_GPU_SEL 145
#define VF610_CLK_GPU_EN 146
#define VF610_CLK_GPU2D 147
#define VF610_CLK_ENET0 148
#define VF610_CLK_ENET1 149
#define VF610_CLK_DMAMUX0 150
#define VF610_CLK_DMAMUX1 151
#define VF610_CLK_DMAMUX2 152
#define VF610_CLK_DMAMUX3 153
#define VF610_CLK_FLEXCAN0_EN 154
#define VF610_CLK_FLEXCAN1_EN 155
#define VF610_CLK_PLL7_USB_HOST 156
#define VF610_CLK_USBPHY0 157
#define VF610_CLK_USBPHY1 158
#define VF610_CLK_LVDS1_IN 159
#define VF610_CLK_ANACLK1 160
#define VF610_CLK_PLL1_BYPASS_SRC 161
#define VF610_CLK_PLL2_BYPASS_SRC 162
#define VF610_CLK_PLL3_BYPASS_SRC 163
#define VF610_CLK_PLL4_BYPASS_SRC 164
#define VF610_CLK_PLL5_BYPASS_SRC 165
#define VF610_CLK_PLL6_BYPASS_SRC 166
#define VF610_CLK_PLL7_BYPASS_SRC 167
#define VF610_CLK_PLL1 168
#define VF610_CLK_PLL2 169
#define VF610_CLK_PLL3 170
#define VF610_CLK_PLL4 171
#define VF610_CLK_PLL5 172
#define VF610_CLK_PLL6 173
#define VF610_CLK_PLL7 174
#define VF610_PLL1_BYPASS 175
#define VF610_PLL2_BYPASS 176
#define VF610_PLL3_BYPASS 177
#define VF610_PLL4_BYPASS 178
#define VF610_PLL5_BYPASS 179
#define VF610_PLL6_BYPASS 180
#define VF610_PLL7_BYPASS 181
#define VF610_CLK_SNVS 182
#define VF610_CLK_DAP 183
#define VF610_CLK_OCOTP 184
#define VF610_CLK_DDRMC 185
#define VF610_CLK_WKPU 186
#define VF610_CLK_TCON0 187
#define VF610_CLK_TCON1 188
#define VF610_CLK_CAAM 189
#define VF610_CLK_CRC 190
#define VF610_CLK_END 191
#endif /* __DT_BINDINGS_CLOCK_VF610_H */

8
include/dt-bindings/display/tda998x.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_TDA998X_H
#define _DT_BINDINGS_TDA998X_H
#define TDA998x_SPDIF 1
#define TDA998x_I2S 2
#endif /*_DT_BINDINGS_TDA998X_H */

56
include/dt-bindings/dma/sun4i-a10.h
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/*
* Copyright 2014 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_
#define __DT_BINDINGS_DMA_SUN4I_A10_H_
#define SUN4I_DMA_NORMAL 0
#define SUN4I_DMA_DEDICATED 1
#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */

16
include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define ZYNQMP_DPDMA_VIDEO0 0
#define ZYNQMP_DPDMA_VIDEO1 1
#define ZYNQMP_DPDMA_VIDEO2 2
#define ZYNQMP_DPDMA_GRAPHICS 3
#define ZYNQMP_DPDMA_AUDIO0 4
#define ZYNQMP_DPDMA_AUDIO1 5
#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */

18
include/dt-bindings/gpio/uniphier-gpio.h
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/*
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H
#define _DT_BINDINGS_GPIO_UNIPHIER_H
#define UNIPHIER_GPIO_LINES_PER_BANK 8
#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15)
#define UNIPHIER_GPIO_PORT(bank, line) \
((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))
#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n))
#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */

18
include/dt-bindings/leds/leds-pca9532.h
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/*
* This header provides constants for pca9532 LED bindings.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef _DT_BINDINGS_LEDS_PCA9532_H
#define _DT_BINDINGS_LEDS_PCA9532_H
#define PCA9532_TYPE_NONE 0
#define PCA9532_TYPE_LED 1
#define PCA9532_TYPE_N2100_BEEP 2
#define PCA9532_TYPE_GPIO 3
#define PCA9532_LED_TIMER2 4
#endif /* _DT_BINDINGS_LEDS_PCA9532_H */

74
include/dt-bindings/media/tda1997x.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017 Gateworks Corporation
*/
#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H
#define _DT_BINDINGS_MEDIA_TDA1997X_H
/* TDA19973 36bit Video Port control registers */
#define TDA1997X_VP36_35_32 0
#define TDA1997X_VP36_31_28 1
#define TDA1997X_VP36_27_24 2
#define TDA1997X_VP36_23_20 3
#define TDA1997X_VP36_19_16 4
#define TDA1997X_VP36_15_12 5
#define TDA1997X_VP36_11_08 6
#define TDA1997X_VP36_07_04 7
#define TDA1997X_VP36_03_00 8
/* TDA19971 24bit Video Port control registers */
#define TDA1997X_VP24_V23_20 0
#define TDA1997X_VP24_V19_16 1
#define TDA1997X_VP24_V15_12 3
#define TDA1997X_VP24_V11_08 4
#define TDA1997X_VP24_V07_04 6
#define TDA1997X_VP24_V03_00 7
/* Pin groups */
#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */
#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */
#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */
#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ)
/* pinswapped groups */
#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP)
#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP)
#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP)
#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP)
#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP)
#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP)
#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP)
#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP)
#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP)
/* Audio bus DAI format */
#define TDA1997X_I2S16 1 /* I2S 16bit */
#define TDA1997X_I2S32 2 /* I2S 32bit */
#define TDA1997X_SPDIF 3 /* SPDIF */
#define TDA1997X_OBA 4 /* One Bit Audio */
#define TDA1997X_DST 5 /* Direct Stream Transfer */
#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */
#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */
#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */
#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */
/* Audio bus channel layout */
#define TDA1997X_LAYOUT0 0 /* 2-channel */
#define TDA1997X_LAYOUT1 1 /* 8-channel */
/* Audio bus clock */
#define TDA1997X_ACLK_16FS 0
#define TDA1997X_ACLK_32FS 1
#define TDA1997X_ACLK_64FS 2
#define TDA1997X_ACLK_128FS 3
#define TDA1997X_ACLK_256FS 4
#define TDA1997X_ACLK_512FS 5
#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */

17
include/dt-bindings/mfd/at91-usart.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides macros for AT91 USART DT bindings.
*
* Copyright (C) 2018 Microchip Technology
*
* Author: Radu Pirea <radu.pirea@microchip.com>
*
*/
#ifndef __DT_BINDINGS_AT91_USART_H__
#define __DT_BINDINGS_AT91_USART_H__
#define AT91_USART_MODE_SERIAL 0
#define AT91_USART_MODE_SPI 1
#endif /* __DT_BINDINGS_AT91_USART_H__ */

15
include/dt-bindings/mfd/atmel-flexcom.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides macros for Atmel Flexcom DT bindings.
*
* Copyright (C) 2015 Cyrille Pitchen <cyrille.pitchen@atmel.com>
*/
#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__
#define __DT_BINDINGS_ATMEL_FLEXCOM_H__
#define ATMEL_FLEXCOM_MODE_USART 1
#define ATMEL_FLEXCOM_MODE_SPI 2
#define ATMEL_FLEXCOM_MODE_TWI 3
#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */

21
include/dt-bindings/net/microchip-lan78xx.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H
#define _DT_BINDINGS_MICROCHIP_LAN78XX_H
/* LED modes for LAN7800/LAN7850 embedded PHY */
#define LAN78XX_LINK_ACTIVITY 0
#define LAN78XX_LINK_1000_ACTIVITY 1
#define LAN78XX_LINK_100_ACTIVITY 2
#define LAN78XX_LINK_10_ACTIVITY 3
#define LAN78XX_LINK_100_1000_ACTIVITY 4
#define LAN78XX_LINK_10_1000_ACTIVITY 5
#define LAN78XX_LINK_10_100_ACTIVITY 6
#define LAN78XX_DUPLEX_COLLISION 8
#define LAN78XX_COLLISION 9
#define LAN78XX_ACTIVITY 10
#define LAN78XX_AUTONEG_FAULT 12
#define LAN78XX_FORCE_LED_OFF 14
#define LAN78XX_FORCE_LED_ON 15
#endif

13
include/dt-bindings/net/qca-ar803x.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Device Tree constants for the Qualcomm Atheros AR803x PHYs
*/
#ifndef _DT_BINDINGS_QCA_AR803X_H
#define _DT_BINDINGS_QCA_AR803X_H
#define AR803X_STRENGTH_FULL 0
#define AR803X_STRENGTH_HALF 1
#define AR803X_STRENGTH_QUARTER 2
#endif

21
include/dt-bindings/phy/phy-ti.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for TI SERDES.
*/
#ifndef _DT_BINDINGS_TI_SERDES
#define _DT_BINDINGS_TI_SERDES
/* Clock index for output clocks from WIZ */
/* MUX Clocks */
#define TI_WIZ_PLL0_REFCLK 0
#define TI_WIZ_PLL1_REFCLK 1
#define TI_WIZ_REFCLK_DIG 2
/* Reserve index here for future additions */
/* MISC Clocks */
#define TI_WIZ_PHY_EN_REFCLK 16
#endif /* _DT_BINDINGS_TI_SERDES */

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include/dt-bindings/pinctrl/am33xx.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants specific to AM33XX pinctrl bindings.
*/
#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
#define _DT_BINDINGS_PINCTRL_AM33XX_H
#include <dt-bindings/pinctrl/omap.h>
/* am33xx specific mux bit defines */
#undef PULL_ENA
#undef INPUT_EN
#define PULL_DISABLE (1 << 3)
#define INPUT_EN (1 << 5)
#define SLEWCTRL_SLOW (1 << 6)
#define SLEWCTRL_FAST 0
/* update macro depending on INPUT_EN and PULL_ENA */
#undef PIN_OUTPUT
#undef PIN_OUTPUT_PULLUP
#undef PIN_OUTPUT_PULLDOWN
#undef PIN_INPUT
#undef PIN_INPUT_PULLUP
#undef PIN_INPUT_PULLDOWN
#define PIN_OUTPUT (PULL_DISABLE)
#define PIN_OUTPUT_PULLUP (PULL_UP)
#define PIN_OUTPUT_PULLDOWN 0
#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (INPUT_EN)
/* undef non-existing modes */
#undef PIN_OFF_NONE
#undef PIN_OFF_OUTPUT_HIGH
#undef PIN_OFF_OUTPUT_LOW
#undef PIN_OFF_INPUT_PULLUP
#undef PIN_OFF_INPUT_PULLDOWN
#undef PIN_OFF_WAKEUPENABLE
#define AM335X_PIN_OFFSET_MIN 0x0800U
#define AM335X_PIN_GPMC_AD0 0x800
#define AM335X_PIN_GPMC_AD1 0x804
#define AM335X_PIN_GPMC_AD2 0x808
#define AM335X_PIN_GPMC_AD3 0x80c
#define AM335X_PIN_GPMC_AD4 0x810
#define AM335X_PIN_GPMC_AD5 0x814
#define AM335X_PIN_GPMC_AD6 0x818
#define AM335X_PIN_GPMC_AD7 0x81c
#define AM335X_PIN_GPMC_AD8 0x820
#define AM335X_PIN_GPMC_AD9 0x824
#define AM335X_PIN_GPMC_AD10 0x828
#define AM335X_PIN_GPMC_AD11 0x82c
#define AM335X_PIN_GPMC_AD12 0x830
#define AM335X_PIN_GPMC_AD13 0x834
#define AM335X_PIN_GPMC_AD14 0x838
#define AM335X_PIN_GPMC_AD15 0x83c
#define AM335X_PIN_GPMC_A0 0x840
#define AM335X_PIN_GPMC_A1 0x844
#define AM335X_PIN_GPMC_A2 0x848
#define AM335X_PIN_GPMC_A3 0x84c
#define AM335X_PIN_GPMC_A4 0x850
#define AM335X_PIN_GPMC_A5 0x854
#define AM335X_PIN_GPMC_A6 0x858
#define AM335X_PIN_GPMC_A7 0x85c
#define AM335X_PIN_GPMC_A8 0x860
#define AM335X_PIN_GPMC_A9 0x864
#define AM335X_PIN_GPMC_A10 0x868
#define AM335X_PIN_GPMC_A11 0x86c
#define AM335X_PIN_GPMC_WAIT0 0x870
#define AM335X_PIN_GPMC_WPN 0x874
#define AM335X_PIN_GPMC_BEN1 0x878
#define AM335X_PIN_GPMC_CSN0 0x87c
#define AM335X_PIN_GPMC_CSN1 0x880
#define AM335X_PIN_GPMC_CSN2 0x884
#define AM335X_PIN_GPMC_CSN3 0x888
#define AM335X_PIN_GPMC_CLK 0x88c
#define AM335X_PIN_GPMC_ADVN_ALE 0x890
#define AM335X_PIN_GPMC_OEN_REN 0x894
#define AM335X_PIN_GPMC_WEN 0x898
#define AM335X_PIN_GPMC_BEN0_CLE 0x89c
#define AM335X_PIN_LCD_DATA0 0x8a0
#define AM335X_PIN_LCD_DATA1 0x8a4
#define AM335X_PIN_LCD_DATA2 0x8a8
#define AM335X_PIN_LCD_DATA3 0x8ac
#define AM335X_PIN_LCD_DATA4 0x8b0
#define AM335X_PIN_LCD_DATA5 0x8b4
#define AM335X_PIN_LCD_DATA6 0x8b8
#define AM335X_PIN_LCD_DATA7 0x8bc
#define AM335X_PIN_LCD_DATA8 0x8c0
#define AM335X_PIN_LCD_DATA9 0x8c4
#define AM335X_PIN_LCD_DATA10 0x8c8
#define AM335X_PIN_LCD_DATA11 0x8cc
#define AM335X_PIN_LCD_DATA12 0x8d0
#define AM335X_PIN_LCD_DATA13 0x8d4
#define AM335X_PIN_LCD_DATA14 0x8d8
#define AM335X_PIN_LCD_DATA15 0x8dc
#define AM335X_PIN_LCD_VSYNC 0x8e0
#define AM335X_PIN_LCD_HSYNC 0x8e4
#define AM335X_PIN_LCD_PCLK 0x8e8
#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec
#define AM335X_PIN_MMC0_DAT3 0x8f0
#define AM335X_PIN_MMC0_DAT2 0x8f4
#define AM335X_PIN_MMC0_DAT1 0x8f8
#define AM335X_PIN_MMC0_DAT0 0x8fc
#define AM335X_PIN_MMC0_CLK 0x900
#define AM335X_PIN_MMC0_CMD 0x904
#define AM335X_PIN_MII1_COL 0x908
#define AM335X_PIN_MII1_CRS 0x90c
#define AM335X_PIN_MII1_RX_ER 0x910
#define AM335X_PIN_MII1_TX_EN 0x914
#define AM335X_PIN_MII1_RX_DV 0x918
#define AM335X_PIN_MII1_TXD3 0x91c
#define AM335X_PIN_MII1_TXD2 0x920
#define AM335X_PIN_MII1_TXD1 0x924
#define AM335X_PIN_MII1_TXD0 0x928
#define AM335X_PIN_MII1_TX_CLK 0x92c
#define AM335X_PIN_MII1_RX_CLK 0x930
#define AM335X_PIN_MII1_RXD3 0x934
#define AM335X_PIN_MII1_RXD2 0x938
#define AM335X_PIN_MII1_RXD1 0x93c
#define AM335X_PIN_MII1_RXD0 0x940
#define AM335X_PIN_RMII1_REF_CLK 0x944
#define AM335X_PIN_MDIO 0x948
#define AM335X_PIN_MDC 0x94c
#define AM335X_PIN_SPI0_SCLK 0x950
#define AM335X_PIN_SPI0_D0 0x954
#define AM335X_PIN_SPI0_D1 0x958
#define AM335X_PIN_SPI0_CS0 0x95c
#define AM335X_PIN_SPI0_CS1 0x960
#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964
#define AM335X_PIN_UART0_CTSN 0x968
#define AM335X_PIN_UART0_RTSN 0x96c
#define AM335X_PIN_UART0_RXD 0x970
#define AM335X_PIN_UART0_TXD 0x974
#define AM335X_PIN_UART1_CTSN 0x978
#define AM335X_PIN_UART1_RTSN 0x97c
#define AM335X_PIN_UART1_RXD 0x980
#define AM335X_PIN_UART1_TXD 0x984
#define AM335X_PIN_I2C0_SDA 0x988
#define AM335X_PIN_I2C0_SCL 0x98c
#define AM335X_PIN_MCASP0_ACLKX 0x990
#define AM335X_PIN_MCASP0_FSX 0x994
#define AM335X_PIN_MCASP0_AXR0 0x998
#define AM335X_PIN_MCASP0_AHCLKR 0x99c
#define AM335X_PIN_MCASP0_ACLKR 0x9a0
#define AM335X_PIN_MCASP0_FSR 0x9a4
#define AM335X_PIN_MCASP0_AXR1 0x9a8
#define AM335X_PIN_MCASP0_AHCLKX 0x9ac
#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0
#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4
#define AM335X_PIN_WARMRSTN 0x9b8
#define AM335X_PIN_NNMI 0x9c0
#define AM335X_PIN_TMS 0x9d0
#define AM335X_PIN_TDI 0x9d4
#define AM335X_PIN_TDO 0x9d8
#define AM335X_PIN_TCK 0x9dc
#define AM335X_PIN_TRSTN 0x9e0
#define AM335X_PIN_EMU0 0x9e4
#define AM335X_PIN_EMU1 0x9e8
#define AM335X_PIN_RTC_PWRONRSTN 0x9f8
#define AM335X_PIN_PMIC_POWER_EN 0x9fc
#define AM335X_PIN_EXT_WAKEUP 0xa00
#define AM335X_PIN_USB0_DRVVBUS 0xa1c
#define AM335X_PIN_USB1_DRVVBUS 0xa34
#define AM335X_PIN_OFFSET_MAX 0x0a34U
#endif

13
include/dt-bindings/pinctrl/apple.h
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/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
* This header provides constants for Apple pinctrl bindings.
*/
#ifndef _DT_BINDINGS_PINCTRL_APPLE_H
#define _DT_BINDINGS_PINCTRL_APPLE_H
#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16))
#define APPLE_PIN(pinmux) ((pinmux) & 0xffff)
#define APPLE_FUNC(pinmux) ((pinmux) >> 16)
#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */

26
include/dt-bindings/pinctrl/bcm2835.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Header providing constants for bcm2835 pinctrl bindings.
*
* Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com>
*/
#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__
#define __DT_BINDINGS_PINCTRL_BCM2835_H__
/* brcm,function property */
#define BCM2835_FSEL_GPIO_IN 0
#define BCM2835_FSEL_GPIO_OUT 1
#define BCM2835_FSEL_ALT5 2
#define BCM2835_FSEL_ALT4 3
#define BCM2835_FSEL_ALT0 4
#define BCM2835_FSEL_ALT1 5
#define BCM2835_FSEL_ALT2 6
#define BCM2835_FSEL_ALT3 7
/* brcm,pull property */
#define BCM2835_PUD_OFF 0
#define BCM2835_PUD_DOWN 1
#define BCM2835_PUD_UP 2
#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */

858
include/dt-bindings/pinctrl/mt8365-pinfunc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#ifndef __MT8365_PINFUNC_H
#define __MT8365_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1)
#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2)
#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5)
#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1)
#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2)
#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3)
#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5)
#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7)
#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1)
#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2)
#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3)
#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5)
#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7)
#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1)
#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2)
#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3)
#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5)
#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6)
#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7)
#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1)
#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2)
#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3)
#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5)
#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6)
#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7)
#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1)
#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2)
#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3)
#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5)
#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6)
#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7)
#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1)
#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2)
#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3)
#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5)
#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6)
#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7)
#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1)
#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3)
#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5)
#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7)
#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1)
#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2)
#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3)
#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5)
#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7)
#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1)
#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2)
#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3)
#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5)
#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7)
#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1)
#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2)
#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3)
#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5)
#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7)
#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1)
#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2)
#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3)
#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4)
#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5)
#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7)
#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1)
#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2)
#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3)
#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4)
#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5)
#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7)
#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1)
#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2)
#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3)
#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4)
#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5)
#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7)
#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1)
#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2)
#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3)
#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4)
#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5)
#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6)
#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7)
#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1)
#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2)
#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3)
#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4)
#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5)
#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6)
#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7)
#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1)
#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2)
#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3)
#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4)
#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5)
#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6)
#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7)
#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1)
#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2)
#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3)
#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4)
#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5)
#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6)
#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7)
#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1)
#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2)
#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3)
#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4)
#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5)
#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6)
#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7)
#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1)
#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2)
#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7)
#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1)
#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2)
#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7)
#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1)
#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2)
#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3)
#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4)
#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7)
#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1)
#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7)
#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1)
#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2)
#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3)
#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4)
#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5)
#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6)
#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7)
#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1)
#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7)
#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1)
#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2)
#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3)
#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4)
#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5)
#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6)
#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7)
#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1)
#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3)
#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4)
#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5)
#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6)
#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7)
#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1)
#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3)
#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4)
#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5)
#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6)
#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7)
#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1)
#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2)
#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3)
#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4)
#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5)
#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6)
#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7)
#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1)
#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2)
#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3)
#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4)
#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5)
#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6)
#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7)
#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1)
#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2)
#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3)
#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4)
#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5)
#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6)
#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1)
#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2)
#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3)
#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4)
#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5)
#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6)
#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1)
#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2)
#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3)
#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4)
#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5)
#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1)
#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2)
#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3)
#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4)
#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5)
#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1)
#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2)
#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3)
#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4)
#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5)
#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1)
#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2)
#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7)
#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1)
#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2)
#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7)
#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1)
#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2)
#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3)
#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4)
#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5)
#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6)
#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7)
#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1)
#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2)
#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3)
#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4)
#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5)
#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6)
#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7)
#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1)
#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2)
#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3)
#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4)
#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5)
#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6)
#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7)
#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1)
#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2)
#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3)
#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4)
#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5)
#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6)
#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7)
#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1)
#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2)
#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1)
#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2)
#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1)
#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1)
#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1)
#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1)
#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1)
#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2)
#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1)
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1)
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2)
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3)
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1)
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2)
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3)
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1)
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2)
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3)
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1)
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2)
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3)
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1)
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2)
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3)
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1)
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2)
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3)
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1)
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2)
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3)
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1)
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2)
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3)
#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1)
#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1)
#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1)
#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6)
#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7)
#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1)
#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6)
#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7)
#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1)
#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1)
#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1)
#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1)
#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1)
#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2)
#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7)
#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1)
#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2)
#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7)
#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1)
#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2)
#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4)
#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5)
#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7)
#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1)
#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2)
#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4)
#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5)
#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7)
#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1)
#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2)
#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3)
#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4)
#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5)
#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7)
#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1)
#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2)
#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4)
#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5)
#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7)
#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1)
#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2)
#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7)
#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1)
#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2)
#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5)
#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7)
#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1)
#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2)
#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5)
#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7)
#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1)
#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2)
#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5)
#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7)
#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1)
#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5)
#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7)
#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1)
#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5)
#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7)
#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1)
#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5)
#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7)
#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1)
#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5)
#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7)
#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1)
#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5)
#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7)
#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1)
#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2)
#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3)
#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4)
#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5)
#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6)
#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1)
#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2)
#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3)
#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4)
#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5)
#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6)
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1)
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2)
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3)
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4)
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5)
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6)
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1)
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2)
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3)
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4)
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5)
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6)
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1)
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2)
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3)
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4)
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5)
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6)
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1)
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2)
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3)
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5)
#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1)
#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2)
#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6)
#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6)
#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6)
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6)
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6)
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7)
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1)
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2)
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3)
#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1)
#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2)
#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1)
#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2)
#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1)
#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2)
#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1)
#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2)
#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1)
#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2)
#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1)
#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2)
#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1)
#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2)
#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1)
#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2)
#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1)
#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2)
#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1)
#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2)
#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1)
#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2)
#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1)
#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1)
#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2)
#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7)
#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1)
#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2)
#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7)
#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1)
#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2)
#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7)
#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1)
#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2)
#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7)
#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1)
#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2)
#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7)
#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1)
#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2)
#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3)
#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4)
#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5)
#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1)
#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2)
#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3)
#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4)
#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5)
#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1)
#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2)
#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3)
#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4)
#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5)
#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1)
#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2)
#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3)
#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4)
#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6)
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7)
#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1)
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2)
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3)
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4)
#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5)
#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6)
#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7)
#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1)
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2)
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3)
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4)
#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5)
#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6)
#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7)
#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1)
#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2)
#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7)
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1)
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2)
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7)
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1)
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2)
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7)
#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1)
#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2)
#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7)
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1)
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2)
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7)
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1)
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2)
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7)
#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1)
#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2)
#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7)
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1)
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2)
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7)
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1)
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2)
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7)
#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1)
#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2)
#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1)
#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2)
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1)
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2)
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3)
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1)
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2)
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3)
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1)
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2)
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3)
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1)
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2)
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3)
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1)
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2)
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3)
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7)
#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1)
#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7)
#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1)
#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7)
#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1)
#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7)
#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1)
#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1)
#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1)
#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1)
#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1)
#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1)
#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1)
#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1)
#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1)
#endif /* __MT8365_PINFUNC_H */

19
include/dt-bindings/pinctrl/pinctrl-zynqmp.h
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@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* MIO pin configuration defines for Xilinx ZynqMP
*
* Copyright (C) 2020 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
/* Bit value for different voltage levels */
#define IO_STANDARD_LVCMOS33 0
#define IO_STANDARD_LVCMOS18 1
/* Bit values for Slew Rates */
#define SLEW_RATE_FAST 0
#define SLEW_RATE_SLOW 1
#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */

141
include/dt-bindings/pinctrl/rzn1-pinctrl.h
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@ -1,141 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Defines macros and constants for Renesas RZ/N1 pin controller pin
* muxing functions.
*/
#ifndef __DT_BINDINGS_RZN1_PINCTRL_H
#define __DT_BINDINGS_RZN1_PINCTRL_H
#define RZN1_PINMUX(_gpio, _func) \
(((_func) << 8) | (_gpio))
/*
* Given the different levels of muxing on the SoC, it was decided to
* 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO
* muxes are all represented by one single value.
*
* You can derive the hardware value pretty easily too, as
* 0...9 are Level 1
* 10...71 are Level 2. The Level 2 mux will be set to this
* value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be
* set accordingly.
* 72...103 are for the 2 MDIO muxes.
*/
#define RZN1_FUNC_HIGHZ 0
#define RZN1_FUNC_0L 1
#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2
#define RZN1_FUNC_CLK_ETH_NAND 3
#define RZN1_FUNC_QSPI 4
#define RZN1_FUNC_SDIO 5
#define RZN1_FUNC_LCD 6
#define RZN1_FUNC_LCD_E 7
#define RZN1_FUNC_MSEBIM 8
#define RZN1_FUNC_MSEBIS 9
#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */
#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0)
#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1)
#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2)
#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3)
#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4)
#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5)
#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6)
#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7)
#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8)
#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9)
#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10)
#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11)
#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12)
#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13)
#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14)
#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15)
#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16)
#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17)
#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18)
#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19)
#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20)
#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21)
#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22)
#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23)
#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24)
#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25)
#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26)
#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27)
#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28)
#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29)
#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30)
#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31)
#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32)
#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33)
#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34)
#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35)
#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36)
#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37)
#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38)
#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39)
#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40)
#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41)
#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42)
#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43)
#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44)
#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45)
#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46)
#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47)
#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48)
#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49)
#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50)
#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51)
#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52)
#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53)
#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54)
#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55)
#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56)
#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57)
#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58)
#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59)
#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60)
#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61)
#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62)
/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */
#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0)
#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1)
#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2)
#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3)
#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4)
#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5)
#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6)
#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7)
/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8)
#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9)
#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10)
#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11)
#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12)
#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13)
#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14)
#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15)
/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */
#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16)
#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17)
#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18)
#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19)
#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20)
#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21)
#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22)
#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23)
/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24)
#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25)
#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26)
#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27)
#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28)
#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29)
#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30)
#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31)
#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32)
#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */

62
include/dt-bindings/pinctrl/sun4i-a10.h
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@ -1,62 +0,0 @@
/*
* Copyright 2014 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
#define SUN4I_PINCTRL_10_MA 0
#define SUN4I_PINCTRL_20_MA 1
#define SUN4I_PINCTRL_30_MA 2
#define SUN4I_PINCTRL_40_MA 3
#define SUN4I_PINCTRL_NO_PULL 0
#define SUN4I_PINCTRL_PULL_UP 1
#define SUN4I_PINCTRL_PULL_DOWN 2
#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */

19
include/dt-bindings/power/mediatek,mt8365-power.h
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@ -1,19 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2022 MediaTek Inc.
*/
#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
#define _DT_BINDINGS_POWER_MT8365_POWER_H
#define MT8365_POWER_DOMAIN_MM 0
#define MT8365_POWER_DOMAIN_CONN 1
#define MT8365_POWER_DOMAIN_MFG 2
#define MT8365_POWER_DOMAIN_AUDIO 3
#define MT8365_POWER_DOMAIN_CAM 4
#define MT8365_POWER_DOMAIN_DSP 5
#define MT8365_POWER_DOMAIN_VDEC 6
#define MT8365_POWER_DOMAIN_VENC 7
#define MT8365_POWER_DOMAIN_APU 8
#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */

19
include/dt-bindings/power/owl-s700-powergate.h
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@ -1,19 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Actions Semi S700 SPS
*
* Copyright (c) 2017 Andreas Färber
*/
#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H
#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H
#define S700_PD_VDE 0
#define S700_PD_VCE_SI 1
#define S700_PD_USB2_1 2
#define S700_PD_HDE 3
#define S700_PD_DMA 4
#define S700_PD_DS 5
#define S700_PD_USB3 6
#define S700_PD_USB2_0 7
#endif

21
include/dt-bindings/power/rk3228-power.h
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@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__
#define __DT_BINDINGS_POWER_RK3228_POWER_H__
/**
* RK3228 idle id Summary.
*/
#define RK3228_PD_CORE 0
#define RK3228_PD_MSCH 1
#define RK3228_PD_BUS 2
#define RK3228_PD_SYS 3
#define RK3228_PD_VIO 4
#define RK3228_PD_VOP 5
#define RK3228_PD_VPU 6
#define RK3228_PD_RKVDEC 7
#define RK3228_PD_GPU 8
#define RK3228_PD_PERI 9
#define RK3228_PD_GMAC 10
#endif

45
include/dt-bindings/power/xlnx-zynqmp-power.h
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@ -1,45 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
#define _DT_BINDINGS_ZYNQMP_POWER_H
#define PD_RPU_0 7
#define PD_RPU_1 8
#define PD_R5_0_ATCM 15
#define PD_R5_0_BTCM 16
#define PD_R5_1_ATCM 17
#define PD_R5_1_BTCM 18
#define PD_USB_0 22
#define PD_USB_1 23
#define PD_TTC_0 24
#define PD_TTC_1 25
#define PD_TTC_2 26
#define PD_TTC_3 27
#define PD_SATA 28
#define PD_ETH_0 29
#define PD_ETH_1 30
#define PD_ETH_2 31
#define PD_ETH_3 32
#define PD_UART_0 33
#define PD_UART_1 34
#define PD_SPI_0 35
#define PD_SPI_1 36
#define PD_I2C_0 37
#define PD_I2C_1 38
#define PD_SD_0 39
#define PD_SD_1 40
#define PD_DP 41
#define PD_GDMA 42
#define PD_ADMA 43
#define PD_NAND 44
#define PD_QSPI 45
#define PD_GPIO 46
#define PD_CAN_0 47
#define PD_CAN_1 48
#define PD_GPU 58
#define PD_PCIE 59
#endif

16
include/dt-bindings/regulator/dlg,da9063-regulator.h
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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H
#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H
/*
* These buck mode constants may be used to specify values in device tree
* properties (e.g. regulator-initial-mode).
* A description of the following modes is in the manufacturers datasheet.
*/
#define DA9063_BUCK_MODE_SLEEP 1
#define DA9063_BUCK_MODE_SYNC 2
#define DA9063_BUCK_MODE_AUTO 3
#endif

34
include/dt-bindings/reset/actions,s700-reset.h
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@ -1,34 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
//
// Device Tree binding constants for Actions Semi S700 Reset Management Unit
//
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H
#define __DT_BINDINGS_ACTIONS_S700_RESET_H
#define RESET_AUDIO 0
#define RESET_CSI 1
#define RESET_DE 2
#define RESET_DSI 3
#define RESET_GPIO 4
#define RESET_I2C0 5
#define RESET_I2C1 6
#define RESET_I2C2 7
#define RESET_I2C3 8
#define RESET_KEY 9
#define RESET_LCD0 10
#define RESET_SI 11
#define RESET_SPI0 12
#define RESET_SPI1 13
#define RESET_SPI2 14
#define RESET_SPI3 15
#define RESET_UART0 16
#define RESET_UART1 17
#define RESET_UART2 18
#define RESET_UART3 19
#define RESET_UART4 20
#define RESET_UART5 21
#define RESET_UART6 22
#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */

65
include/dt-bindings/reset/actions,s900-reset.h
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@ -1,65 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
//
// Device Tree binding constants for Actions Semi S900 Reset Management Unit
//
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
#define __DT_BINDINGS_ACTIONS_S900_RESET_H
#define RESET_CHIPID 0
#define RESET_CPU_SCNT 1
#define RESET_SRAMI 2
#define RESET_DDR_CTL_PHY 3
#define RESET_DMAC 4
#define RESET_GPIO 5
#define RESET_BISP_AXI 6
#define RESET_CSI0 7
#define RESET_CSI1 8
#define RESET_DE 9
#define RESET_DSI 10
#define RESET_GPU3D_PA 11
#define RESET_GPU3D_PB 12
#define RESET_HDE 13
#define RESET_I2C0 14
#define RESET_I2C1 15
#define RESET_I2C2 16
#define RESET_I2C3 17
#define RESET_I2C4 18
#define RESET_I2C5 19
#define RESET_IMX 20
#define RESET_NANDC0 21
#define RESET_NANDC1 22
#define RESET_SD0 23
#define RESET_SD1 24
#define RESET_SD2 25
#define RESET_SD3 26
#define RESET_SPI0 27
#define RESET_SPI1 28
#define RESET_SPI2 29
#define RESET_SPI3 30
#define RESET_UART0 31
#define RESET_UART1 32
#define RESET_UART2 33
#define RESET_UART3 34
#define RESET_UART4 35
#define RESET_UART5 36
#define RESET_UART6 37
#define RESET_HDMI 38
#define RESET_LVDS 39
#define RESET_EDP 40
#define RESET_USB2HUB 41
#define RESET_USB2HSIC 42
#define RESET_USB3 43
#define RESET_PCM1 44
#define RESET_AUDIO 45
#define RESET_PCM0 46
#define RESET_SE 47
#define RESET_GIC 48
#define RESET_DDR_CTL_PHY_AXI 49
#define RESET_CMU_DDR 50
#define RESET_DMM 51
#define RESET_HDCP2TX 52
#define RESET_ETHERNET 53
#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */

13
include/dt-bindings/reset/raspberrypi,firmware-reset.h
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 Nicolas Saenz Julienne
* Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
*/
#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0
#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1
#endif

10
include/dt-bindings/reset/sama7g5-reset.h
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@ -1,10 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef __DT_BINDINGS_RESET_SAMA7G5_H
#define __DT_BINDINGS_RESET_SAMA7G5_H
#define SAMA7G5_RESET_USB_PHY1 4
#define SAMA7G5_RESET_USB_PHY2 5
#define SAMA7G5_RESET_USB_PHY3 6
#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */

17
include/dt-bindings/reset/snps,hsdk-reset.h
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@ -1,17 +0,0 @@
/**
* This header provides index for the HSDK reset controller.
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
#define HSDK_APB_RESET 0
#define HSDK_AXI_RESET 1
#define HSDK_ETH_RESET 2
#define HSDK_USB_RESET 3
#define HSDK_SDIO_RESET 4
#define HSDK_HDMI_RESET 5
#define HSDK_GFX_RESET 6
#define HSDK_DMAC_RESET 7
#define HSDK_EBI_RESET 8
#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/

79
include/dt-bindings/reset/sun20i-d1-ccu.h
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@ -1,79 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2020 huangzhenwei@allwinnertech.com
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
#define RST_MBUS 0
#define RST_BUS_DE 1
#define RST_BUS_DI 2
#define RST_BUS_G2D 3
#define RST_BUS_CE 4
#define RST_BUS_VE 5
#define RST_BUS_DMA 6
#define RST_BUS_MSGBOX0 7
#define RST_BUS_MSGBOX1 8
#define RST_BUS_MSGBOX2 9
#define RST_BUS_SPINLOCK 10
#define RST_BUS_HSTIMER 11
#define RST_BUS_DBG 12
#define RST_BUS_PWM 13
#define RST_BUS_DRAM 14
#define RST_BUS_MMC0 15
#define RST_BUS_MMC1 16
#define RST_BUS_MMC2 17
#define RST_BUS_UART0 18
#define RST_BUS_UART1 19
#define RST_BUS_UART2 20
#define RST_BUS_UART3 21
#define RST_BUS_UART4 22
#define RST_BUS_UART5 23
#define RST_BUS_I2C0 24
#define RST_BUS_I2C1 25
#define RST_BUS_I2C2 26
#define RST_BUS_I2C3 27
#define RST_BUS_SPI0 28
#define RST_BUS_SPI1 29
#define RST_BUS_EMAC 30
#define RST_BUS_IR_TX 31
#define RST_BUS_GPADC 32
#define RST_BUS_THS 33
#define RST_BUS_I2S0 34
#define RST_BUS_I2S1 35
#define RST_BUS_I2S2 36
#define RST_BUS_SPDIF 37
#define RST_BUS_DMIC 38
#define RST_BUS_AUDIO 39
#define RST_USB_PHY0 40
#define RST_USB_PHY1 41
#define RST_BUS_OHCI0 42
#define RST_BUS_OHCI1 43
#define RST_BUS_EHCI0 44
#define RST_BUS_EHCI1 45
#define RST_BUS_OTG 46
#define RST_BUS_LRADC 47
#define RST_BUS_DPSS_TOP 48
#define RST_BUS_HDMI_SUB 49
#define RST_BUS_HDMI_MAIN 50
#define RST_BUS_MIPI_DSI 51
#define RST_BUS_TCON_LCD0 52
#define RST_BUS_TCON_TV 53
#define RST_BUS_LVDS0 54
#define RST_BUS_TVE 55
#define RST_BUS_TVE_TOP 56
#define RST_BUS_TVD 57
#define RST_BUS_TVD_TOP 58
#define RST_BUS_LEDC 59
#define RST_BUS_CSI 60
#define RST_BUS_TPADC 61
#define RST_DSP 62
#define RST_BUS_DSP_CFG 63
#define RST_BUS_DSP_DBG 64
#define RST_BUS_RISCV_CFG 65
#define RST_BUS_CAN0 66
#define RST_BUS_CAN1 67
#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */

16
include/dt-bindings/reset/sun20i-d1-r-ccu.h
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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
#define RST_BUS_R_TIMER 0
#define RST_BUS_R_TWD 1
#define RST_BUS_R_PPU 2
#define RST_BUS_R_IR_RX 3
#define RST_BUS_R_RTC 4
#define RST_BUS_R_CPUCFG 5
#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */

69
include/dt-bindings/reset/sun4i-a10-ccu.h
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@ -1,69 +0,0 @@
/*
* Copyright (C) 2017 Priit Laes <plaes@plaes.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN4I_A10_H
#define _DT_BINDINGS_RST_SUN4I_A10_H
#define RST_USB_PHY0 1
#define RST_USB_PHY1 2
#define RST_USB_PHY2 3
#define RST_GPS 4
#define RST_DE_BE0 5
#define RST_DE_BE1 6
#define RST_DE_FE0 7
#define RST_DE_FE1 8
#define RST_DE_MP 9
#define RST_TVE0 10
#define RST_TCON0 11
#define RST_TVE1 12
#define RST_TCON1 13
#define RST_CSI0 14
#define RST_CSI1 15
#define RST_VE 16
#define RST_ACE 17
#define RST_LVDS 18
#define RST_GPU 19
#define RST_HDMI_H 20
#define RST_HDMI_SYS 21
#define RST_HDMI_AUDIO_DMA 22
#endif /* DT_BINDINGS_RST_SUN4I_A10_H */

98
include/dt-bindings/reset/sun50i-a64-ccu.h
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@ -1,98 +0,0 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
#define _DT_BINDINGS_RST_SUN50I_A64_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_DRAM 3
#define RST_MBUS 4
#define RST_BUS_MIPI_DSI 5
#define RST_BUS_CE 6
#define RST_BUS_DMA 7
#define RST_BUS_MMC0 8
#define RST_BUS_MMC1 9
#define RST_BUS_MMC2 10
#define RST_BUS_NAND 11
#define RST_BUS_DRAM 12
#define RST_BUS_EMAC 13
#define RST_BUS_TS 14
#define RST_BUS_HSTIMER 15
#define RST_BUS_SPI0 16
#define RST_BUS_SPI1 17
#define RST_BUS_OTG 18
#define RST_BUS_EHCI0 19
#define RST_BUS_EHCI1 20
#define RST_BUS_OHCI0 21
#define RST_BUS_OHCI1 22
#define RST_BUS_VE 23
#define RST_BUS_TCON0 24
#define RST_BUS_TCON1 25
#define RST_BUS_DEINTERLACE 26
#define RST_BUS_CSI 27
#define RST_BUS_HDMI0 28
#define RST_BUS_HDMI1 29
#define RST_BUS_DE 30
#define RST_BUS_GPU 31
#define RST_BUS_MSGBOX 32
#define RST_BUS_SPINLOCK 33
#define RST_BUS_DBG 34
#define RST_BUS_LVDS 35
#define RST_BUS_CODEC 36
#define RST_BUS_SPDIF 37
#define RST_BUS_THS 38
#define RST_BUS_I2S0 39
#define RST_BUS_I2S1 40
#define RST_BUS_I2S2 41
#define RST_BUS_I2C0 42
#define RST_BUS_I2C1 43
#define RST_BUS_I2C2 44
#define RST_BUS_SCR 45
#define RST_BUS_UART0 46
#define RST_BUS_UART1 47
#define RST_BUS_UART2 48
#define RST_BUS_UART3 49
#define RST_BUS_UART4 50
#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */

73
include/dt-bindings/reset/sun50i-h6-ccu.h
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@ -1,73 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
#define _DT_BINDINGS_RESET_SUN50I_H6_H_
#define RST_MBUS 0
#define RST_BUS_DE 1
#define RST_BUS_DEINTERLACE 2
#define RST_BUS_GPU 3
#define RST_BUS_CE 4
#define RST_BUS_VE 5
#define RST_BUS_EMCE 6
#define RST_BUS_VP9 7
#define RST_BUS_DMA 8
#define RST_BUS_MSGBOX 9
#define RST_BUS_SPINLOCK 10
#define RST_BUS_HSTIMER 11
#define RST_BUS_DBG 12
#define RST_BUS_PSI 13
#define RST_BUS_PWM 14
#define RST_BUS_IOMMU 15
#define RST_BUS_DRAM 16
#define RST_BUS_NAND 17
#define RST_BUS_MMC0 18
#define RST_BUS_MMC1 19
#define RST_BUS_MMC2 20
#define RST_BUS_UART0 21
#define RST_BUS_UART1 22
#define RST_BUS_UART2 23
#define RST_BUS_UART3 24
#define RST_BUS_I2C0 25
#define RST_BUS_I2C1 26
#define RST_BUS_I2C2 27
#define RST_BUS_I2C3 28
#define RST_BUS_SCR0 29
#define RST_BUS_SCR1 30
#define RST_BUS_SPI0 31
#define RST_BUS_SPI1 32
#define RST_BUS_EMAC 33
#define RST_BUS_TS 34
#define RST_BUS_IR_TX 35
#define RST_BUS_THS 36
#define RST_BUS_I2S0 37
#define RST_BUS_I2S1 38
#define RST_BUS_I2S2 39
#define RST_BUS_I2S3 40
#define RST_BUS_SPDIF 41
#define RST_BUS_DMIC 42
#define RST_BUS_AUDIO_HUB 43
#define RST_USB_PHY0 44
#define RST_USB_PHY1 45
#define RST_USB_PHY3 46
#define RST_USB_HSIC 47
#define RST_BUS_OHCI0 48
#define RST_BUS_OHCI3 49
#define RST_BUS_EHCI0 50
#define RST_BUS_XHCI 51
#define RST_BUS_EHCI3 52
#define RST_BUS_OTG 53
#define RST_BUS_PCIE 54
#define RST_PCIE_POWERUP 55
#define RST_BUS_HDMI 56
#define RST_BUS_HDMI_SUB 57
#define RST_BUS_TCON_TOP 58
#define RST_BUS_TCON_LCD0 59
#define RST_BUS_TCON_TV0 60
#define RST_BUS_CSI 61
#define RST_BUS_HDCP 62
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */

18
include/dt-bindings/reset/sun50i-h6-r-ccu.h
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@ -1,18 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*/
#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
#define RST_R_APB1_TIMER 0
#define RST_R_APB1_TWD 1
#define RST_R_APB1_PWM 2
#define RST_R_APB2_UART 3
#define RST_R_APB2_I2C 4
#define RST_R_APB1_IR 5
#define RST_R_APB1_W1 6
#define RST_R_APB2_RSB 7
#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */

23
include/dt-bindings/reset/sun5i-ccu.h
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@ -1,23 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*/
#ifndef _RST_SUN5I_H_
#define _RST_SUN5I_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_GPS 2
#define RST_DE_BE 3
#define RST_DE_FE 4
#define RST_TVE 5
#define RST_LCD 6
#define RST_CSI 7
#define RST_VE 8
#define RST_GPU 9
#define RST_IEP 10
#endif /* _RST_SUN5I_H_ */

106
include/dt-bindings/reset/sun6i-a31-ccu.h
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@ -1,106 +0,0 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_
#define _DT_BINDINGS_RST_SUN6I_A31_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_PHY2 2
#define RST_AHB1_MIPI_DSI 3
#define RST_AHB1_SS 4
#define RST_AHB1_DMA 5
#define RST_AHB1_MMC0 6
#define RST_AHB1_MMC1 7
#define RST_AHB1_MMC2 8
#define RST_AHB1_MMC3 9
#define RST_AHB1_NAND1 10
#define RST_AHB1_NAND0 11
#define RST_AHB1_SDRAM 12
#define RST_AHB1_EMAC 13
#define RST_AHB1_TS 14
#define RST_AHB1_HSTIMER 15
#define RST_AHB1_SPI0 16
#define RST_AHB1_SPI1 17
#define RST_AHB1_SPI2 18
#define RST_AHB1_SPI3 19
#define RST_AHB1_OTG 20
#define RST_AHB1_EHCI0 21
#define RST_AHB1_EHCI1 22
#define RST_AHB1_OHCI0 23
#define RST_AHB1_OHCI1 24
#define RST_AHB1_OHCI2 25
#define RST_AHB1_VE 26
#define RST_AHB1_LCD0 27
#define RST_AHB1_LCD1 28
#define RST_AHB1_CSI 29
#define RST_AHB1_HDMI 30
#define RST_AHB1_BE0 31
#define RST_AHB1_BE1 32
#define RST_AHB1_FE0 33
#define RST_AHB1_FE1 34
#define RST_AHB1_MP 35
#define RST_AHB1_GPU 36
#define RST_AHB1_DEU0 37
#define RST_AHB1_DEU1 38
#define RST_AHB1_DRC0 39
#define RST_AHB1_DRC1 40
#define RST_AHB1_LVDS 41
#define RST_APB1_CODEC 42
#define RST_APB1_SPDIF 43
#define RST_APB1_DIGITAL_MIC 44
#define RST_APB1_DAUDIO0 45
#define RST_APB1_DAUDIO1 46
#define RST_APB2_I2C0 47
#define RST_APB2_I2C1 48
#define RST_APB2_I2C2 49
#define RST_APB2_I2C3 50
#define RST_APB2_UART0 51
#define RST_APB2_UART1 52
#define RST_APB2_UART2 53
#define RST_APB2_UART3 54
#define RST_APB2_UART4 55
#define RST_APB2_UART5 56
#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */

87
include/dt-bindings/reset/sun8i-a23-a33-ccu.h
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@ -1,87 +0,0 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_
#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_MBUS 3
#define RST_BUS_MIPI_DSI 4
#define RST_BUS_SS 5
#define RST_BUS_DMA 6
#define RST_BUS_MMC0 7
#define RST_BUS_MMC1 8
#define RST_BUS_MMC2 9
#define RST_BUS_NAND 10
#define RST_BUS_DRAM 11
#define RST_BUS_HSTIMER 12
#define RST_BUS_SPI0 13
#define RST_BUS_SPI1 14
#define RST_BUS_OTG 15
#define RST_BUS_EHCI 16
#define RST_BUS_OHCI 17
#define RST_BUS_VE 18
#define RST_BUS_LCD 19
#define RST_BUS_CSI 20
#define RST_BUS_DE_BE 21
#define RST_BUS_DE_FE 22
#define RST_BUS_GPU 23
#define RST_BUS_MSGBOX 24
#define RST_BUS_SPINLOCK 25
#define RST_BUS_DRC 26
#define RST_BUS_SAT 27
#define RST_BUS_LVDS 28
#define RST_BUS_CODEC 29
#define RST_BUS_I2S0 30
#define RST_BUS_I2S1 31
#define RST_BUS_I2C0 32
#define RST_BUS_I2C1 33
#define RST_BUS_I2C2 34
#define RST_BUS_UART0 35
#define RST_BUS_UART1 36
#define RST_BUS_UART2 37
#define RST_BUS_UART3 38
#define RST_BUS_UART4 39
#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */

98
include/dt-bindings/reset/sun8i-a83t-ccu.h
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@ -1,98 +0,0 @@
/*
* Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_DRAM 3
#define RST_MBUS 4
#define RST_BUS_MIPI_DSI 5
#define RST_BUS_SS 6
#define RST_BUS_DMA 7
#define RST_BUS_MMC0 8
#define RST_BUS_MMC1 9
#define RST_BUS_MMC2 10
#define RST_BUS_NAND 11
#define RST_BUS_DRAM 12
#define RST_BUS_EMAC 13
#define RST_BUS_HSTIMER 14
#define RST_BUS_SPI0 15
#define RST_BUS_SPI1 16
#define RST_BUS_OTG 17
#define RST_BUS_EHCI0 18
#define RST_BUS_EHCI1 19
#define RST_BUS_OHCI0 20
#define RST_BUS_VE 21
#define RST_BUS_TCON0 22
#define RST_BUS_TCON1 23
#define RST_BUS_CSI 24
#define RST_BUS_HDMI0 25
#define RST_BUS_HDMI1 26
#define RST_BUS_DE 27
#define RST_BUS_GPU 28
#define RST_BUS_MSGBOX 29
#define RST_BUS_SPINLOCK 30
#define RST_BUS_LVDS 31
#define RST_BUS_SPDIF 32
#define RST_BUS_I2S0 33
#define RST_BUS_I2S1 34
#define RST_BUS_I2S2 35
#define RST_BUS_TDM 36
#define RST_BUS_I2C0 37
#define RST_BUS_I2C1 38
#define RST_BUS_I2C2 39
#define RST_BUS_UART0 40
#define RST_BUS_UART1 41
#define RST_BUS_UART2 42
#define RST_BUS_UART3 43
#define RST_BUS_UART4 44
#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */

15
include/dt-bindings/reset/sun8i-de2.h
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@ -1,15 +0,0 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
#define RST_MIXER0 0
#define RST_MIXER1 1
#define RST_WB 2
#define RST_ROT 3
#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */

106
include/dt-bindings/reset/sun8i-h3-ccu.h
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@ -1,106 +0,0 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_
#define _DT_BINDINGS_RST_SUN8I_H3_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_PHY2 2
#define RST_USB_PHY3 3
#define RST_MBUS 4
#define RST_BUS_CE 5
#define RST_BUS_DMA 6
#define RST_BUS_MMC0 7
#define RST_BUS_MMC1 8
#define RST_BUS_MMC2 9
#define RST_BUS_NAND 10
#define RST_BUS_DRAM 11
#define RST_BUS_EMAC 12
#define RST_BUS_TS 13
#define RST_BUS_HSTIMER 14
#define RST_BUS_SPI0 15
#define RST_BUS_SPI1 16
#define RST_BUS_OTG 17
#define RST_BUS_EHCI0 18
#define RST_BUS_EHCI1 19
#define RST_BUS_EHCI2 20
#define RST_BUS_EHCI3 21
#define RST_BUS_OHCI0 22
#define RST_BUS_OHCI1 23
#define RST_BUS_OHCI2 24
#define RST_BUS_OHCI3 25
#define RST_BUS_VE 26
#define RST_BUS_TCON0 27
#define RST_BUS_TCON1 28
#define RST_BUS_DEINTERLACE 29
#define RST_BUS_CSI 30
#define RST_BUS_TVE 31
#define RST_BUS_HDMI0 32
#define RST_BUS_HDMI1 33
#define RST_BUS_DE 34
#define RST_BUS_GPU 35
#define RST_BUS_MSGBOX 36
#define RST_BUS_SPINLOCK 37
#define RST_BUS_DBG 38
#define RST_BUS_EPHY 39
#define RST_BUS_CODEC 40
#define RST_BUS_SPDIF 41
#define RST_BUS_THS 42
#define RST_BUS_I2S0 43
#define RST_BUS_I2S1 44
#define RST_BUS_I2S2 45
#define RST_BUS_I2C0 46
#define RST_BUS_I2C1 47
#define RST_BUS_I2C2 48
#define RST_BUS_UART0 49
#define RST_BUS_UART1 50
#define RST_BUS_UART2 51
#define RST_BUS_UART3 52
#define RST_BUS_SCR0 53
/* New resets imported in H5 */
#define RST_BUS_SCR1 54
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */

53
include/dt-bindings/reset/sun8i-r-ccu.h
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@ -1,53 +0,0 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
#define RST_APB0_IR 0
#define RST_APB0_TIMER 1
#define RST_APB0_RSB 2
#define RST_APB0_UART 3
/* 4 is reserved for RST_APB0_W1 on A31 */
#define RST_APB0_I2C 5
#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */

130
include/dt-bindings/reset/sun8i-r40-ccu.h
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@ -1,130 +0,0 @@
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
#define _DT_BINDINGS_RST_SUN8I_R40_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_PHY2 2
#define RST_DRAM 3
#define RST_MBUS 4
#define RST_BUS_MIPI_DSI 5
#define RST_BUS_CE 6
#define RST_BUS_DMA 7
#define RST_BUS_MMC0 8
#define RST_BUS_MMC1 9
#define RST_BUS_MMC2 10
#define RST_BUS_MMC3 11
#define RST_BUS_NAND 12
#define RST_BUS_DRAM 13
#define RST_BUS_EMAC 14
#define RST_BUS_TS 15
#define RST_BUS_HSTIMER 16
#define RST_BUS_SPI0 17
#define RST_BUS_SPI1 18
#define RST_BUS_SPI2 19
#define RST_BUS_SPI3 20
#define RST_BUS_SATA 21
#define RST_BUS_OTG 22
#define RST_BUS_EHCI0 23
#define RST_BUS_EHCI1 24
#define RST_BUS_EHCI2 25
#define RST_BUS_OHCI0 26
#define RST_BUS_OHCI1 27
#define RST_BUS_OHCI2 28
#define RST_BUS_VE 29
#define RST_BUS_MP 30
#define RST_BUS_DEINTERLACE 31
#define RST_BUS_CSI0 32
#define RST_BUS_CSI1 33
#define RST_BUS_HDMI0 34
#define RST_BUS_HDMI1 35
#define RST_BUS_DE 36
#define RST_BUS_TVE0 37
#define RST_BUS_TVE1 38
#define RST_BUS_TVE_TOP 39
#define RST_BUS_GMAC 40
#define RST_BUS_GPU 41
#define RST_BUS_TVD0 42
#define RST_BUS_TVD1 43
#define RST_BUS_TVD2 44
#define RST_BUS_TVD3 45
#define RST_BUS_TVD_TOP 46
#define RST_BUS_TCON_LCD0 47
#define RST_BUS_TCON_LCD1 48
#define RST_BUS_TCON_TV0 49
#define RST_BUS_TCON_TV1 50
#define RST_BUS_TCON_TOP 51
#define RST_BUS_DBG 52
#define RST_BUS_LVDS 53
#define RST_BUS_CODEC 54
#define RST_BUS_SPDIF 55
#define RST_BUS_AC97 56
#define RST_BUS_IR0 57
#define RST_BUS_IR1 58
#define RST_BUS_THS 59
#define RST_BUS_KEYPAD 60
#define RST_BUS_I2S0 61
#define RST_BUS_I2S1 62
#define RST_BUS_I2S2 63
#define RST_BUS_I2C0 64
#define RST_BUS_I2C1 65
#define RST_BUS_I2C2 66
#define RST_BUS_I2C3 67
#define RST_BUS_CAN 68
#define RST_BUS_SCR 69
#define RST_BUS_PS20 70
#define RST_BUS_PS21 71
#define RST_BUS_I2C4 72
#define RST_BUS_UART0 73
#define RST_BUS_UART1 74
#define RST_BUS_UART2 75
#define RST_BUS_UART3 76
#define RST_BUS_UART4 77
#define RST_BUS_UART5 78
#define RST_BUS_UART6 79
#define RST_BUS_UART7 80
#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */

81
include/dt-bindings/reset/sun8i-v3s-ccu.h
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/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on sun8i-v3s-ccu.h, which is
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_
#define _DT_BINDINGS_RST_SUN8I_V3S_H_
#define RST_USB_PHY0 0
#define RST_MBUS 1
#define RST_BUS_CE 5
#define RST_BUS_DMA 6
#define RST_BUS_MMC0 7
#define RST_BUS_MMC1 8
#define RST_BUS_MMC2 9
#define RST_BUS_DRAM 11
#define RST_BUS_EMAC 12
#define RST_BUS_HSTIMER 14
#define RST_BUS_SPI0 15
#define RST_BUS_OTG 17
#define RST_BUS_EHCI0 18
#define RST_BUS_OHCI0 22
#define RST_BUS_VE 26
#define RST_BUS_TCON0 27
#define RST_BUS_CSI 30
#define RST_BUS_DE 34
#define RST_BUS_DBG 38
#define RST_BUS_EPHY 39
#define RST_BUS_CODEC 40
#define RST_BUS_I2C0 46
#define RST_BUS_I2C1 47
#define RST_BUS_UART0 49
#define RST_BUS_UART1 50
#define RST_BUS_UART2 51
/* Reset lines not available on V3s */
#define RST_BUS_I2S0 52
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */

102
include/dt-bindings/reset/sun9i-a80-ccu.h
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@ -1,102 +0,0 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_
#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_
#define RST_BUS_FD 0
#define RST_BUS_VE 1
#define RST_BUS_GPU_CTRL 2
#define RST_BUS_SS 3
#define RST_BUS_MMC 4
#define RST_BUS_NAND0 5
#define RST_BUS_NAND1 6
#define RST_BUS_SDRAM 7
#define RST_BUS_SATA 8
#define RST_BUS_TS 9
#define RST_BUS_SPI0 10
#define RST_BUS_SPI1 11
#define RST_BUS_SPI2 12
#define RST_BUS_SPI3 13
#define RST_BUS_OTG 14
#define RST_BUS_OTG_PHY 15
#define RST_BUS_MIPI_HSI 16
#define RST_BUS_GMAC 17
#define RST_BUS_MSGBOX 18
#define RST_BUS_SPINLOCK 19
#define RST_BUS_HSTIMER 20
#define RST_BUS_DMA 21
#define RST_BUS_LCD0 22
#define RST_BUS_LCD1 23
#define RST_BUS_EDP 24
#define RST_BUS_LVDS 25
#define RST_BUS_CSI 26
#define RST_BUS_HDMI0 27
#define RST_BUS_HDMI1 28
#define RST_BUS_DE 29
#define RST_BUS_MP 30
#define RST_BUS_GPU 31
#define RST_BUS_MIPI_DSI 32
#define RST_BUS_SPDIF 33
#define RST_BUS_AC97 34
#define RST_BUS_I2S0 35
#define RST_BUS_I2S1 36
#define RST_BUS_LRADC 37
#define RST_BUS_GPADC 38
#define RST_BUS_CIR_TX 39
#define RST_BUS_I2C0 40
#define RST_BUS_I2C1 41
#define RST_BUS_I2C2 42
#define RST_BUS_I2C3 43
#define RST_BUS_I2C4 44
#define RST_BUS_UART0 45
#define RST_BUS_UART1 46
#define RST_BUS_UART2 47
#define RST_BUS_UART3 48
#define RST_BUS_UART4 49
#define RST_BUS_UART5 50
#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */

58
include/dt-bindings/reset/sun9i-a80-de.h
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@ -1,58 +0,0 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
#define RST_FE0 0
#define RST_FE1 1
#define RST_FE2 2
#define RST_DEU0 3
#define RST_DEU1 4
#define RST_BE0 5
#define RST_BE1 6
#define RST_BE2 7
#define RST_DRC0 8
#define RST_DRC1 9
#define RST_MERGE 10
#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */

56
include/dt-bindings/reset/sun9i-a80-usb.h
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@ -1,56 +0,0 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_
#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_
#define RST_USB0_HCI 0
#define RST_USB1_HCI 1
#define RST_USB2_HCI 2
#define RST_USB0_PHY 3
#define RST_USB1_HSIC 4
#define RST_USB1_PHY 5
#define RST_USB2_HSIC 6
#define RST_USB2_PHY 7
#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */

38
include/dt-bindings/reset/suniv-ccu-f1c100s.h
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@ -1,38 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*
* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
*
*/
#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
#define RST_USB_PHY0 0
#define RST_BUS_DMA 1
#define RST_BUS_MMC0 2
#define RST_BUS_MMC1 3
#define RST_BUS_DRAM 4
#define RST_BUS_SPI0 5
#define RST_BUS_SPI1 6
#define RST_BUS_OTG 7
#define RST_BUS_VE 8
#define RST_BUS_LCD 9
#define RST_BUS_DEINTERLACE 10
#define RST_BUS_CSI 11
#define RST_BUS_TVD 12
#define RST_BUS_TVE 13
#define RST_BUS_DE_BE 14
#define RST_BUS_DE_FE 15
#define RST_BUS_CODEC 16
#define RST_BUS_SPDIF 17
#define RST_BUS_IR 18
#define RST_BUS_RSB 19
#define RST_BUS_I2S0 20
#define RST_BUS_I2C0 21
#define RST_BUS_I2C1 22
#define RST_BUS_I2C2 23
#define RST_BUS_UART0 24
#define RST_BUS_UART1 25
#define RST_BUS_UART2 26
#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */

130
include/dt-bindings/reset/xlnx-zynqmp-resets.h
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@ -1,130 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
#define _DT_BINDINGS_ZYNQMP_RESETS_H
#define ZYNQMP_RESET_PCIE_CFG 0
#define ZYNQMP_RESET_PCIE_BRIDGE 1
#define ZYNQMP_RESET_PCIE_CTRL 2
#define ZYNQMP_RESET_DP 3
#define ZYNQMP_RESET_SWDT_CRF 4
#define ZYNQMP_RESET_AFI_FM5 5
#define ZYNQMP_RESET_AFI_FM4 6
#define ZYNQMP_RESET_AFI_FM3 7
#define ZYNQMP_RESET_AFI_FM2 8
#define ZYNQMP_RESET_AFI_FM1 9
#define ZYNQMP_RESET_AFI_FM0 10
#define ZYNQMP_RESET_GDMA 11
#define ZYNQMP_RESET_GPU_PP1 12
#define ZYNQMP_RESET_GPU_PP0 13
#define ZYNQMP_RESET_GPU 14
#define ZYNQMP_RESET_GT 15
#define ZYNQMP_RESET_SATA 16
#define ZYNQMP_RESET_ACPU3_PWRON 17
#define ZYNQMP_RESET_ACPU2_PWRON 18
#define ZYNQMP_RESET_ACPU1_PWRON 19
#define ZYNQMP_RESET_ACPU0_PWRON 20
#define ZYNQMP_RESET_APU_L2 21
#define ZYNQMP_RESET_ACPU3 22
#define ZYNQMP_RESET_ACPU2 23
#define ZYNQMP_RESET_ACPU1 24
#define ZYNQMP_RESET_ACPU0 25
#define ZYNQMP_RESET_DDR 26
#define ZYNQMP_RESET_APM_FPD 27
#define ZYNQMP_RESET_SOFT 28
#define ZYNQMP_RESET_GEM0 29
#define ZYNQMP_RESET_GEM1 30
#define ZYNQMP_RESET_GEM2 31
#define ZYNQMP_RESET_GEM3 32
#define ZYNQMP_RESET_QSPI 33
#define ZYNQMP_RESET_UART0 34
#define ZYNQMP_RESET_UART1 35
#define ZYNQMP_RESET_SPI0 36
#define ZYNQMP_RESET_SPI1 37
#define ZYNQMP_RESET_SDIO0 38
#define ZYNQMP_RESET_SDIO1 39
#define ZYNQMP_RESET_CAN0 40
#define ZYNQMP_RESET_CAN1 41
#define ZYNQMP_RESET_I2C0 42
#define ZYNQMP_RESET_I2C1 43
#define ZYNQMP_RESET_TTC0 44
#define ZYNQMP_RESET_TTC1 45
#define ZYNQMP_RESET_TTC2 46
#define ZYNQMP_RESET_TTC3 47
#define ZYNQMP_RESET_SWDT_CRL 48
#define ZYNQMP_RESET_NAND 49
#define ZYNQMP_RESET_ADMA 50
#define ZYNQMP_RESET_GPIO 51
#define ZYNQMP_RESET_IOU_CC 52
#define ZYNQMP_RESET_TIMESTAMP 53
#define ZYNQMP_RESET_RPU_R50 54
#define ZYNQMP_RESET_RPU_R51 55
#define ZYNQMP_RESET_RPU_AMBA 56
#define ZYNQMP_RESET_OCM 57
#define ZYNQMP_RESET_RPU_PGE 58
#define ZYNQMP_RESET_USB0_CORERESET 59
#define ZYNQMP_RESET_USB1_CORERESET 60
#define ZYNQMP_RESET_USB0_HIBERRESET 61
#define ZYNQMP_RESET_USB1_HIBERRESET 62
#define ZYNQMP_RESET_USB0_APB 63
#define ZYNQMP_RESET_USB1_APB 64
#define ZYNQMP_RESET_IPI 65
#define ZYNQMP_RESET_APM_LPD 66
#define ZYNQMP_RESET_RTC 67
#define ZYNQMP_RESET_SYSMON 68
#define ZYNQMP_RESET_AFI_FM6 69
#define ZYNQMP_RESET_LPD_SWDT 70
#define ZYNQMP_RESET_FPD 71
#define ZYNQMP_RESET_RPU_DBG1 72
#define ZYNQMP_RESET_RPU_DBG0 73
#define ZYNQMP_RESET_DBG_LPD 74
#define ZYNQMP_RESET_DBG_FPD 75
#define ZYNQMP_RESET_APLL 76
#define ZYNQMP_RESET_DPLL 77
#define ZYNQMP_RESET_VPLL 78
#define ZYNQMP_RESET_IOPLL 79
#define ZYNQMP_RESET_RPLL 80
#define ZYNQMP_RESET_GPO3_PL_0 81
#define ZYNQMP_RESET_GPO3_PL_1 82
#define ZYNQMP_RESET_GPO3_PL_2 83
#define ZYNQMP_RESET_GPO3_PL_3 84
#define ZYNQMP_RESET_GPO3_PL_4 85
#define ZYNQMP_RESET_GPO3_PL_5 86
#define ZYNQMP_RESET_GPO3_PL_6 87
#define ZYNQMP_RESET_GPO3_PL_7 88
#define ZYNQMP_RESET_GPO3_PL_8 89
#define ZYNQMP_RESET_GPO3_PL_9 90
#define ZYNQMP_RESET_GPO3_PL_10 91
#define ZYNQMP_RESET_GPO3_PL_11 92
#define ZYNQMP_RESET_GPO3_PL_12 93
#define ZYNQMP_RESET_GPO3_PL_13 94
#define ZYNQMP_RESET_GPO3_PL_14 95
#define ZYNQMP_RESET_GPO3_PL_15 96
#define ZYNQMP_RESET_GPO3_PL_16 97
#define ZYNQMP_RESET_GPO3_PL_17 98
#define ZYNQMP_RESET_GPO3_PL_18 99
#define ZYNQMP_RESET_GPO3_PL_19 100
#define ZYNQMP_RESET_GPO3_PL_20 101
#define ZYNQMP_RESET_GPO3_PL_21 102
#define ZYNQMP_RESET_GPO3_PL_22 103
#define ZYNQMP_RESET_GPO3_PL_23 104
#define ZYNQMP_RESET_GPO3_PL_24 105
#define ZYNQMP_RESET_GPO3_PL_25 106
#define ZYNQMP_RESET_GPO3_PL_26 107
#define ZYNQMP_RESET_GPO3_PL_27 108
#define ZYNQMP_RESET_GPO3_PL_28 109
#define ZYNQMP_RESET_GPO3_PL_29 110
#define ZYNQMP_RESET_GPO3_PL_30 111
#define ZYNQMP_RESET_GPO3_PL_31 112
#define ZYNQMP_RESET_RPU_LS 113
#define ZYNQMP_RESET_PS_ONLY 114
#define ZYNQMP_RESET_PL 115
#define ZYNQMP_RESET_PS_PL0 116
#define ZYNQMP_RESET_PS_PL1 117
#define ZYNQMP_RESET_PS_PL2 118
#define ZYNQMP_RESET_PS_PL3 119
#endif

28
include/dt-bindings/soc/bcm2835-pm.h
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@ -1,28 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H
#define _DT_BINDINGS_ARM_BCM2835_PM_H
#define BCM2835_POWER_DOMAIN_GRAFX 0
#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1
#define BCM2835_POWER_DOMAIN_IMAGE 2
#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3
#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4
#define BCM2835_POWER_DOMAIN_IMAGE_H264 5
#define BCM2835_POWER_DOMAIN_USB 6
#define BCM2835_POWER_DOMAIN_DSI0 7
#define BCM2835_POWER_DOMAIN_DSI1 8
#define BCM2835_POWER_DOMAIN_CAM0 9
#define BCM2835_POWER_DOMAIN_CAM1 10
#define BCM2835_POWER_DOMAIN_CCP2TX 11
#define BCM2835_POWER_DOMAIN_HDMI 12
#define BCM2835_POWER_DOMAIN_COUNT 13
#define BCM2835_RESET_V3D 0
#define BCM2835_RESET_ISP 1
#define BCM2835_RESET_H264 2
#define BCM2835_RESET_COUNT 3
#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */

9
include/dt-bindings/soc/ti,sci_pm_domain.h
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
#define TI_SCI_PD_EXCLUSIVE 1
#define TI_SCI_PD_SHARED 0
#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */

9
include/dt-bindings/sound/apq8016-lpass.h
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_APQ8016_LPASS_H
#define __DT_APQ8016_LPASS_H
#include <dt-bindings/sound/qcom,lpass.h>
/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */
#endif /* __DT_APQ8016_LPASS_H */

13
include/dt-bindings/sound/microchip,pdmc.h
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_MICROCHIP_PDMC_H__
#define __DT_BINDINGS_MICROCHIP_PDMC_H__
/* PDM microphone's pin placement */
#define MCHP_PDMC_DS0 0
#define MCHP_PDMC_DS1 1
/* PDM microphone clock edge sampling */
#define MCHP_PDMC_CLK_POSITIVE 0
#define MCHP_PDMC_CLK_NEGATIVE 1
#endif /* __DT_BINDINGS_MICROCHIP_PDMC_H__ */