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arm: Remove mx31pdk board
DM, OF_CONTROL, DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Acked-by: Magnus Lilja <lilja.magnus@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
parent
5d1281296f
commit
f247354708
@ -29,6 +29,5 @@ config MX31_CLK32
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Frequency in Hz of the low frequency input clock. Typically
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Frequency in Hz of the low frequency input clock. Typically
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32768 or 32000 Hz.
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32768 or 32000 Hz.
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source "board/freescale/mx31pdk/Kconfig"
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endif
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endif
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@ -1,15 +0,0 @@
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if TARGET_MX31PDK
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config SYS_BOARD
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default "mx31pdk"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "mx31"
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config SYS_CONFIG_NAME
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default "mx31pdk"
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endif
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@ -1,6 +0,0 @@
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MX31PDK BOARD
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M: Magnus Lilja <lilja.magnus@gmail.com>
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S: Maintained
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F: board/freescale/mx31pdk/
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F: include/configs/mx31pdk.h
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F: configs/mx31pdk_defconfig
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@ -1,11 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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ifdef CONFIG_SPL_BUILD
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obj-y += lowlevel_init.o
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endif
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obj-y += mx31pdk.o
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@ -1,76 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/macro.h>
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.globl lowlevel_init
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lowlevel_init:
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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write32 IPU_CONF, IPU_CONF_DI_EN
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write32 CCM_CCMR, CCM_CCMR_SETUP
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wait_timer 0x40000
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write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
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write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
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/* Set up clock to 532MHz */
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write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
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write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
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write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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/* Set up MX31 DDR pins */
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write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
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write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
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write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
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write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
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write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
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write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
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write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
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write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
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write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
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write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
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write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
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write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
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write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
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write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
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write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
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write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
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write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
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write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
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write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
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write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
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write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
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write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
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write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
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write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
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write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
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write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
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write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
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/* Set up MX31 DDR Memory Controller */
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write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
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write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
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/* Perform DDR init sequence */
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write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
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write32 CSD0_BASE | 0x0f00, 0x12344321
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write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
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write32 CSD0_BASE, 0x12344321
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write32 CSD0_BASE, 0x12344321
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write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
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write8 CSD0_BASE | 0x00000033, 0xda
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write8 CSD0_BASE | 0x01000000, 0xff
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write32 WEIM_ESDCTL0, ESDCTL_RW
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write32 CSD0_BASE, 0xDEADBEEF
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write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
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mov pc, lr
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@ -1,119 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*/
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#include <common.h>
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#include <init.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <watchdog.h>
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#include <power/pmic.h>
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#include <fsl_pmic.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong bootflag)
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{
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/*
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* copy ourselves from where we are running to where we were
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* linked at. Use ulong pointers as all addresses involved
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* are 4-byte-aligned.
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*/
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ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
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asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
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asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
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asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
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asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
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for (dst = start_ptr; dst < end_ptr; dst++)
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*dst = *(dst+(run_ptr-link_ptr));
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/*
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* branch to nand_boot's link-time address.
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*/
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asm volatile("ldr pc, =nand_boot");
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}
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int board_early_init_f(void)
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{
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/* CS5: CPLD incl. network controller */
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static const struct mxc_weimcs cs5 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(5, &cs5);
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/* Setup UART1 and SPI2 pins */
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mx31_uart1_hw_init();
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mx31_spi2_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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u32 val;
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struct pmic *p;
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int ret;
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ret = pmic_init(CONFIG_FSL_PMIC_BUS);
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if (ret)
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return ret;
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p = pmic_get("FSL_PMIC");
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if (!p)
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return -ENODEV;
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/* Enable RTC battery */
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pmic_reg_read(p, REG_POWER_CTL0, &val);
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pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
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pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
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#ifdef CONFIG_HW_WATCHDOG
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hw_watchdog_init();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: MX31PDK\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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@ -1,40 +0,0 @@
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CONFIG_ARM=y
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# CONFIG_SPL_USE_ARCH_MEMCPY is not set
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# CONFIG_SPL_USE_ARCH_MEMSET is not set
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CONFIG_ARCH_MX31=y
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CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
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CONFIG_SYS_TEXT_BASE=0x87e00000
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_OFFSET=0x40000
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CONFIG_TARGET_MX31PDK=y
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CONFIG_SPL_TEXT_BASE=0x87dc0000
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL=y
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CONFIG_ENV_OFFSET_REDUND=0x60000
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# CONFIG_SPL_FRAMEWORK is not set
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CONFIG_SPL_NAND_SUPPORT=y
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# CONFIG_AUTO_COMPLETE is not set
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_SPI=y
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CONFIG_DEFAULT_SPI_BUS=1
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CONFIG_DEFAULT_SPI_MODE=4
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_DATE=y
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CONFIG_ENV_IS_IN_NAND=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_MXC_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXC=y
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CONFIG_SMC911X=y
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CONFIG_SMC911X_BASE=0xB6000000
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CONFIG_SMC911X_32_BIT=y
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CONFIG_SPI=y
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CONFIG_MXC_SPI=y
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@ -1,141 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the Freescale i.MX31 PDK board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_MAX_SIZE 2048
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/* PMIC Controller */
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#define CONFIG_POWER
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#define CONFIG_POWER_SPI
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#define CONFIG_POWER_FSL
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 2
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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#define CONFIG_RTC_MC13XXX
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
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"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
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"tftpboot 0x81000000 uImage-mx31; bootm\0" \
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"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
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"nand erase 0x0 0x40000; " \
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"nand write 0x81000000 0x0 0x40000\0"
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||||||
|
|
||||||
/*
|
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||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* memtest works on */
|
|
||||||
|
|
||||||
/* default load address */
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x81000000
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Physical Memory Map
|
|
||||||
*/
|
|
||||||
#define PHYS_SDRAM_1 CSD0_BASE
|
|
||||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
|
||||||
GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
|
||||||
CONFIG_SYS_INIT_RAM_SIZE)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* environment organization
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NAND driver
|
|
||||||
*/
|
|
||||||
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
|
|
||||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
||||||
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
|
|
||||||
#define CONFIG_MXC_NAND_HWECC
|
|
||||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
|
||||||
|
|
||||||
/* NAND configuration for the NAND_SPL */
|
|
||||||
|
|
||||||
/* Start copying real U-Boot from the second page */
|
|
||||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
|
||||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
|
|
||||||
/* Load U-Boot to this address */
|
|
||||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
|
||||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
|
|
||||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
|
||||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
|
||||||
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
|
|
||||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
|
||||||
|
|
||||||
/* Configuration of lowlevel_init.S (clocks and SDRAM) */
|
|
||||||
#define CCM_CCMR_SETUP 0x074B0BF5
|
|
||||||
#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
|
|
||||||
PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
|
|
||||||
PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
|
|
||||||
PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
|
|
||||||
#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
|
|
||||||
PLL_MFN(12))
|
|
||||||
|
|
||||||
#define ESDMISC_MDDR_SETUP 0x00000004
|
|
||||||
#define ESDMISC_MDDR_RESET_DL 0x0000000c
|
|
||||||
#define ESDCFG0_MDDR_SETUP 0x006ac73a
|
|
||||||
|
|
||||||
#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
|
|
||||||
#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
|
|
||||||
ESDCTL_DSIZ(2) | ESDCTL_BL(1))
|
|
||||||
#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
|
|
||||||
#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
|
|
||||||
#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
|
|
||||||
#define ESDCTL_RW ESDCTL_SETTINGS
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
Loading…
Reference in New Issue
Block a user