From f1b077c512b566a3a7bf1cf89ecb1ff49791ebd1 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 6 Apr 2026 15:37:09 -0500 Subject: [PATCH] arm: dts: mediatek: add Genio 520/720 SNOR support Add devicetree nodes needed to enable SNOR support on Genio 520 and 720 EVKs. This is copied from the most recent upstream submission [1] of the devicetree for these boards, so there should be minimal differences when we eventually switch to OF_UPSTREAM. Link: https://lore.kernel.org/linux-mediatek/20251111070031.305281-10-jh.hsu@mediatek.com/ [1] Link: https://patch.msgid.link/20260406-mtk-genio-720-snor-v1-1-cbfd5fc4e59a@baylibre.com Signed-off-by: David Lechner --- arch/arm/dts/mt8189.dtsi | 17 +++++++++++++++ arch/arm/dts/mt8371-genio-common.dtsi | 31 +++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi index e550745ac5d..891d3249ecd 100644 --- a/arch/arm/dts/mt8189.dtsi +++ b/arch/arm/dts/mt8189.dtsi @@ -181,6 +181,23 @@ status = "disabled"; }; + nor_flash: spi@11018000 { + compatible = "mediatek,mt8189-nor","mediatek,mt8186-nor"; + reg = <0 0x11018000 0 0x1000>; + clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>, + <&pericfg_ao_clk CLK_PERAO_SFLASH>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_F>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_H>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_P>; + clock-names = "spi", "sf", "axi_f", "axi_h", "axi_p"; + assigned-clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D8>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + xhci0: usb@11200000 { compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x1000>, diff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi index 046e9d57752..1d4728e3732 100644 --- a/arch/arm/dts/mt8371-genio-common.dtsi +++ b/arch/arm/dts/mt8371-genio-common.dtsi @@ -162,6 +162,21 @@ regulator-always-on; }; +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &pio { mmc0_default_pins: mmc0-default-pins { pins-clk { @@ -274,6 +289,22 @@ }; }; + nor_pins: nor-pins { + pins-ck-io { + pinmux = , + , + ; + drive-strength = <8>; + bias-pull-down; + }; + + pins-cs { + pinmux = ; + drive-strength = <8>; + bias-pull-up; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = ,