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mtd: rawnand: sunxi: add support for H6/H616 nand controller
Introduce H6/H616 NAND controller support for U-Boot The H616 NAND controller has the same base as A10/A23, with some differences: - MDMA is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. Introduce the basic support, with ECC and scrambling, but without DMA/MDMA. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
This commit is contained in:
Richard Genoud
Michael Trimarchi
parent
4a611a82e5
commit
f163da5e6d
@ -472,7 +472,8 @@ config NAND_SANDBOX
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config NAND_SUNXI
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bool "Support for NAND on Allwinner SoCs"
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default ARCH_SUNXI
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depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
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depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I \
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|| MACH_SUN50I_H616 || MACH_SUN50I_H6
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select SYS_NAND_SELF_INIT
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select SYS_NAND_U_BOOT_LOCATIONS
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select SPL_NAND_SUPPORT
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@ -187,6 +187,14 @@ static void sunxi_nfc_set_clk_rate(unsigned long hz)
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CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
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ccm + CCU_NAND0_CLK_CFG);
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#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_H6)
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setbits_le32(ccm + CCU_H6_NAND_GATE_RESET,
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(1 << GATE_SHIFT) | (1 << RESET_SHIFT));
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setbits_le32(ccm + CCU_H6_MBUS_GATE, (1 << MBUS_GATE_OFFSET_NAND));
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writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
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CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
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ccm + CCU_NAND1_CLK_CFG);
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#else
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/* gate on nand clock */
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setbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_NAND0));
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#ifdef CONFIG_MACH_SUN9I
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@ -194,6 +202,7 @@ static void sunxi_nfc_set_clk_rate(unsigned long hz)
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#else
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setbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_DMA));
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#endif
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#endif
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}
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static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
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@ -688,6 +697,53 @@ static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
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buf[3] = user_data >> 24;
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}
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/*
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* On H6/H616 the user_data length has to be set in specific registers
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* before writing.
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*/
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static void sunxi_nfc_reset_user_data_len(struct sunxi_nfc *nfc)
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{
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int loop_step = NFC_REG_USER_DATA_LEN_CAPACITY;
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/* not all SoCs have this register */
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if (!nfc->caps->reg_user_data_len)
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return;
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for (int i = 0; i < nfc->caps->max_ecc_steps; i += loop_step)
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writel(0, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, i));
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}
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static void sunxi_nfc_set_user_data_len(struct sunxi_nfc *nfc,
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int len, int step)
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{
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bool found = false;
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u32 val;
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int i;
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/* not all SoCs have this register */
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if (!nfc->caps->reg_user_data_len)
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return;
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for (i = 0; i < nfc->caps->nuser_data_tab; i++) {
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if (len == nfc->caps->user_data_len_tab[i]) {
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found = true;
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break;
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}
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}
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if (!found) {
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dev_warn(nfc->dev,
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"Unsupported length for user data reg: %d\n", len);
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return;
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}
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val = readl(nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step));
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val &= ~NFC_USER_DATA_LEN_MSK(step);
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val |= field_prep(NFC_USER_DATA_LEN_MSK(step), i);
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writel(val, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step));
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}
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static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
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u8 *data, int data_off,
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u8 *oob, int oob_off,
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@ -715,6 +771,9 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
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if (ret)
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return ret;
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sunxi_nfc_reset_user_data_len(nfc);
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sunxi_nfc_set_user_data_len(nfc, 4, 0);
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sunxi_nfc_randomizer_enable(mtd);
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writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
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nfc->regs + NFC_REG_CMD);
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@ -855,6 +914,9 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
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if (ret)
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return ret;
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sunxi_nfc_reset_user_data_len(nfc);
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sunxi_nfc_set_user_data_len(nfc, 4, 0);
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sunxi_nfc_randomizer_enable(mtd);
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writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
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NFC_ACCESS_DIR | NFC_ECC_OP,
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@ -1275,7 +1337,6 @@ static int sunxi_nand_chip_init_timings(struct sunxi_nfc *nfc,
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static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
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struct nand_ecc_ctrl *ecc)
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{
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static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
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struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
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@ -1302,12 +1363,12 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
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/* Add ECC info retrieval from DT */
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for (i = 0; i < nfc->caps->nstrengths; i++) {
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if (ecc->strength <= strengths[i]) {
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if (ecc->strength <= nfc->caps->ecc_strengths[i]) {
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/*
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* Update ecc->strength value with the actual strength
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* that will be used by the ECC engine.
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*/
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ecc->strength = strengths[i];
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ecc->strength = nfc->caps->ecc_strengths[i];
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break;
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}
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}
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@ -1721,9 +1782,22 @@ static int sunxi_nand_probe(struct udevice *dev)
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return 0;
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}
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static const u8 sunxi_ecc_strengths_a10[] = {
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16, 24, 28, 32, 40, 48, 56, 60, 64
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};
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static const u8 sunxi_ecc_strengths_h6[] = {
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16, 24, 28, 32, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80
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};
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static const u8 sunxi_user_data_len_h6[] = {
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0, 4, 8, 12, 16, 20, 24, 28, 32
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};
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static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
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.has_ecc_block_512 = true,
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.nstrengths = 9,
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.nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_a10),
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.ecc_strengths = sunxi_ecc_strengths_a10,
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.reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT,
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.reg_user_data = NFC_REG_A10_USER_DATA,
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.reg_pat_found = NFC_REG_ECC_ST,
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@ -1732,6 +1806,24 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
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.pat_found_mask = GENMASK(31, 16),
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.ecc_mode_mask = GENMASK(15, 12),
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.random_en_mask = BIT(9),
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.max_ecc_steps = 16,
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};
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static const struct sunxi_nfc_caps sunxi_nfc_h616_caps = {
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.nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_h6),
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.ecc_strengths = sunxi_ecc_strengths_h6,
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.reg_ecc_err_cnt = NFC_REG_H6_ECC_ERR_CNT,
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.reg_user_data = NFC_REG_H6_USER_DATA,
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.reg_user_data_len = NFC_REG_H6_USER_DATA_LEN,
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.reg_pat_found = NFC_REG_H6_PAT_FOUND,
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.reg_spare_area = NFC_REG_H6_SPARE_AREA,
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.reg_pat_id = NFC_REG_H6_PAT_ID,
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.pat_found_mask = GENMASK(31, 0),
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.ecc_mode_mask = GENMASK(15, 8),
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.random_en_mask = BIT(5),
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.user_data_len_tab = sunxi_user_data_len_h6,
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.nuser_data_tab = ARRAY_SIZE(sunxi_user_data_len_h6),
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.max_ecc_steps = 32,
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};
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static const struct udevice_id sunxi_nand_ids[] = {
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@ -1739,6 +1831,10 @@ static const struct udevice_id sunxi_nand_ids[] = {
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.compatible = "allwinner,sun4i-a10-nand",
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.data = (unsigned long)&sunxi_nfc_a10_caps,
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},
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{
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.compatible = "allwinner,sun50i-h616-nand-controller",
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.data = (unsigned long)&sunxi_nfc_h616_caps,
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},
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{ }
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};
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@ -44,15 +44,26 @@
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#define NFC_REG_IO_DATA 0x0030
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#define NFC_REG_ECC_CTL 0x0034
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#define NFC_REG_ECC_ST 0x0038
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#define NFC_REG_DEBUG 0x003C
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#define NFC_REG_H6_PAT_FOUND 0x003C
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#define NFC_REG_A10_ECC_ERR_CNT 0x0040
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#define NFC_REG_H6_ECC_ERR_CNT 0x0050
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#define NFC_REG_ECC_ERR_CNT(nfc, x) (((nfc)->caps->reg_ecc_err_cnt + (x)) & ~0x3)
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#define NFC_REG_A10_USER_DATA 0x0050
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#define NFC_REG_H6_USER_DATA 0x0080
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#define NFC_REG_H6_USER_DATA_LEN 0x0070
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#define NFC_REG_USER_DATA(nfc, x) ((nfc)->caps->reg_user_data + ((x) * 4))
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/* A USER_DATA_LEN register can hold the length of 8 USER_DATA registers */
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#define NFC_REG_USER_DATA_LEN_CAPACITY 8
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#define NFC_REG_USER_DATA_LEN(nfc, step) \
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((nfc)->caps->reg_user_data_len + \
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((step) / NFC_REG_USER_DATA_LEN_CAPACITY) * 4)
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#define NFC_REG_SPARE_AREA(nfc) ((nfc)->caps->reg_spare_area)
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#define NFC_REG_A10_SPARE_AREA 0x00A0
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#define NFC_REG_PAT_ID(nfc) ((nfc)->caps->reg_pat_id)
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#define NFC_REG_H6_SPARE_AREA 0x0114
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#define NFC_REG_PAT_ID(nfc) ((nfc)->caps->reg_pat_id)
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#define NFC_REG_A10_PAT_ID 0x00A4
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#define NFC_REG_H6_PAT_ID 0x0118
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#define NFC_RAM0_BASE 0x0400
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#define NFC_RAM1_BASE 0x0800
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@ -161,6 +172,9 @@
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#define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
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#define NFC_USER_DATA_LEN_MSK(step) \
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(0xf << (((step) % NFC_REG_USER_DATA_LEN_CAPACITY) * 4))
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#define NFC_DEFAULT_TIMEOUT_MS 1000
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#define NFC_SRAM_SIZE 1024
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@ -173,8 +187,10 @@
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*
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* @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks
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* @nstrengths: Number of element of ECC strengths array
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* @ecc_strengths: available ECC strengths array
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* @reg_ecc_err_cnt: ECC error counter register
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* @reg_user_data: User data register
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* @reg_user_data_len: User data length register
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* @reg_spare_area: Spare Area Register
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* @reg_pat_id: Pattern ID Register
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* @reg_pat_found: Data Pattern Status Register
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@ -182,12 +198,21 @@
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* @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register
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* @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register
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* @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register
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* @user_data_len_tab: Table of lenghts supported by USER_DATA_LEN register
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* The table index is the value to set in NFC_USER_DATA_LEN
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* registers, and the corresponding value is the number of
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* bytes to write
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* @nuser_data_tab: Size of @user_data_len_tab
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* @max_ecc_steps: Maximum supported steps for ECC, this is also the
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* number of user data registers
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*/
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struct sunxi_nfc_caps {
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bool has_ecc_block_512;
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unsigned int nstrengths;
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const u8 *ecc_strengths;
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unsigned int reg_ecc_err_cnt;
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unsigned int reg_user_data;
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unsigned int reg_user_data_len;
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unsigned int reg_spare_area;
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unsigned int reg_pat_id;
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unsigned int reg_pat_found;
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@ -195,6 +220,9 @@ struct sunxi_nfc_caps {
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unsigned int ecc_err_mask;
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unsigned int ecc_mode_mask;
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unsigned int random_en_mask;
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const u8 *user_data_len_tab;
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unsigned int nuser_data_tab;
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unsigned int max_ecc_steps;
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};
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#endif
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