Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-marvell into next

- mvebu: Fix boot mode detection (Pali)
- mvebu: clearfog: defconfig and eMMC updates (Martin)

arch/arm/dts/armada-388-clearfog-u-boot.dtsi

@@ -10,6 +10,7 @@
 
 &sdhci {
 	bootph-pre-ram;
+	non-removable; /* assume that the card is always present, required for eMMC variant */
 };
 
 &gpio0 {

arch/arm/mach-mvebu/Kconfig

@@ -107,6 +107,7 @@ config TARGET_CLEARFOG
 	bool "Support ClearFog"
 	select 88F6820
 	select BOARD_LATE_INIT
+	select OF_BOARD_SETUP
 
 config TARGET_HELIOS4
 	bool "Support Helios4"

arch/arm/mach-mvebu/cpu.c

@@ -67,6 +67,10 @@ u32 get_boot_device(void)
 {
 	u32 val;
 	u32 boot_device;
+	u32 boot_err_mode;
+#ifdef CONFIG_ARMADA_38X
+	u32 boot_err_code;
+#endif
 
 	/*
 	 * First check, if UART boot-mode is active. This can only
@@ -74,9 +78,9 @@ u32 get_boot_device(void)
 	 * MSB marks if the UART mode is active.
 	 */
 	val = readl(BOOTROM_ERR_REG);
-	boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
-	debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
-	if (boot_device == BOOTROM_ERR_MODE_UART)
+	boot_err_mode = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
+	debug("BOOTROM_ERR_REG=0x%08x boot_err_mode=0x%x\n", val, boot_err_mode);
+	if (boot_err_mode == BOOTROM_ERR_MODE_UART)
 		return BOOT_DEVICE_UART;
 
 #ifdef CONFIG_ARMADA_38X
@@ -84,8 +88,9 @@ u32 get_boot_device(void)
 	 * If the bootrom error code contains any other than zeros it's an
 	 * error condition and the bootROM has fallen back to UART boot
 	 */
-	boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
-	if (boot_device)
+	boot_err_code = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
+	debug("boot_err_code=0x%x\n", boot_err_code);
+	if (boot_err_code)
 		return BOOT_DEVICE_UART;
 #endif
 
@@ -95,31 +100,27 @@ u32 get_boot_device(void)
 	val = readl(CFG_SAR_REG);	/* SAR - Sample At Reset */
 	boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
 	debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
-	switch (boot_device) {
 #ifdef BOOT_FROM_NAND
-	case BOOT_FROM_NAND:
+	if (BOOT_FROM_NAND(boot_device))
 		return BOOT_DEVICE_NAND;
 #endif
 #ifdef BOOT_FROM_MMC
-	case BOOT_FROM_MMC:
-	case BOOT_FROM_MMC_ALT:
+	if (BOOT_FROM_MMC(boot_device))
 		return BOOT_DEVICE_MMC1;
 #endif
-	case BOOT_FROM_UART:
-#ifdef BOOT_FROM_UART_ALT
-	case BOOT_FROM_UART_ALT:
-#endif
+#ifdef BOOT_FROM_UART
+	if (BOOT_FROM_UART(boot_device))
 		return BOOT_DEVICE_UART;
+#endif
 #ifdef BOOT_FROM_SATA
-	case BOOT_FROM_SATA:
-	case BOOT_FROM_SATA_ALT:
+	if (BOOT_FROM_SATA(boot_device))
 		return BOOT_DEVICE_SATA;
 #endif
-	case BOOT_FROM_SPI:
+#ifdef BOOT_FROM_SPI
+	if (BOOT_FROM_SPI(boot_device))
 		return BOOT_DEVICE_SPI;
-	default:
+#endif
 	return BOOT_DEVICE_BOOTROM;
-	};
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)

arch/arm/mach-mvebu/include/mach/soc.h

@@ -128,7 +128,14 @@
 #define BOOTROM_ERR_REG		(MVEBU_REGISTER(0x182d0))
 #define BOOTROM_ERR_MODE_OFFS	28
 #define BOOTROM_ERR_MODE_MASK	(0xf << BOOTROM_ERR_MODE_OFFS)
+#define BOOTROM_ERR_MODE_MAIN	0x2
+#define BOOTROM_ERR_MODE_EXEC	0x3
 #define BOOTROM_ERR_MODE_UART	0x6
+#define BOOTROM_ERR_MODE_PEX	0x8
+#define BOOTROM_ERR_MODE_NOR	0x9
+#define BOOTROM_ERR_MODE_NAND	0xA
+#define BOOTROM_ERR_MODE_SATA	0xB
+#define BOOTROM_ERR_MODE_MMC	0xE
 #define BOOTROM_ERR_CODE_OFFS	0
 #define BOOTROM_ERR_CODE_MASK	(0xf << BOOTROM_ERR_CODE_OFFS)
 
@@ -143,8 +150,8 @@
 #define BOOT_DEV_SEL_OFFS	3
 #define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
 
-#define BOOT_FROM_UART		0x30
-#define BOOT_FROM_SPI		0x38
+#define BOOT_FROM_UART(x)	(x == 0x30)
+#define BOOT_FROM_SPI(x)	(x == 0x38)
 
 #define CFG_SYS_TCLK		((readl(CFG_SAR_REG) & BIT(20)) ? \
 				 200000000 : 166000000)
@@ -160,14 +167,14 @@
 #define BOOT_DEV_SEL_OFFS	4
 #define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)
 
-#define BOOT_FROM_NAND		0x0A
-#define BOOT_FROM_SATA		0x22
-#define BOOT_FROM_UART		0x28
-#define BOOT_FROM_SATA_ALT	0x2A
-#define BOOT_FROM_UART_ALT	0x3f
-#define BOOT_FROM_SPI		0x32
-#define BOOT_FROM_MMC		0x30
-#define BOOT_FROM_MMC_ALT	0x31
+#define BOOT_FROM_NOR(x)	((x >= 0x00 && x <= 0x07) || x == 0x16 || x == 0x17 || x == 0x2E || x == 0x2F || (x >= 0x3A && x <= 0x3C))
+#define BOOT_FROM_NAND(x)	((x >= 0x08 && x <= 0x15) || (x >= 0x18 && x <= 0x25))
+#define BOOT_FROM_SPINAND(x)	(x == 0x26 || x == 0x27)
+#define BOOT_FROM_UART(x)	(x == 0x28 || x == 0x29)
+#define BOOT_FROM_SATA(x)	(x == 0x2A || x == 0x2B)
+#define BOOT_FROM_PEX(x)	(x == 0x2C || x == 0x2D)
+#define BOOT_FROM_MMC(x)	(x == 0x30 || x == 0x31)
+#define BOOT_FROM_SPI(x)	(x >= 0x32 && x <= 0x39)
 
 #define CFG_SYS_TCLK		((readl(CFG_SAR_REG) & BIT(15)) ? \
 				 200000000 : 250000000)
@@ -184,9 +191,9 @@
 #define BOOT_DEV_SEL_OFFS	11
 #define BOOT_DEV_SEL_MASK	(0x7 << BOOT_DEV_SEL_OFFS)
 
-#define BOOT_FROM_NAND		0x1
-#define BOOT_FROM_UART		0x2
-#define BOOT_FROM_SPI		0x3
+#define BOOT_FROM_NAND(x)	(x == 0x1)
+#define BOOT_FROM_UART(x)	(x == 0x2)
+#define BOOT_FROM_SPI(x)	(x == 0x3)
 
 #define CFG_SYS_TCLK		200000000	/* 200MHz */
 #elif defined(CONFIG_ARMADA_XP)
@@ -206,8 +213,12 @@
 #define BOOT_DEV_SEL_OFFS	5
 #define BOOT_DEV_SEL_MASK	(0xf << BOOT_DEV_SEL_OFFS)
 
-#define BOOT_FROM_UART		0x2
-#define BOOT_FROM_SPI		0x3
+#define BOOT_FROM_NOR(x)	(x == 0x0)
+#define BOOT_FROM_NAND(x)	(x == 0x1)
+#define BOOT_FROM_UART(x)	(x == 0x2)
+#define BOOT_FROM_SPI(x)	(x == 0x3)
+#define BOOT_FROM_PEX(x)	(x == 0x4)
+#define BOOT_FROM_SATA(x)	(x == 0x5)
 
 #define CFG_SYS_TCLK		250000000	/* 250MHz */
 #endif

board/solidrun/clearfog/clearfog.c

@@ -10,6 +10,7 @@
 #include <miiphy.h>
 #include <net.h>
 #include <netdev.h>
+#include <mmc.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
@@ -261,3 +262,35 @@ int board_late_init(void)
 
 	return 0;
 }
+
+static bool has_emmc(void)
+{
+	struct mmc *mmc;
+
+	mmc = find_mmc_device(0);
+	if (!mmc)
+		return 0;
+	return (!mmc_init(mmc) && IS_MMC(mmc)) ? true : false;
+}
+
+/*
+ * The Clearfog devices have only one SDHC device. This is either eMMC
+ * if it is populated on the SOM or SDHC if not. The Linux device tree
+ * assumes the SDHC case. Detect if the device is an eMMC and fixup the
+ * device-tree, so that it will be detected by Linux.
+ */
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int node;
+
+	if (has_emmc()) {
+		node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-380-sdhci");
+		if (node < 0)
+			return 0; /* Unexpected eMMC device; patching not supported */
+
+		puts("Patching FDT so that eMMC is detected by OS\n");
+		return fdt_setprop_empty(blob, node, "non-removable");
+	}
+
+	return 0;
+}

configs/clearfog_spi_defconfig

@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x00800000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_TARGET_CLEARFOG=y
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
+CONFIG_SPL_TEXT_BASE=0x40000030
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xf1012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x22fd0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x40023000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_I2C=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_TLV_EEPROM=y
+CONFIG_SPL_CMD_TLV_EEPROM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_MIN_ENTRIES=128
+CONFIG_ARP_TIMEOUT=200
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_MV=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVNETA=y
+CONFIG_MII=y
+CONFIG_MVMDIO=y
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_SCSI=y
+CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y