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mtd: rawnand: atmel: set pmecc data setup time

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Setup the pmecc data setup time as 3 clock cycles for 133MHz as
recommended by the datasheet.

Backported from Linux: f55f552a7c7e0a1 ("mtd: rawnand: atmel: set pmecc
data setup time")

Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver")

Signed-off-by: Zixun LI <admin@hifiphile.com>
Tested-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
This commit is contained in:
Zixun LI 2025-11-07 16:02:23 +01:00 committed by Eugen Hristev
parent b10c055d4e
commit ee5053adcb
1 changed files with 6 additions and 0 deletions
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6
drivers/mtd/nand/raw/atmel/pmecc.c
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@ -142,6 +142,7 @@ struct atmel_pmecc_caps {
int nstrengths;
int el_offset;
bool correct_erased_chunks;
bool clk_ctrl;
};
struct atmel_pmecc_user_conf_cache {
@ -840,6 +841,10 @@ atmel_pmecc_create(struct udevice *dev,
pmecc->regs.timing = 0;
/* pmecc data setup time */
if (caps->clk_ctrl)
writel(PMECC_CLK_133MHZ, pmecc->regs.base + ATMEL_PMECC_CLK);
/* Disable all interrupts before registering the PMECC handler. */
writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR);
atmel_pmecc_reset(pmecc);
@ -884,6 +889,7 @@ static struct atmel_pmecc_caps at91sam9g45_caps = {
.strengths = atmel_pmecc_strengths,
.nstrengths = 5,
.el_offset = 0x8c,
.clk_ctrl = true,
};
static struct atmel_pmecc_caps sama5d4_caps = {