From 0c8baa619dffde84b07b3b7a71e801cab4f09f7e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 8 May 2019 14:47:05 +0200 Subject: [PATCH 1/8] arm: at91: gardena-smart-gateway-at91sam: Enable CMD_WDT This patch enables the "wdt" command, which is quite useful for watchdog testing. Signed-off-by: Stefan Roese Cc: Eugen Hristev --- configs/gardena-smart-gateway-at91sam_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index 577dceb2d4b..a25d3780640 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y From 57fbd36c668dfe0bff7eb2bca9c0d3d625f84185 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 3 May 2019 15:56:44 +0300 Subject: [PATCH 2/8] board: atmel: sama5d2_icp: add periph reset in SPL hw init Some periphs on the board need to be reset by holding their reset GPIO down for a specific time period. On a warm reset, the periphs are not being reset by any reset pin and may be in a wrong state. Reset them in the SPL to make sure we are booting into the correct state machine of the specific board periphs (KSZ eth switch, USB hub, HSIC eth, Ethercat) Signed-off-by: Eugen Hristev --- board/atmel/sama5d2_icp/sama5d2_icp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 807cfcdb196..1c28aaba85a 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -73,6 +73,23 @@ int misc_init_r(void) /* SPL */ #ifdef CONFIG_SPL_BUILD +/* deassert reset lines for external periph in case of warm reboot */ +static void board_reset_additional_periph(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */ +} + +static void board_start_additional_periph(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */ +} + #ifdef CONFIG_SD_BOOT void spl_mmc_init(void) { @@ -93,12 +110,18 @@ void spl_board_init(void) #ifdef CONFIG_SD_BOOT spl_mmc_init(); #endif + board_reset_additional_periph(); } void spl_display_print(void) { } +void spl_board_prepare_for_boot(void) +{ + board_start_additional_periph(); +} + static void ddrc_conf(struct atmel_mpddrc_config *ddrc) { ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); From 2950c514e8fc2c9d6a48cd7187521bc648dc679e Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 3 May 2019 16:24:21 +0300 Subject: [PATCH 3/8] board: atmel: sama5d2_icp: standby disable on CAN transceivers in SPL The 2 CAN transceivers have a STBDY pin which must be low in order to operate. This pin is tied to PB25. Set it to 0 in bootstrap. At a later time, this needs to be controlled by Linux power management system, or requested by some driver as a gpio and tied to 0 during CAN link up. Signed-off-by: Eugen Hristev --- board/atmel/sama5d2_icp/sama5d2_icp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 1c28aaba85a..f55ea2c6f89 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -73,6 +73,12 @@ int misc_init_r(void) /* SPL */ #ifdef CONFIG_SPL_BUILD +/* must set PB25 low to enable the CAN transceivers */ +static void board_can_stdby_dis(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0); +} + /* deassert reset lines for external periph in case of warm reboot */ static void board_reset_additional_periph(void) { @@ -111,6 +117,7 @@ void spl_board_init(void) spl_mmc_init(); #endif board_reset_additional_periph(); + board_can_stdby_dis(); } void spl_display_print(void) From bc2d313d68f8b8f21438d4e52ebb932cd4ce83b8 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 3 May 2019 16:26:53 +0300 Subject: [PATCH 4/8] board: atmel: sama5d2_icp: enable green led on SPL completion Enable the green led on SPL completion. Red led has no pulldown and it will be lighted by default when the board starts up. If the PMIC is not configured to enable LDO2, the leds will not light. Signed-off-by: Eugen Hristev --- board/atmel/sama5d2_icp/sama5d2_icp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index f55ea2c6f89..1593e2bd4ea 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -79,6 +79,13 @@ static void board_can_stdby_dis(void) atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0); } +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */ +} + /* deassert reset lines for external periph in case of warm reboot */ static void board_reset_additional_periph(void) { @@ -118,6 +125,7 @@ void spl_board_init(void) #endif board_reset_additional_periph(); board_can_stdby_dis(); + board_leds_init(); } void spl_display_print(void) From 1cee54ebf3e2d221213fbb45f0f86798c8979fd6 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 15 May 2019 09:12:39 +0000 Subject: [PATCH 5/8] configs: sama5d2_ptc_ek: fix NAND PMECC_CAP CONFIG_PMECC_CAP has a higher priority than its ONFI detected parameter and will overwrite it when defined. As per commit 49ad40298cc5, CONFIG_PMECC_CAP has a default value of 2 if not otherwise stated. This results in the overwriting of the ONFI ECC bits value. The following errors are seen when booting the kernel from the nand flash: Loading Environment from NAND... PMECC: Too many errors NAND read from offset 140000 failed -74 *** Warning - some problems detected reading environment; recovered successfully *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: eth0: ethernet@f8008000 Hit any key to stop autoboot: 0 NAND read: device 0 offset 0x180000, size 0x80000 PMECC: Too many errors NAND read from offset 180000 failed -74 0 bytes read: ERROR NAND read: device 0 offset 0x200000, size 0x600000 PMECC: Too many errors NAND read from offset 200000 failed -74 0 bytes read: ERROR Bad Linux ARM zImage magic! Fix it by setting the right value for ECC bits. Fixes: 49ad40298cc5 ("ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig") Signed-off-by: Tudor Ambarus --- configs/sama5d2_ptc_ek_mmc_defconfig | 1 + configs/sama5d2_ptc_ek_nandflash_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index bf2b5584df1..25b3aaf623e 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -51,6 +51,7 @@ CONFIG_MMC_SDHCI_ATMEL=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=4 CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index 9608ecd0b33..3f7e6270d0c 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=4 CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y From cd60ea71f380ee4c7af2a56419d6234878b950e4 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 28 May 2019 11:41:56 +0300 Subject: [PATCH 6/8] configs: atmel: sama5d4_xplained_mmc: enable HW PMECC NAND: BUG at drivers/mtd/nand/raw/nand_base.c:4361/nand_scan_tail()! This board has a NAND flash enabled, and it requires the HW PMECC in order to correctly probe this flash. In the NAND flash configuration , this is selected by the GENERATE_PMECC_HEADER which is not needed for mmc configuration. Signed-off-by: Eugen Hristev --- configs/sama5d4_xplained_mmc_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index f673832dffc..0504b4ec0fc 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -59,6 +59,8 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=8 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 From 0be07872e3200d9d0f6829e641166f0781327cdf Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 24 May 2019 09:38:10 +0300 Subject: [PATCH 7/8] spl: at91: add support for SPL_AT91_MCK_BYPASS By default the configuration of the PMC is to have an external crystal connected that requires driving on both XIN and XOUT pins. The bypass configuration means that only XIN will be used, the SoC will not do any driving, and the XIN needs to be provided with a proper signal. This is the MOSCXTBY bit in the PMC main clock generator register. The SPL needs to properly initialize the PMC registers before switching to external clock signal and raising the clock to the cruise speed. Also created Kconfig for this specific configuration. By default this is disabled. Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/spl_atmel.c | 8 ++++++++ common/spl/Kconfig | 12 ++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index ef745c94775..85290be3696 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -44,7 +44,15 @@ static void switch_to_main_crystal_osc(void) #endif tmp = readl(&pmc->mor); +/* + * some boards have an external oscillator with driving. + * in this case we need to disable the internal SoC driving (bypass mode) + */ +#if defined(CONFIG_SPL_AT91_MCK_BYPASS) + tmp |= AT91_PMC_MOR_OSCBYPASS; +#else tmp &= ~AT91_PMC_MOR_OSCBYPASS; +#endif tmp &= ~AT91_PMC_MOR_KEY(0xff); tmp |= AT91_PMC_MOR_KEY(0x37); writel(tmp, &pmc->mor); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index dd078fe79d1..0d01353ee84 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1151,5 +1151,17 @@ config TPL_YMODEM_SUPPORT endif # TPL +config SPL_AT91_MCK_BYPASS + bool "Use external clock signal as a source of main clock for AT91 platforms" + depends on ARCH_AT91 + default n + help + Use external 8 to 24 Mhz clock signal as source of main clock instead + of an external crystal oscillator. + This option disables the internal driving on the XOUT pin. + The external source has to provide a stable clock on the XIN pin. + If this option is disabled, the SoC expects a crystal oscillator + that needs driving on both XIN and XOUT lines. + endif # SPL endmenu From 9ed91550d548f76f40e22f0562ff3c4ba15f85c7 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 24 May 2019 09:40:08 +0300 Subject: [PATCH 8/8] configs: at91: sama5d2_icp: enable CONFIG_SPL_AT91_MCK_BYPASS and resync Enabled CONFIG_SPL_AT91_MCK_BYPASS and resync with savedefconfig Signed-off-by: Eugen Hristev --- configs/sama5d2_icp_mmc_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 1fafb767af7..e0471086d6a 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -23,12 +23,12 @@ CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -75,3 +75,4 @@ CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER_HII is not set