From 281256c064c9ea14b18c7f54ea8717a94eff28b2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 8 Aug 2019 09:55:33 +0000 Subject: [PATCH 001/190] arm: dts: sync dts for i.MX6UL Sync kernel dts for i.MX6UL from commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6ul-14x14-evk.dts | 422 +----------------- arch/arm/dts/imx6ul-14x14-evk.dtsi | 531 +++++++++++++++++++++++ arch/arm/dts/imx6ul-pinfunc.h | 175 ++++---- arch/arm/dts/imx6ul.dtsi | 301 ++++++++----- include/dt-bindings/clock/imx6ul-clock.h | 50 ++- 5 files changed, 863 insertions(+), 616 deletions(-) create mode 100644 arch/arm/dts/imx6ul-14x14-evk.dtsi diff --git a/arch/arm/dts/imx6ul-14x14-evk.dts b/arch/arm/dts/imx6ul-14x14-evk.dts index a642d776547..2438669f149 100644 --- a/arch/arm/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/dts/imx6ul-14x14-evk.dts @@ -1,427 +1,13 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. /dts-v1/; #include "imx6ul.dtsi" +#include "imx6ul-14x14-evk.dtsi" / { model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; - - aliases { - spi5 = &soft_spi; - }; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_sd1_vmmc: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - off-on-delay = <20000>; - enable-active-high; - }; - - reg_can_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; - }; - - reg_gpio_dvfs: regulator-gpio { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dvfs>; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1400000>; - regulator-name = "gpio_dvfs"; - regulator-type = "voltage"; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; - states = <1300000 0x1 1400000 0x0>; - }; - }; - - soft_spi: soft-spi { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4>; - pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - status = "okay"; - gpio-sck = <&gpio5 11 0>; - gpio-mosi = <&gpio5 10 0>; - cs-gpios = <&gpio5 7 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio_spi@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - registers-default = /bits/ 8 <0x57>; - spi-max-frequency = <100000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - status = "okay"; - - mag3110@0e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - position = <2>; - }; - - fxls8471@1e { - compatible = "fsl,fxls8471"; - reg = <0x1e>; - position = <0>; - interrupt-parent = <&gpio5>; - interrupts = <0 8>; - }; -}; - -&i2c2 { - clock_frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1>; - imx6ul-evk { - pinctrl_hog_1: hoggrp-1 { - fsl,pins = < - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 - >; - }; - - pinctrl_dvfs: dvfsgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp_gpio { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2grp_gpio { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_spi4: spi4grp { - fsl,pins = < - MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 - MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_8bit: usdhc2grp_8bit { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - >; - }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; - }; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - ddrsmp=<0>; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a"; - spi-max-frequency = <29000000>; - spi-nor,ddr-quad-read-dummy = <6>; - reg = <0>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbphy1 { - tx-d-cal = <0x5>; -}; - -&usbphy2 { - tx-d-cal = <0x5>; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; }; diff --git a/arch/arm/dts/imx6ul-14x14-evk.dtsi b/arch/arm/dts/imx6ul-14x14-evk.dtsi new file mode 100644 index 00000000000..d1baf0f0812 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk.dtsi @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +/ { + aliases { + spi5 = &{/spi4}; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + backlight_display: backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_3v3: regulator-can-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + }; + }; + + panel { + compatible = "innolux,at043tn24"; + backlight = <&backlight_display>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8960"; + reg = <0x1a>; + wlf,shared-lrclk; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + }; +}; + +&lcdif { + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sim2: sim2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-pinfunc.h b/arch/arm/dts/imx6ul-pinfunc.h index 0034eeb8454..380d2db13a9 100644 --- a/arch/arm/dts/imx6ul-pinfunc.h +++ b/arch/arm/dts/imx6ul-pinfunc.h @@ -1,10 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. */ #ifndef __DTS_IMX6UL_PINFUNC_H @@ -34,14 +30,14 @@ #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 #define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 #define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 #define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 @@ -63,12 +59,14 @@ #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 #define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 +#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0 #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 @@ -94,22 +92,24 @@ #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 #define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 +#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 @@ -200,7 +200,7 @@ #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 #define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 @@ -232,7 +232,7 @@ #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 @@ -242,7 +242,7 @@ #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 @@ -251,7 +251,7 @@ #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 @@ -259,7 +259,7 @@ #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 @@ -267,7 +267,7 @@ #define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 @@ -275,23 +275,23 @@ #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 #define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 @@ -299,59 +299,61 @@ #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 @@ -360,7 +362,7 @@ #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 @@ -377,7 +379,7 @@ #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 @@ -400,6 +402,7 @@ #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 @@ -412,7 +415,7 @@ #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 #define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 #define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 @@ -431,7 +434,7 @@ #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 @@ -440,7 +443,7 @@ #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 #define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 #define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 #define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 #define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 @@ -464,7 +467,7 @@ #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 @@ -477,13 +480,15 @@ #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 #define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 #define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 @@ -491,6 +496,7 @@ #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 #define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 #define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 @@ -498,14 +504,16 @@ #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 #define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 +#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 @@ -514,6 +522,7 @@ #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 @@ -522,6 +531,7 @@ #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 +#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 @@ -530,6 +540,7 @@ #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 @@ -537,56 +548,64 @@ #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 #define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 +#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 #define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 #define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 #define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 #define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 #define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 +#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 #define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 #define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 @@ -594,7 +613,8 @@ #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 #define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 @@ -602,7 +622,8 @@ #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 #define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 @@ -610,7 +631,7 @@ #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 #define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 #define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 @@ -622,7 +643,7 @@ #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 #define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 @@ -631,12 +652,12 @@ #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 #define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 #define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 @@ -644,7 +665,7 @@ #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 #define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 @@ -652,7 +673,7 @@ #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 #define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 #define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 @@ -660,42 +681,42 @@ #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 #define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 #define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 #define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 #define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 @@ -726,7 +747,7 @@ #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 #define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 @@ -748,7 +769,7 @@ #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 #define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 @@ -783,7 +804,7 @@ #define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 #define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 #define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 #define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 @@ -791,11 +812,11 @@ #define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 #define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 #define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 #define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 #define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 #define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 #define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 @@ -878,10 +899,10 @@ #define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 #define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 #define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 #define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 #define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 @@ -913,7 +934,7 @@ #define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 #define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 @@ -924,7 +945,7 @@ #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 #define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 #define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index 71b42d4a205..5644b0f34d5 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -1,19 +1,23 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2015 Freescale Semiconductor, Inc. #include #include #include #include #include "imx6ul-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + aliases { ethernet0 = &fec1; ethernet1 = &fec2; @@ -59,14 +63,17 @@ device_type = "cpu"; reg = <0>; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; operating-points = < /* kHz uV */ + 696000 1275000 528000 1175000 396000 1025000 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ + 696000 1275000 528000 1175000 396000 1175000 198000 1175000 @@ -77,30 +84,39 @@ <&clks IMX6UL_CA7_SECONDARY_SEL>, <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>, - <&clks IMX6UL_PLL1_BYPASS>, - <&clks IMX6UL_CLK_PLL1>, - <&clks IMX6UL_PLL1_BYPASS_SRC>, - <&clks IMX6UL_CLK_OSC>; + <&clks IMX6UL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", "pll1_sw", - "pll1_sys", "pll1_bypass", "pll1", - "pll1_bypass_src", "osc"; + "pll1_sys"; arm-supply = <®_arm>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a7-gic"; + intc: interrupt-controller@a01000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupts = ; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x00a01000 0x1000>, - <0x00a02000 0x1000>, + <0x00a02000 0x2000>, <0x00a04000 0x2000>, <0x00a06000 0x2000>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + ckil: clock-cli { compatible = "fixed-clock"; #clock-cells = <0>; @@ -129,6 +145,22 @@ clock-output-names = "ipp_di1"; }; + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gpc>; + interrupts = ; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -136,18 +168,12 @@ interrupt-parent = <&gpc>; ranges; - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - status = "disabled"; - }; - - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; }; - dma_apbh: dma-apbh@01804000 { + dma_apbh: dma-apbh@1804000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, @@ -160,7 +186,7 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; - gpmi: gpmi-nand@01806000 { + gpmi: gpmi-nand@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -180,22 +206,21 @@ status = "disabled"; }; - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - u-boot,dm-spl; - ecspi1: ecspi@02008000 { + ecspi1: spi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -207,7 +232,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: spi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -219,7 +244,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: spi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -231,7 +256,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: spi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -243,7 +268,7 @@ status = "disabled"; }; - uart7: serial@02018000 { + uart7: serial@2018000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02018000 0x4000>; @@ -254,7 +279,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02020000 0x4000>; @@ -265,7 +290,7 @@ status = "disabled"; }; - uart8: serial@02024000 { + uart8: serial@2024000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02024000 0x4000>; @@ -276,7 +301,7 @@ status = "disabled"; }; - sai1: sai@02028000 { + sai1: sai@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x02028000 0x4000>; @@ -291,7 +316,7 @@ status = "disabled"; }; - sai2: sai@0202c000 { + sai2: sai@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x0202c000 0x4000>; @@ -306,7 +331,7 @@ status = "disabled"; }; - sai3: sai@02030000 { + sai3: sai@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x02030000 0x4000>; @@ -322,7 +347,7 @@ }; }; - tsc: tsc@02040000 { + tsc: tsc@2040000 { compatible = "fsl,imx6ul-tsc"; reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; interrupts = , @@ -333,10 +358,10 @@ status = "disabled"; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6UL_CLK_PWM1>, <&clks IMX6UL_CLK_PWM1>; clock-names = "ipg", "per"; @@ -344,10 +369,10 @@ status = "disabled"; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6UL_CLK_PWM2>, <&clks IMX6UL_CLK_PWM2>; clock-names = "ipg", "per"; @@ -355,10 +380,10 @@ status = "disabled"; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6UL_CLK_PWM3>, <&clks IMX6UL_CLK_PWM3>; clock-names = "ipg", "per"; @@ -366,10 +391,10 @@ status = "disabled"; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6UL_CLK_PWM4>, <&clks IMX6UL_CLK_PWM4>; clock-names = "ipg", "per"; @@ -377,27 +402,29 @@ status = "disabled"; }; - can1: flexcan@02090000 { + can1: flexcan@2090000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_CAN1_IPG>, <&clks IMX6UL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; - can2: flexcan@02094000 { + can2: flexcan@2094000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_CAN2_IPG>, <&clks IMX6UL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; - gpt1: gpt@02098000 { + gpt1: gpt@2098000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x02098000 0x4000>; interrupts = ; @@ -406,11 +433,12 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -419,11 +447,12 @@ <&iomuxc 16 33 16>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -431,11 +460,12 @@ gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -443,11 +473,12 @@ gpio-ranges = <&iomuxc 0 65 29>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -455,11 +486,12 @@ gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO5>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -467,9 +499,10 @@ gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; }; - fec2: ethernet@020b4000 { + fec2: ethernet@20b4000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x020b4000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = , ; clocks = <&clks IMX6UL_CLK_ENET>, @@ -484,7 +517,7 @@ status = "disabled"; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = ; @@ -492,14 +525,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_WDOG1>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = ; @@ -507,7 +540,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6ul-ccm"; reg = <0x020c4000 0x4000>; interrupts = , @@ -517,7 +550,7 @@ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; @@ -574,7 +607,7 @@ }; }; - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = ; @@ -583,7 +616,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = ; @@ -592,7 +625,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -608,6 +641,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; + value = <0x60>; mask = <0x60>; status = "disabled"; }; @@ -619,19 +653,23 @@ linux,keycode = ; wakeup-source; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6ul-snvs-lpgpr"; + }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = ; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = ; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6ul-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , @@ -639,7 +677,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -648,18 +686,18 @@ interrupt-parent = <&intc>; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6ul-iomuxc"; reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@020e4000 { + gpr: iomuxc-gpr@20e4000 { compatible = "fsl,imx6ul-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; - gpt2: gpt@020e8000 { + gpt2: gpt@20e8000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x020e8000 0x4000>; interrupts = ; @@ -668,19 +706,19 @@ clock-names = "ipg", "per"; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6UL_CLK_SDMA>, + clocks = <&clks IMX6UL_CLK_IPG>, <&clks IMX6UL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; - pwm5: pwm@020f0000 { + pwm5: pwm@20f0000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f0000 0x4000>; interrupts = ; @@ -691,7 +729,7 @@ status = "disabled"; }; - pwm6: pwm@020f4000 { + pwm6: pwm@20f4000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f4000 0x4000>; interrupts = ; @@ -702,7 +740,7 @@ status = "disabled"; }; - pwm7: pwm@020f8000 { + pwm7: pwm@20f8000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f8000 0x4000>; interrupts = ; @@ -713,7 +751,7 @@ status = "disabled"; }; - pwm8: pwm@020fc000 { + pwm8: pwm@20fc000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020fc000 0x4000>; interrupts = ; @@ -725,14 +763,44 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - usbotg1: usb@02184000 { + crypto: caam@2140000 { + compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2140000 0x3c000>; + ranges = <0 0x2140000 0x3c000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, + <&clks IMX6UL_CLK_CAAM_MEM>; + clock-names = "ipg", "aclk", "mem"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + }; + + usbotg1: usb@2184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = ; @@ -746,7 +814,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = ; @@ -759,15 +827,16 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; }; - fec1: ethernet@02188000 { + fec1: ethernet@2188000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = , ; clocks = <&clks IMX6UL_CLK_ENET>, @@ -782,7 +851,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02190000 0x4000>; interrupts = ; @@ -794,7 +863,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02194000 0x4000>; interrupts = ; @@ -806,7 +875,7 @@ status = "disabled"; }; - adc1: adc@02198000 { + adc1: adc@2198000 { compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; reg = <0x02198000 0x4000>; interrupts = ; @@ -818,7 +887,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -828,7 +897,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -838,7 +907,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -848,12 +917,44 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; }; - lcdif: lcdif@021c8000 { + weim: weim@21b8000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_EIM>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; + }; + + ocotp: ocotp-ctrl@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6ul-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6UL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + }; + + lcdif: lcdif@21c8000 { compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; reg = <0x021c8000 0x4000>; interrupts = ; @@ -864,7 +965,7 @@ status = "disabled"; }; - qspi: qspi@021e0000 { + qspi: spi@21e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; @@ -877,7 +978,7 @@ status = "disabled"; }; - wdog3: wdog@021e4000 { + wdog3: wdog@21e4000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x021e4000 0x4000>; interrupts = ; @@ -885,7 +986,7 @@ status = "disabled"; }; - uart2: serial@021e8000 { + uart2: serial@21e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021e8000 0x4000>; @@ -896,7 +997,7 @@ status = "disabled"; }; - uart3: serial@021ec000 { + uart3: serial@21ec000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021ec000 0x4000>; @@ -907,7 +1008,7 @@ status = "disabled"; }; - uart4: serial@021f0000 { + uart4: serial@21f0000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021f0000 0x4000>; @@ -918,7 +1019,7 @@ status = "disabled"; }; - uart5: serial@021f4000 { + uart5: serial@21f4000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021f4000 0x4000>; @@ -929,7 +1030,7 @@ status = "disabled"; }; - i2c4: i2c@021f8000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -939,7 +1040,7 @@ status = "disabled"; }; - uart6: serial@021fc000 { + uart6: serial@21fc000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021fc000 0x4000>; diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index 4623f170a8f..79094338e6f 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -1,10 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * + * Copyright (C) 2015 Freescale Semiconductor, Inc. */ #ifndef __DT_BINDINGS_CLOCK_IMX6UL_H @@ -105,7 +101,7 @@ #define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 #define IMX6UL_CLK_ARM 93 #define IMX6UL_CLK_PERIPH_CLK2 94 -#define IMX6UL_CLK_PERIPH2_CLK2 95 +#define IMX6UL_CLK_PERIPH2_CLK2 95 #define IMX6UL_CLK_AHB 96 #define IMX6UL_CLK_MMDC_PODF 97 #define IMX6UL_CLK_AXI_PODF 98 @@ -235,20 +231,32 @@ #define IMX6UL_CLK_CSI_PODF 222 #define IMX6UL_CLK_PLL3_120M 223 #define IMX6UL_CLK_KPP 224 -/* For i.MX6ULL */ -#define IMX6UL_CLK_ESAI_SEL 224 -#define IMX6UL_CLK_ESAI_PRED 225 -#define IMX6UL_CLK_ESAI_PODF 226 -#define IMX6UL_CLK_ESAI_EXTAL 227 -#define IMX6UL_CLK_ESAI_MEM 228 -#define IMX6UL_CLK_ESAI_IPG 229 -#define IMX6UL_CLK_DCP_CLK 230 -#define IMX6UL_CLK_EPDC_PRE_SEL 231 -#define IMX6UL_CLK_EPDC_SEL 232 -#define IMX6UL_CLK_EPDC_PODF 233 -#define IMX6UL_CLK_EPDC_ACLK 234 -#define IMX6UL_CLK_EPDC_PIX 235 +#define IMX6ULL_CLK_ESAI_PRED 225 +#define IMX6ULL_CLK_ESAI_PODF 226 +#define IMX6ULL_CLK_ESAI_EXTAL 227 +#define IMX6ULL_CLK_ESAI_MEM 228 +#define IMX6ULL_CLK_ESAI_IPG 229 +#define IMX6ULL_CLK_DCP_CLK 230 +#define IMX6ULL_CLK_EPDC_PRE_SEL 231 +#define IMX6ULL_CLK_EPDC_SEL 232 +#define IMX6ULL_CLK_EPDC_PODF 233 +#define IMX6ULL_CLK_EPDC_ACLK 234 +#define IMX6ULL_CLK_EPDC_PIX 235 +#define IMX6ULL_CLK_ESAI_SEL 236 +#define IMX6UL_CLK_CKO1_SEL 237 +#define IMX6UL_CLK_CKO1_PODF 238 +#define IMX6UL_CLK_CKO1 239 +#define IMX6UL_CLK_CKO2_SEL 240 +#define IMX6UL_CLK_CKO2_PODF 241 +#define IMX6UL_CLK_CKO2 242 +#define IMX6UL_CLK_CKO 243 +#define IMX6UL_CLK_GPIO1 244 +#define IMX6UL_CLK_GPIO2 245 +#define IMX6UL_CLK_GPIO3 246 +#define IMX6UL_CLK_GPIO4 247 +#define IMX6UL_CLK_GPIO5 248 +#define IMX6UL_CLK_MMDC_P1_IPG 249 -#define IMX6UL_CLK_END 236 +#define IMX6UL_CLK_END 250 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ From c15838128847a03e1aac6b61dd9c7d7ffb0ed30e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 8 Aug 2019 09:55:37 +0000 Subject: [PATCH 002/190] arm: dts: sync dts for i.MX6ULL Sync kernel dts for i.MX6ULL from commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6ull-14x14-evk.dts | 523 +----------- arch/arm/dts/imx6ull-pinfunc-snvs.h | 7 +- arch/arm/dts/imx6ull-pinfunc.h | 116 ++- arch/arm/dts/imx6ull.dtsi | 1190 ++------------------------- 4 files changed, 130 insertions(+), 1706 deletions(-) diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 9ebcfe1f4ea..74aaa8a56a3 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -1,527 +1,18 @@ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. /dts-v1/; #include "imx6ull.dtsi" +#include "imx6ul-14x14-evk.dtsi" / { - model = "Freescale i.MX6 ULL 14x14 EVK Board"; + model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_can_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; - }; - - reg_sd1_vmmc: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_gpio_dvfs: regulator-gpio { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dvfs>; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1400000>; - regulator-name = "gpio_dvfs"; - regulator-type = "voltage"; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; - states = <1300000 0x1 1400000 0x0>; - }; - }; - - spi5 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4>; - status = "okay"; - gpio-sck = <&gpio5 11 0>; - gpio-mosi = <&gpio5 10 0>; - cs-gpios = <&gpio5 7 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio_spi@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - oe-gpios = <&gpio5 8 0>; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - registers-default = /bits/ 8 <0x57>; - spi-max-frequency = <100000>; - }; - }; -}; - -&cpu0 { - arm-supply = <®_arm>; - soc-supply = <®_soc>; - dc-supply = <®_gpio_dvfs>; }; &clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&gpc { - fsl,cpu_pupscr_sw2iso = <0x1>; - fsl,cpu_pupscr_sw = <0x0>; - fsl,cpu_pdnscr_iso2sw = <0x1>; - fsl,cpu_pdnscr_iso = <0x1>; - fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - mag3110@0e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - position = <2>; - }; - - fxls8471@1e { - compatible = "fsl,fxls8471"; - reg = <0x1e>; - position = <0>; - interrupt-parent = <&gpio5>; - interrupts = <0 8>; - }; -}; - -&i2c2 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1>; - imx6ul-evk { - pinctrl_hog_1: hoggrp-1 { - fsl,pins = < - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ - >; - }; - - pinctrl_csi1: csi1grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 - MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 - MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 - MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 - MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 - MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 - MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 - MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 - MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 - MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 - MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 - MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_uart2dte: uart2dtegrp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; - }; -}; - -&iomuxc_snvs { - pinctrl-names = "default_snvs"; - pinctrl-0 = <&pinctrl_hog_2>; - imx6ul-evk { - pinctrl_hog_2: hoggrp-2 { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 - >; - }; - - pinctrl_dvfs: dvfsgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 - >; - }; - - pinctrl_lcdif_reset: lcdifresetgrp { - fsl,pins = < - /* used for lcd reset */ - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_spi4: spi4grp { - fsl,pins = < - MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 - >; - }; - - pinctrl_sai2_hp_det_b: sai2_hp_det_grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 - >; - }; - }; -}; - - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl - &pinctrl_lcdif_reset>; - display = <&display0>; - status = "okay"; - - display0: display { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - ddrsmp=<0>; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - /* compatible = "micron,n25q256a"; */ - compatible = "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-nor,ddr-quad-read-dummy = <6>; - reg = <0>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; - /* for DTE mode, add below change */ - /* fsl,dte-mode; */ - /* pinctrl-0 = <&pinctrl_uart2dte>; */ - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbphy1 { - tx-d-cal = <0x5>; -}; - -&usbphy2 { - tx-d-cal = <0x5>; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - enable-sdio-wakeup; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - enable-sdio-wakeup; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,wdog_b; + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; + assigned-clock-rates = <320000000>; }; diff --git a/arch/arm/dts/imx6ull-pinfunc-snvs.h b/arch/arm/dts/imx6ull-pinfunc-snvs.h index da3f412e426..54cfe72295a 100644 --- a/arch/arm/dts/imx6ull-pinfunc-snvs.h +++ b/arch/arm/dts/imx6ull-pinfunc-snvs.h @@ -1,9 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2017 NXP */ #ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H @@ -26,4 +24,3 @@ #define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 #endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ - diff --git a/arch/arm/dts/imx6ull-pinfunc.h b/arch/arm/dts/imx6ull-pinfunc.h index 7770ed39f62..eb025a9d475 100644 --- a/arch/arm/dts/imx6ull-pinfunc.h +++ b/arch/arm/dts/imx6ull-pinfunc.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __DTS_IMX6ULL_PINFUNC_H @@ -14,46 +11,77 @@ * The pin function ID is a tuple of * */ -#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 0x3 0x0 +/* signals common for i.MX6UL and i.MX6ULL */ +#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 +#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 +#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 +#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 +#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 -#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 -#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 -#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 -#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 -#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 -#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 -#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 -#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 -#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 - -#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 -#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 +/* signals for i.MX6ULL only */ +#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 +#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 +#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3 +#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4 +#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0 +#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 #endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 4598f2f4119..22e4a307fa5 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -1,1173 +1,81 @@ -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2016 Freescale Semiconductor, Inc. -#include -#include -#include -#include +#include "imx6ul.dtsi" #include "imx6ull-pinfunc.h" #include "imx6ull-pinfunc-snvs.h" -#include "skeleton.dtsi" + +/* Delete UART8 in AIPS-1 (i.MX6UL specific) */ +/delete-node/ &uart8; +/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ +/delete-node/ &crypto; + +&cpu0 { + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1250000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&ocotp { + compatible = "fsl,imx6ull-ocotp", "syscon"; +}; + +&usdhc1 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; / { - aliases { - can0 = &flexcan1; - can1 = &flexcan2; - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - spi0 = &qspi; - spi1 = &ecspi1; - spi2 = &ecspi2; - spi3 = &ecspi3; - spi4 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-latency = <61036>; /* two CLK32 periods */ - operating-points = < - /* kHz uV */ - 528000 1175000 - 99000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 528000 1175000 - 99000 1175000 - >; - clocks = <&clks IMX6UL_CLK_ARM>, - <&clks IMX6UL_CLK_PLL2_BUS>, - <&clks IMX6UL_CLK_PLL2_PFD2>, - <&clks IMX6UL_CA7_SECONDARY_SEL>, - <&clks IMX6UL_CLK_STEP>, - <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>, - <&clks IMX6UL_PLL1_BYPASS>, - <&clks IMX6UL_CLK_PLL1>, - <&clks IMX6UL_PLL1_BYPASS_SRC>, - <&clks IMX6UL_CLK_OSC>; - clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", - "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc"; - }; - }; - - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a02000 0x100>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock@3 { - compatible = "fixed-clock"; - reg = <3>; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - }; - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - busfreq { - compatible = "fsl,imx_busfreq"; - clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, - <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, - <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, - <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, - <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, - <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, - <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, - <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, - <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>, - <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1>; - clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", - "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", - "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", - "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; - fsl,max_ddr_freq = <400000000>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - status = "disabled"; - }; - - ocrams: sram@00900000 { - compatible = "fsl,lpm-sram"; - reg = <0x00900000 0x4000>; - }; - - ocrams_ddr: sram@00904000 { - compatible = "fsl,ddr-lpm-sram"; - reg = <0x00904000 0x1000>; - }; - - ocram: sram@00905000 { - compatible = "mmio-sram"; - reg = <0x00905000 0x1B000>; - }; - - dma_apbh: dma-apbh@01804000 { - compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x01804000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6UL_CLK_APBHDMA>; - }; - - gpmi: gpmi-nand@01806000{ - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01806000 0x2000>, <0x01808000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clks IMX6UL_CLK_GPMI_IO>, - <&clks IMX6UL_CLK_GPMI_APB>, - <&clks IMX6UL_CLK_GPMI_BCH>, - <&clks IMX6UL_CLK_GPMI_BCH_APB>, - <&clks IMX6UL_CLK_PER_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - aips1: aips-bus@02000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@02000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@02004000 { - compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = ; - dmas = <&sdma 41 18 0>, - <&sdma 42 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>, - <&clks IMX6UL_CLK_OSC>, - <&clks IMX6UL_CLK_SPDIF>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "dma"; - status = "disabled"; - }; - - ecspi1: ecspi@02008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI1>, - <&clks IMX6UL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: ecspi@0200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI2>, - <&clks IMX6UL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: ecspi@02010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI3>, - <&clks IMX6UL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi4: ecspi@02014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI4>, - <&clks IMX6UL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart7: serial@02018000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02018000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART7_IPG>, - <&clks IMX6UL_CLK_UART7_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@02020000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART1_IPG>, - <&clks IMX6UL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - esai: esai@02024000 { - compatible = "fsl,imx6ull-esai"; - reg = <0x02024000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ESAI_IPG>, - <&clks IMX6UL_CLK_ESAI_MEM>, - <&clks IMX6UL_CLK_ESAI_EXTAL>, - <&clks IMX6UL_CLK_ESAI_IPG>, - <&clks IMX6UL_CLK_SPBA>; - clock-names = "core", "mem", "extal", - "fsys", "dma"; - dmas = <&sdma 0 21 0>, <&sdma 47 21 0>; - dma-names = "rx", "tx"; - dma-source = <&gpr 0 14 0 15>; - status = "disabled"; - }; - - sai1: sai@02028000 { - compatible = "fsl,imx6ul-sai", - "fsl,imx6sx-sai"; - reg = <0x02028000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI1_IPG>, - <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_SAI1>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 35 24 0>, <&sdma 36 24 0>; - status = "disabled"; - }; - - sai2: sai@0202c000 { - compatible = "fsl,imx6ul-sai", - "fsl,imx6sx-sai"; - reg = <0x0202c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI2_IPG>, - <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_SAI2>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 37 24 0>, <&sdma 38 24 0>; - status = "disabled"; - }; - - sai3: sai@02030000 { - compatible = "fsl,imx6ul-sai", - "fsl,imx6sx-sai"; - reg = <0x02030000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI3_IPG>, - <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_SAI3>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 39 24 0>, <&sdma 40 24 0>; - status = "disabled"; - }; - - asrc: asrc@02034000 { - compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ASRC_IPG>, - <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, - <&clks IMX6UL_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck_0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f", "dma"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; - status = "okay"; - }; - }; - - tsc: tsc@02040000 { - compatible = "fsl,imx6ul-tsc"; - reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_ADC2>; - clock-names = "tsc", "adc"; - status = "disabled"; - }; - - pwm1: pwm@02080000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM1>, - <&clks IMX6UL_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm2: pwm@02084000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm3: pwm@02088000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM3>, - <&clks IMX6UL_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm4: pwm@0208c000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - flexcan1: can@02090000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN1_IPG>, - <&clks IMX6UL_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - stop-mode = <&gpr 0x10 1 0x10 17>; - status = "disabled"; - }; - - flexcan2: can@02094000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN2_IPG>, - <&clks IMX6UL_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - stop-mode = <&gpr 0x10 2 0x10 18>; - status = "disabled"; - }; - - gpt1: gpt@02098000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_GPT1_BUS>, - <&clks IMX6UL_CLK_GPT1_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@0209c000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@020a0000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@020a4000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@020a8000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@020ac000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - snvslp: snvs@020b0000 { - compatible = "fsl,imx6ul-snvs"; - reg = <0x020b0000 0x4000>; - interrupts = ; - }; - - fec2: ethernet@020b4000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x020b4000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET2_REF_125M>, - <&clks IMX6UL_CLK_ENET2_REF_125M>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - stop-mode = <&gpr 0x10 4>; - fsl,num-tx-queues=<1>; - fsl,num-rx-queues=<1>; - fsl,magic-packet; - fsl,wakeup_irq = <0>; - status = "disabled"; - }; - - kpp: kpp@020b8000 { - compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: wdog@020bc000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG1>; - }; - - wdog2: wdog@020c0000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG2>; - status = "disabled"; - }; - - clks: ccm@020c4000 { - compatible = "fsl,imx6ul-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; - }; - - anatop: anatop@020c8000 { - compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", - "syscon", "simple-bus"; - reg = <0x020c8000 0x1000>; - interrupts = , - , - ; - - reg_3p0: regulator-3p0@120 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2625000>; - regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore@140 { - compatible = "fsl,anatop-regulator"; - regulator-name = "cpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc@140 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - usbphy1: usbphy@020c9000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY1>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@020ca000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY2>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - tempmon: tempmon { - compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; - interrupts = ; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; - }; - - snvs: snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x61>; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup; - }; - }; - - epit1: epit@020d0000 { - reg = <0x020d0000 0x4000>; - interrupts = ; - }; - - epit2: epit@020d4000 { - reg = <0x020d4000 0x4000>; - interrupts = ; - }; - - src: src@020d8000 { - compatible = "fsl,imx6ul-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: gpc@020dc000 { - compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>; - }; - - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6ul-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@020e4000 { - compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - mqs: mqs { - compatible = "fsl,imx6sx-mqs"; - gpr = <&gpr>; - status = "disabled"; - }; - - gpt2: gpt@020e8000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; - reg = <0x020e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "ipg", "per"; - }; - - sdma: sdma@020ec000 { - compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SDMA>, - <&clks IMX6UL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - iram = <&ocram>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pwm5: pwm@020f0000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm6: pwm@020f4000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm7: pwm@020f8000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm8: pwm@020fc000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - }; - - aips2: aips-bus@02100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@02184000 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@02184200 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@02184800 { - #index-cells = <1>; - compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - }; - - fec1: ethernet@02188000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET_REF>, - <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - stop-mode = <&gpr 0x10 3>; - fsl,num-tx-queues=<1>; - fsl,num-rx-queues=<1>; - fsl,magic-packet; - fsl,wakeup_irq = <0>; - status = "disabled"; - }; - - usdhc1: usdhc@02190000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc2: usdhc@02194000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - adc1: adc@02198000 { - compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ADC1>; - num-channels = <2>; - clock-names = "adc"; - status = "disabled"; - }; - - i2c1: i2c@021a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@021a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@021a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C3>; - status = "disabled"; - }; - - romcp@021ac000 { - compatible = "fsl,imx6ul-romcp", "syscon"; - reg = <0x021ac000 0x4000>; - }; - - mmdc: mmdc@021b0000 { - compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - }; - - weim: weim@021b8000 { - compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>; - }; - - ocotp: ocotp-ctrl@021bc000 { - compatible = "fsl,imx6ull-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6UL_CLK_OCOTP>; - }; - - csu: csu@021c0000 { - compatible = "fsl,imx6ul-csu"; - reg = <0x021c0000 0x4000>; - interrupts = ; - status = "disabled"; - }; - - csi: csi@021c4000 { - compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi"; - reg = <0x021c4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_CSI>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "disp-axi", "csi_mclk", "disp_dcic"; - status = "disabled"; - }; - - lcdif: lcdif@021c8000 { - compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; - reg = <0x021c8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, - <&clks IMX6UL_CLK_LCDIF_APB>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - pxp: pxp@021cc000 { - compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; - reg = <0x021cc000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>; - clock-names = "pxp_ipg", "pxp_axi"; - status = "disabled"; - }; - - qspi: qspi@021e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi"; - reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6UL_CLK_QSPI>, - <&clks IMX6UL_CLK_QSPI>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - wdog3: wdog@021e4000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x021e4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG3>; - status = "disabled"; - }; - - uart2: serial@021e8000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART2_IPG>, - <&clks IMX6UL_CLK_UART2_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@021ec000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART3_IPG>, - <&clks IMX6UL_CLK_UART3_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@021f0000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART4_IPG>, - <&clks IMX6UL_CLK_UART4_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@021f4000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART5_IPG>, - <&clks IMX6UL_CLK_UART5_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@021f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C4>; - status = "disabled"; - }; - - uart6: serial@021fc000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART6_IPG>, - <&clks IMX6UL_CLK_UART6_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - aips3: aips-bus@02200000 { + aips3: aips-bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02200000 0x100000>; ranges; - dcp: dcp@02280000 { + dcp: crypto@2280000 { + compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; reg = <0x02280000 0x4000>; interrupts = , , ; - /*clocks = <&clks IMX6UL_CLK_DCP>;*/ + clocks = <&clks IMX6ULL_CLK_DCP_CLK>; clock-names = "dcp"; - status = "disabled"; }; - rngb: rngb@02284000 { - reg = <0x02284000 0x4000>; - interrupts = ; + iomuxc_snvs: iomuxc-snvs@2290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x4000>; }; - uart8: serial@02288000 { + uart8: serial@2288000 { compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart"; reg = <0x02288000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_UART8_IPG>, <&clks IMX6UL_CLK_UART8_SERIAL>; clock-names = "ipg", "per"; - dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; - dma-names = "rx", "tx"; status = "disabled"; }; - - epdc: epdc@0228c000 { - compatible = "fsl,imx7d-epdc"; - interrupts = ; - reg = <0x0228c000 0x4000>; - clocks = <&clks IMX6UL_CLK_EPDC_ACLK>, - <&clks IMX6UL_CLK_EPDC_PIX>; - clock-names = "epdc_axi", "epdc_pix"; - /* Need to fix epdc-ram */ - /* epdc-ram = <&gpr 0x4 30>; */ - status = "disabled"; - }; - - iomuxc_snvs: iomuxc-snvs@02290000 { - compatible = "fsl,imx6ull-iomuxc-snvs"; - reg = <0x02290000 0x10000>; - }; - - snvs_gpr: snvs-gpr@0x02294000 { - compatible = "fsl, imx6ull-snvs-gpr"; - reg = <0x02294000 0x10000>; - }; }; }; }; From 939a9644f0d02f63756dd92b7503f752919d6140 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 8 Aug 2019 09:55:47 +0000 Subject: [PATCH 003/190] arm: dts: import dts for i.MX6ULZ Import kernel dts for i.MX6ULZ from commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Fabio Estevam --- arch/arm/dts/Makefile | 3 ++- arch/arm/dts/imx6ulz.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ulz.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 62da168ef86..8170c39e07e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -606,7 +606,8 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ imx6ull-phycore-segin.dtb \ - imx6ull-dart-6ul.dtb + imx6ull-dart-6ul.dtb \ + imx6ulz-14x14-evk.dtb dtb-$(CONFIG_ARCH_MX6) += \ imx6-apalis.dtb \ diff --git a/arch/arm/dts/imx6ulz.dtsi b/arch/arm/dts/imx6ulz.dtsi new file mode 100644 index 00000000000..aeb2ddc540e --- /dev/null +++ b/arch/arm/dts/imx6ulz.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2018 NXP. + +#include "imx6ull.dtsi" + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ ethernet1; + /delete-property/ i2c2; + /delete-property/ i2c3; + /delete-property/ serial4; + /delete-property/ serial5; + /delete-property/ serial6; + /delete-property/ serial7; + /delete-property/ spi2; + /delete-property/ spi3; + /delete-property/ spi4; + }; +}; + +/delete-node/ &adc1; +/delete-node/ &ecspi3; +/delete-node/ &ecspi4; +/delete-node/ &epit2; +/delete-node/ &gpt2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &pwm5; +/delete-node/ &pwm6; +/delete-node/ &pwm7; +/delete-node/ &pwm8; +/delete-node/ &uart5; +/delete-node/ &uart6; +/delete-node/ &uart7; +/delete-node/ &uart8; From 81ae46c2e69f2864d73caa59a35e0887d155705e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 8 Aug 2019 09:55:52 +0000 Subject: [PATCH 004/190] imx: add i.MX6ULZ cpu type Add i.MX6ULZ cpu type and helper. Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/cpu.c | 2 ++ arch/arm/mach-imx/mx6/soc.c | 4 ++++ 4 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index d4a83eef72d..073efcd1b42 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -17,6 +17,7 @@ #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6UL 0x64 #define MXC_CPU_MX6ULL 0x65 +#define MXC_CPU_MX6ULZ 0x6B #define MXC_CPU_MX6SOLO 0x66 /* dummy */ #define MXC_CPU_MX6SLL 0x67 #define MXC_CPU_MX6D 0x6A diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 4925dd78945..260608062e1 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -38,6 +38,7 @@ #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) +#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 6e9a1752109..73ce7f8d7d5 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -173,6 +173,8 @@ const char *get_imx_type(u32 imxtype) return "6UL"; /* Ultra-Lite version of the mx6 */ case MXC_CPU_MX6ULL: return "6ULL"; /* ULL version of the mx6 */ + case MXC_CPU_MX6ULZ: + return "6ULZ"; /* ULZ version of the mx6 */ case MXC_CPU_MX51: return "51"; case MXC_CPU_MX53: diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 075d2467ce4..d37d3856d3e 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -85,6 +85,10 @@ u32 get_cpu_rev(void) type = MXC_CPU_MX6D; } + if (type == MXC_CPU_MX6ULL) { + if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6)) + type = MXC_CPU_MX6ULZ; + } } major = ((reg >> 8) & 0xff); if ((major >= 1) && From 1d293e6804fe077853636b0517ef00609299936e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 8 Aug 2019 09:55:57 +0000 Subject: [PATCH 005/190] imx: add i.MX6ULZ board Add i.MX6ULZ board support. the i.MX6ULZ is SW compatible with i.MX6ULL. so most code of i.MX6ULL can be reused by i.MX6ULZ. Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6ulz-14x14-evk.dts | 22 ++++++++++++++ board/freescale/mx6ullevk/MAINTAINERS | 1 + board/freescale/mx6ullevk/mx6ullevk.c | 10 ++++-- configs/mx6ulz_14x14_evk_defconfig | 44 +++++++++++++++++++++++++++ include/configs/mx6ullevk.h | 13 +++++++- 5 files changed, 87 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx6ulz-14x14-evk.dts create mode 100644 configs/mx6ulz_14x14_evk_defconfig diff --git a/arch/arm/dts/imx6ulz-14x14-evk.dts b/arch/arm/dts/imx6ulz-14x14-evk.dts new file mode 100644 index 00000000000..483d9732c00 --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2018 NXP. + +/dts-v1/; + +#include "imx6ulz.dtsi" +#include "imx6ul-14x14-evk.dtsi" + +/delete-node/ &fec1; +/delete-node/ &fec2; +/delete-node/ &can1; +/delete-node/ &can2; +/delete-node/ &lcdif; +/delete-node/ &tsc; + +/ { + model = "Freescale i.MX6 ULZ 14x14 EVK Board"; + compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; + + /delete-node/ panel; +}; diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS index 73031cd121e..3d1b2560363 100644 --- a/board/freescale/mx6ullevk/MAINTAINERS +++ b/board/freescale/mx6ullevk/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/mx6ullevk/ F: include/configs/mx6ullevk.h F: configs/mx6ull_14x14_evk_defconfig F: configs/mx6ull_14x14_evk_plugin_defconfig +F: configs/mx6ulz_14x14_evk_defconfig diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index e1193478026..20ae011ecac 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -84,7 +84,10 @@ int board_late_init(void) #endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "EVK"); + if (is_cpu_type(MXC_CPU_MX6ULZ)) + env_set("board_name", "ULZ-EVK"); + else + env_set("board_name", "EVK"); env_set("board_rev", "14X14"); #endif @@ -93,7 +96,10 @@ int board_late_init(void) int checkboard(void) { - puts("Board: MX6ULL 14x14 EVK\n"); + if (is_cpu_type(MXC_CPU_MX6ULZ)) + puts("Board: MX6ULZ 14x14 EVK\n"); + else + puts("Board: MX6ULL 14x14 EVK\n"); return 0; } diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig new file mode 100644 index 00000000000..f647d72c6ee --- /dev/null +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 1fc5c24decd..f5f3de6cd46 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -55,7 +55,7 @@ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6ull-14x14-evk.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -87,6 +87,16 @@ "else " \ "bootz; " \ "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ @@ -113,6 +123,7 @@ "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ From 8a6e1b1dda2a95cc0b675b704faf2188681e363a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 1 Aug 2019 06:02:41 +0000 Subject: [PATCH 006/190] imx: mx6ul_14x14_evk: Fix SPL boot When booting SPL on the board, met boot failure: " Trying to boot from MMC2 MMC Device 1 not found spl: could not find mmc device 1. error: -19 SPL: failed to boot from all boot devices " Let's register the two mmc controllers in SPL stage to avoid boot failure. Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam --- .../freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index ccbe4044786..32f3912751b 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -111,7 +111,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#ifndef CONFIG_SPL_BUILD static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -127,7 +126,6 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { /* RST_B */ MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -#endif /* * mx6ul_14x14_evk board default supports sd card. If want to use @@ -238,19 +236,6 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { -#ifdef CONFIG_SPL_BUILD -#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) - imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, - ARRAY_SIZE(usdhc2_emmc_pads)); -#else - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); -#endif - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); -#else int i, ret; /* @@ -297,7 +282,6 @@ int board_mmc_init(bd_t *bis) return ret; } } -#endif return 0; } #endif From ae0760584b386230c2c7a0fc0b29fee2627bda14 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 1 Aug 2019 06:02:49 +0000 Subject: [PATCH 007/190] imx: mx6ul_14x14_evk: convert to DM_VIDEO To support DM_VIDEO, Add display node for lcdif Drop board iomuxc settings. Enable DM_VIDEO Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin --- arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi | 49 +++++++++++++++- .../mx6ul_14x14_evk/mx6ul_14x14_evk.c | 57 +++++++------------ configs/mx6ul_14x14_evk_defconfig | 2 +- configs/mx6ul_9x9_evk_defconfig | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- 5 files changed, 71 insertions(+), 41 deletions(-) diff --git a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi index 77cb461a215..e9efdb98315 100644 --- a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi @@ -3,8 +3,55 @@ * Copyright 2018 NXP */ +&{/aliases} { + u-boot,dm-pre-reloc; + display0 = &lcdif; +}; + &qspi { flash0: n25q256a@0 { compatible = "jedec,spi-nor"; }; -}; \ No newline at end of file +}; + +&{/soc} { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&lcdif { + display = <&display0>; + u-boot,dm-pre-reloc; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 32f3912751b..8e5f365d35e 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -28,6 +28,10 @@ #include "../common/pfuze.h" #include #include +#ifdef CONFIG_DM_VIDEO +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -421,40 +425,8 @@ int board_phy_config(struct phy_device *phydev) } #endif -#ifdef CONFIG_VIDEO_MXS +#ifdef CONFIG_DM_VIDEO static iomux_v3_cfg_t const lcd_pads[] = { - MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), - - /* LCD_RST */ - MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* Use GPIO for Brightness adjustment, duty cycle = period. */ MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -505,10 +477,6 @@ int board_init(void) board_qspi_init(); #endif -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); -#endif - return 0; } @@ -537,6 +505,21 @@ int board_late_init(void) env_set("board_rev", "14X14"); #endif +#if defined(CONFIG_DM_VIDEO) + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; + + setup_lcd(); + + ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, 0, 0, true); + if (ret) + return ret; +#endif + return 0; } diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index dacc29421d1..a458d90a34b 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -67,4 +67,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index b9fb2ec1d02..81f9b5b7145 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -70,4 +70,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 42e511591c6..f8a5fd30f32 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -196,7 +196,7 @@ #define CONFIG_IMX_THERMAL #ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_VIDEO +#if defined(CONFIG_DM_VIDEO) #define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO #define CONFIG_SPLASH_SCREEN From bdcac955657b46d78f375f74bf5e7e9b29f726c2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 31 Jul 2019 08:30:02 +0000 Subject: [PATCH 008/190] imx: mx6slevk: enable DM_SPI and DM_SPI_FLASH With DM_SPI and DM_SPI_FLASH enabled, we could get: spi 0 [ ] mxc_spi | | | `-- ecspi@02008000 spi_flash 0 [ ] spi_flash_std | | | `-- m25p80@0 Signed-off-by: Peng Fan --- board/freescale/mx6slevk/mx6slevk.c | 28 ---------------------------- configs/mx6slevk_defconfig | 2 ++ configs/mx6slevk_spinor_defconfig | 2 ++ configs/mx6slevk_spl_defconfig | 2 ++ 4 files changed, 6 insertions(+), 28 deletions(-) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 4c486790370..33ae91c3074 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -41,9 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ @@ -120,25 +116,6 @@ static iomux_v3_cfg_t const fec_pads[] = { MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -#ifdef CONFIG_MXC_SPI -static iomux_v3_cfg_t ecspi1_pads[] = { - MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; -} - -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -} -#endif - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -232,11 +209,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_MXC_SPI - gpio_request(IMX_GPIO_NR(4, 11), "spi_cs"); - setup_spi(); -#endif - #ifdef CONFIG_FEC_MXC setup_fec(); #endif diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index e614ef29ea7..6a7fa13f464 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -35,6 +35,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 @@ -50,6 +51,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 6ade0ef1422..b4812ffaed1 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -35,6 +35,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 @@ -50,6 +51,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 22bd5c3ba98..46a5d2c3866 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 @@ -59,6 +60,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y From 39ebb4187db15641117228f2579ff421cfe0df90 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Aug 2019 10:05:48 +0000 Subject: [PATCH 009/190] pinctrl: imx: use devfdt_get_addr_size_index fdtdec_get_addr_size could not parse addr/size correctly is using address-cells 2 and size-cells 2 on an ARM32 SoC. So switch to use devfdt_get_addr_size_index. Signed-off-by: Peng Fan --- drivers/pinctrl/nxp/pinctrl-imx.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 0c9d15cb0c9..69c41443655 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -214,9 +214,7 @@ int imx_pinctrl_probe(struct udevice *dev, if (info->flags & IMX8_USE_SCU) return 0; - addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg", - &size); - + addr = devfdt_get_addr_size_index(dev, 0, &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; From 4d655bfe03a35a2f85b2b779342b135c54d055a0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Aug 2019 10:07:26 +0000 Subject: [PATCH 010/190] tools: imx8mimage: fix HDMI/FIT parsing Add missed break for HDMI entry. And moving FIT parsing earlier, because it does not have parameter, it will not runs into CFG_REG_SIZE. Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Lukasz Majewski --- tools/imx8mimage.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 50a256cbac5..6c023376984 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -99,8 +99,6 @@ static void parse_cfg_cmd(int32_t cmd, char *token, char *name, int lineno) break; case CMD_SIGNED_HDMI: signed_hdmi = token; - case CMD_FIT: - using_fit = 1; break; case CMD_DDR_FW: /* Do nothing */ @@ -120,6 +118,11 @@ static void parse_cfg_fld(int32_t *cmd, char *token, name, lineno, token); exit(EXIT_FAILURE); } + switch (*cmd) { + case CMD_FIT: + using_fit = 1; + break; + } break; case CFG_REG_SIZE: parse_cfg_cmd(*cmd, token, name, lineno); From 8c247bbe23ca5e81d237bd7fefaa9ed7d1b1e232 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 7 Aug 2019 06:49:39 +0000 Subject: [PATCH 011/190] serial: Kconfig: make MXC_UART usable for MX7 and IMX8M i.MX7 and i.MX8M use mxc uart driver, so let's make the SoC could use MXC_UART kconfig. Signed-off-by: Peng Fan Reviewed-by: Ye Li --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ae2d819ba95..d36a0108ea9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -569,7 +569,7 @@ config MCFUART config MXC_UART bool "IMX serial port support" - depends on MX5 || MX6 + depends on MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. From cda789a5b1c049bfc3592dfbba19d261c2c0c6c4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 7 Aug 2019 06:40:53 +0000 Subject: [PATCH 012/190] spl: pass args to board_return_to_bootrom Pass spl_image and bootdev to board_return_bootrom. i.MX8MN needs the args to let ROM to load images Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Signed-off-by: Peng Fan Reviewed-by: Kever Yang --- arch/arm/cpu/arm926ejs/spear/spl.c | 5 ++++- arch/arm/mach-rockchip/spl.c | 5 ++++- arch/arm/mach-rockchip/tpl.c | 5 ++++- common/spl/spl_bootrom.c | 7 ++++--- include/spl.h | 3 ++- 5 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c index fc332fb6269..a919a455eb0 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl.c +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -277,7 +277,8 @@ void board_init_f(ulong dummy) * BootROM code right after having initialized a few components like the DRAM). * The following function is called from SPL common code (board_init_r). */ -void board_return_to_bootrom(void) +int board_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { /* * Retrieve the BootROM's stack pointer and jump back to the start of @@ -294,4 +295,6 @@ void board_return_to_bootrom(void) "bl back_to_bootrom;" #endif ); + + return 0; } diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 33137cc5ef4..92102b39e7d 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -14,9 +14,12 @@ DECLARE_GLOBAL_DATA_PTR; -void board_return_to_bootrom(void) +int board_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { back_to_bootrom(BROM_BOOT_NEXTSTAGE); + + return 0; } __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 55f6e922d0a..c3734cb0708 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -77,9 +77,12 @@ void board_init_f(ulong dummy) } } -void board_return_to_bootrom(void) +int board_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { back_to_bootrom(BROM_BOOT_NEXTSTAGE); + + return 0; } u32 spl_boot_device(void) diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c index 076f5d8d935..0eefd39a519 100644 --- a/common/spl/spl_bootrom.c +++ b/common/spl/spl_bootrom.c @@ -6,8 +6,10 @@ #include #include -__weak void board_return_to_bootrom(void) +__weak int board_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { + return 0; } static int spl_return_to_bootrom(struct spl_image_info *spl_image, @@ -19,8 +21,7 @@ static int spl_return_to_bootrom(struct spl_image_info *spl_image, * the ROM), it will implement board_return_to_bootrom() and * should not return from it. */ - board_return_to_bootrom(); - return false; + return board_return_to_bootrom(spl_image, bootdev); } SPL_LOAD_IMAGE_METHOD("BOOTROM", 0, BOOT_DEVICE_BOOTROM, spl_return_to_bootrom); diff --git a/include/spl.h b/include/spl.h index e4640f3830b..fd4747b44e4 100644 --- a/include/spl.h +++ b/include/spl.h @@ -387,7 +387,8 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image); * stage wants to return to the ROM code to continue booting, boards * can implement 'board_return_to_bootrom'. */ -void board_return_to_bootrom(void); +int board_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev); /** * board_spl_fit_post_load - allow process images after loading finished From ab1c482440ef33f34d7a4d7a14fe5e99a3704e42 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 24 Jul 2019 08:53:08 +0000 Subject: [PATCH 013/190] arm: dts: imx: fsl-imx8qm.dtsi: add gpio aliases to fix gpio command The gpio command currently uses equal bank names "GPIO0_" for all existing gpio banks, i. e.: U-Boot# gpio status -a Bank GPIO0_: GPIO0_0: input: 0 [ ] GPIO0_1: input: 0 [ ] ... Bank GPIO0_: GPIO0_0: input: 0 [ ] GPIO0_1: input: 0 [ ] ... So the command is broken, it is not possible to address a desired bank. Add gpio aliases to fix this. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin --- arch/arm/dts/fsl-imx8qm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index af060db3a12..6808f68f9d4 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -21,6 +21,13 @@ aliases { ethernet0 = &fec1; ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; serial0 = &lpuart0; serial1 = &lpuart1; serial2 = &lpuart2; From 6f8ef051c5dde7b6daeaf1a542c266d608fac783 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Mon, 2 Sep 2019 18:23:27 -0300 Subject: [PATCH 014/190] apalis_imx6: add board_fit_config_name_match to support FIT in SPL Only one dtb is currently supported, so match with imx6-apalis. Signed-off-by: Ricardo Salveti Reviewed-by: Peng Fan Acked-by: Max Krummenacher --- board/toradex/apalis_imx6/apalis_imx6.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 6421a22c25a..496f76b7f51 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -1116,6 +1116,16 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, "imx6-apalis")) + return 0; + + return -1; +} +#endif + void reset_cpu(ulong addr) { } From 536c564b915a66ba063fcb2511a2498bbddb412f Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Mon, 2 Sep 2019 18:12:02 -0300 Subject: [PATCH 015/190] apalis_imx6: fix broken fsl_esdhc_imx conversion Commit e37ac717d796 ("Convert to use fsl_esdhc_imx for i.MX platforms") converted FSL_ESDHC to FSL_ESDHC_IMX, but the config check for apalis_imx6 wasn't updated accordantly. Signed-off-by: Ricardo Salveti Reviewed-by: Peng Fan Acked-by: Max Krummenacher --- board/toradex/apalis_imx6/apalis_imx6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 496f76b7f51..51505b63e16 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -88,7 +88,7 @@ iomux_v3_cfg_t const uart1_pads_dte[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* Apalis MMC1 */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -285,7 +285,7 @@ int board_ehci_hcd_init(int port) } #endif -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* use the following sequence: eMMC, MMC1, SD1 */ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, From a3f5c7950713be28f6d4b5395079028778dd0204 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Mon, 2 Sep 2019 18:26:15 -0300 Subject: [PATCH 016/190] imx: apalis_imx6: select MX6Q via Kconfig Toradex Apalis iMX6 modules are available in the iMX6D and iMX6Q variants, which are quite similar and already managed via only one dtb in u-boot (imx6-apalis.dtb). Select MX6Q via Kconfig by default in order to automatically enable the HAS_CAAM and MX6_SMP features. Signed-off-by: Ricardo Salveti Reviewed-by: Peng Fan Acked-by: Max Krummenacher --- arch/arm/mach-imx/mx6/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index fe5991e7c6d..43d681113db 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -108,6 +108,7 @@ config TARGET_ADVANTECH_DMS_BA16 config TARGET_APALIS_IMX6 bool "Toradex Apalis iMX6 board" select BOARD_LATE_INIT + select MX6Q select DM select DM_SERIAL select DM_THERMAL From 01fc7e7b879189b4ccb07fe616189ce171f38516 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Mon, 2 Sep 2019 18:18:52 -0300 Subject: [PATCH 017/190] spl: imx: only use HAB if spl fit signature is not enabled There is no need to use HAB for FIT signature validation when SPL_FIT_SIGNATURE is also enabled, as that will be validated via the normal U-Boot signed FIT image flow. This allows having SPL validated by HAB and the payloads to follow being validated with FIT signatures only. Signed-off-by: Ricardo Salveti Reviewed-by: Peng Fan --- arch/arm/mach-imx/spl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 1f230aca339..a98fab8f1ce 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -261,6 +261,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) } } +#if !defined(CONFIG_SPL_FIT_SIGNATURE) ulong board_spl_fit_size_align(ulong size) { /* @@ -285,6 +286,7 @@ void board_spl_fit_post_load(ulong load_addr, size_t length) hang(); } } +#endif #endif From 06f5b5a5fc9784e395b401c7ab61dffe04b1a4f9 Mon Sep 17 00:00:00 2001 From: Robert Hancock Date: Thu, 8 Aug 2019 12:14:39 -0600 Subject: [PATCH 018/190] ARM: imx: Support larger SPL size on IMX6DQ Previously the SPL size on all iMX6 platforms was restricted to 68KB because the OCRAM size on iMX6SL/DL parts is only 128KB. However, the other iMX6 variants have 256KB of OCRAM. Add an option CONFIG_MX6_OCRAM_256KB which allows using the full size on boards which don't need to support the SL/DL variants. This allows for an SPL size of 196KB, which makes it much easier to use configurations such as SPL with driver model and FDT control. Signed-off-by: Robert Hancock Tested-by: Adam Ford #imx6q_logic --- arch/arm/mach-imx/mx6/Kconfig | 9 +++++++++ common/spl/Kconfig | 3 ++- include/configs/imx6_spl.h | 28 ++++++++++++++++++++++++++-- 3 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 43d681113db..36e1c98fb59 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -87,6 +87,15 @@ config MX6ULL select SYSCOUNTER_TIMER select SYS_L2CACHE_OFF +config MX6_OCRAM_256KB + bool "Support 256KB OCRAM" + depends on MX6D || MX6Q + help + Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series + of chips, such as for SPL. The OCRAM of the Lite series of chips is + only 128KB, so using this option will prevent the resulting code from + working on those chips. + config MX6_DDRCAL bool "Include dynamic DDR calibration routines" depends on SPL diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f467eca2be7..2ca219995dd 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -28,7 +28,8 @@ config SPL_FRAMEWORK config SPL_SIZE_LIMIT int "Maximum size of SPL image" depends on SPL - default 69632 if ARCH_MX6 + default 69632 if ARCH_MX6 && !MX6_OCRAM_256KB + default 200704 if ARCH_MX6 && MX6_OCRAM_256KB default 0 help Specifies the maximum length of the U-Boot SPL image. diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 212dee7f28c..a223930240c 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -7,10 +7,32 @@ #define __IMX6_SPL_CONFIG_H #ifdef CONFIG_SPL + +#ifdef CONFIG_MX6_OCRAM_256KB /* - * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: + * see Figure 8.4.1 in IMX6DQ Reference manuals: + * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF + * - BOOT ROM stack is at 0x0093FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to + * fit between 0x00907000 and 0x00938000. + * - Additionally the BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00908000 - 0x00938000 + * or 192KB + */ +#define CONFIG_SPL_MAX_SIZE 0x30000 +#define CONFIG_SPL_STACK 0x0093FFB8 +/* + * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x31000 +#else +/* + * see Figure 8-3 in IMX6SDL Reference manuals: * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF - * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well * - BOOT ROM stack is at 0x0091FFB8 * - if icache/dcache is enabled (eFuse/strapping controlled) then the * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to @@ -29,6 +51,8 @@ */ #define CONFIG_SPL_PAD_TO 0x11000 +#endif + /* MMC support */ #if defined(CONFIG_SPL_MMC_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 From f8f9f79a63be3db5e0cfcfe29241a14f50d4f4c3 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 29 Jul 2019 12:15:54 -0700 Subject: [PATCH 019/190] nitrogen6x: migrate to using device tree Migrate to using device tree required for further driver model integration. Signed-off-by: Troy Kisky --- arch/arm/dts/Makefile | 27 +- arch/arm/dts/imx6dl-nitrogen6x.dts | 15 + arch/arm/dts/imx6q-nitrogen6x.dts | 19 ++ arch/arm/dts/imx6q-sabrelite.dts | 19 ++ arch/arm/dts/imx6qdl-nitrogen6x.dtsi | 69 +++++ arch/arm/dts/imx6qdl-sabrelite.dtsi | 384 ++++++++++++++++++++++++++ board/boundary/nitrogen6x/MAINTAINERS | 5 + configs/mx6qsabrelite_defconfig | 3 +- configs/nitrogen6dl2g_defconfig | 3 +- configs/nitrogen6dl_defconfig | 3 +- configs/nitrogen6q2g_defconfig | 3 +- configs/nitrogen6q_defconfig | 3 +- configs/nitrogen6s1g_defconfig | 3 +- configs/nitrogen6s_defconfig | 3 +- 14 files changed, 543 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/imx6dl-nitrogen6x.dts create mode 100644 arch/arm/dts/imx6q-nitrogen6x.dts create mode 100644 arch/arm/dts/imx6q-sabrelite.dts create mode 100644 arch/arm/dts/imx6qdl-nitrogen6x.dtsi create mode 100644 arch/arm/dts/imx6qdl-sabrelite.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8170c39e07e..90e877322be 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -552,33 +552,42 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ imx53-kp.dtb \ imx53-m53menlo.dtb -dtb-$(CONFIG_MX6Q) += \ - imx6-apalis.dtb \ - imx6q-display5.dtb \ - imx6q-logicpd.dtb \ - imx6q-novena.dtb \ - imx6q-tbs2910.dtb - -dtb-$(CONFIG_MX6QDL) += \ +ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) +dtb-y += \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ imx6dl-mamoj.dtb \ + imx6dl-nitrogen6x.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ imx6dl-wandboard-revb1.dtb \ + +endif + +ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),) +dtb-y += \ + imx6-apalis.dtb \ imx6q-cm-fx6.dtb \ imx6q-dhcom-pdk2.dtb \ + imx6q-display5.dtb \ imx6q-icore.dtb \ imx6q-icore-mipi.dtb \ imx6q-icore-rqs.dtb \ + imx6q-logicpd.dtb \ + imx6q-nitrogen6x.dtb \ + imx6q-novena.dtb \ imx6q-sabreauto.dtb \ + imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ + imx6q-tbs2910.dtb \ imx6q-wandboard-revb1.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ - imx6qp-wandboard-revd1.dtb + imx6qp-wandboard-revd1.dtb \ + +endif dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb diff --git a/arch/arm/dts/imx6dl-nitrogen6x.dts b/arch/arm/dts/imx6dl-nitrogen6x.dts new file mode 100644 index 00000000000..9427ab6399b --- /dev/null +++ b/arch/arm/dts/imx6dl-nitrogen6x.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013-2019 Boundary Devices, Inc. +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board"; + compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-nitrogen6x.dts b/arch/arm/dts/imx6q-nitrogen6x.dts new file mode 100644 index 00000000000..ebb22a404ef --- /dev/null +++ b/arch/arm/dts/imx6q-nitrogen6x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013-2019 Boundary Devices, Inc. +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Nitrogen6x Board"; + compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-sabrelite.dts b/arch/arm/dts/imx6q-sabrelite.dts new file mode 100644 index 00000000000..91e031c7ca8 --- /dev/null +++ b/arch/arm/dts/imx6q-sabrelite.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013-2019 Boundary Devices, Inc. +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sabrelite.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Lite Board"; + compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi new file mode 100644 index 00000000000..5094929b6d5 --- /dev/null +++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013-2019 Boundary Devices, Inc. +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include "imx6qdl-sabrelite.dtsi" + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#undef GP_ENET_PHY_RESET +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Spare */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; +}; + +&fec { +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc3 { + /delete-property/ wp-gpios; +}; diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi b/arch/arm/dts/imx6qdl-sabrelite.dtsi new file mode 100644 index 00000000000..673a19c3df4 --- /dev/null +++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013-2019 Boundary Devices, Inc. +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include +#include +#include + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 +#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#undef GP_ENET_PHY_RESET +#define GP_ENET_PHY_RESET <&gpio3 23 GPIO_ACTIVE_LOW> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Spare */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1: i2c1-1grp { + fsl,pins = < +#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 +#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1: i2c2-1grp { + fsl,pins = < +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 +#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING> +#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3_1: i2c3-1grp { + fsl,pins = < +#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 +#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW> + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 +#define GP_USDHC3_WP <&gpio7 1 GPIO_ACTIVE_HIGH> + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + >; + }; +}; + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc4; + pwm_lcd = &pwm1; + pwm_lvds = &pwm4; + }; + + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USBOTG; + enable-active-high; + }; +}; + +&ecspi1 { + cs-gpios = GP_ECSPI1_NOR_CS; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + mtd@00000000 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + }; + + mtd@000C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + }; + mtd@000C2000 { + label = "splash"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + phy-handle = <ðphy>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + status = "okay"; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + + mdio { + #address-cells = <0>; + #size-cells = <1>; + + ethphy: ethernet-phy { + interrupts-extended = GPIRQ_ENET_PHY; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + scl-gpios = GP_I2C1_SCL; + sda-gpios = GP_I2C1_SDA; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_1>; + scl-gpios = GP_I2C2_SCL; + sda-gpios = GP_I2C2_SDA; + status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_1>; + scl-gpios = GP_I2C3_SCL; + sda-gpios = GP_I2C3_SDA; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + reset-gpios = GP_USBH1_HUB_RESET; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = GP_USDHC3_CD; + wp-gpios = GP_USDHC3_WP; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = GP_USDHC4_CD; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/board/boundary/nitrogen6x/MAINTAINERS b/board/boundary/nitrogen6x/MAINTAINERS index 1602d650e3c..17018d69f64 100644 --- a/board/boundary/nitrogen6x/MAINTAINERS +++ b/board/boundary/nitrogen6x/MAINTAINERS @@ -1,6 +1,11 @@ NITROGEN6X BOARD M: Troy Kisky S: Maintained +F: arch/arm/dts/imx6dl-nitrogen6x.dts +F: arch/arm/dts/imx6q-nitrogen6x.dts +F: arch/arm/dts/imx6q-sabrelite.dts +F: arch/arm/dts/imx6qdl-nitrogen6x.dtsi +F: arch/arm/dts/imx6qdl-sabrelite.dtsi F: board/boundary/nitrogen6x/ F: include/configs/nitrogen6x.h F: configs/mx6qsabrelite_defconfig diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 379407ab438..fe954ecdeb6 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -30,6 +30,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabrelite" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_DWC_AHSATA=y @@ -60,4 +62,3 @@ CONFIG_USB_ETH_CDC=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 11bee9b5508..015336fd3bf 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 @@ -62,4 +64,3 @@ CONFIG_USB_ETH_CDC=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 141289f1742..d7c6e7cfc6d 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 @@ -62,4 +64,3 @@ CONFIG_USB_ETH_CDC=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 841418350b9..782222e3cfe 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -64,4 +66,3 @@ CONFIG_USB_ETH_CDC=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index e0af34c8a75..17521841491 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -64,4 +66,3 @@ CONFIG_USB_ETH_CDC=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 53eb96a986d..10d9c095869 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 @@ -62,4 +64,3 @@ CONFIG_USB_ETH_CDC=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index e60c2378578..c297286bd4e 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 @@ -62,4 +64,3 @@ CONFIG_USB_ETH_CDC=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y From cdcaee95188fe8ca75e9701680ce14129c193de0 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 29 Jul 2019 12:15:55 -0700 Subject: [PATCH 020/190] configs: nitrogen6x: Add DM_MMC/DM_USB/AHCI support Add DM_MMC to all defconfigs whose board is nitrogen6x. mx6qsabrelite_defconfig nitrogen6dl2g_defconfig nitrogen6dl_defconfig nitrogen6q2g_defconfig nitrogen6q_defconfig nitrogen6s1g_defconfig This commit is adding multiple configs, but seems to be the minimum change to not lose features and still compile fine. Signed-off-by: Troy Kisky --- configs/mx6qsabrelite_defconfig | 4 ++++ configs/nitrogen6dl2g_defconfig | 5 +++++ configs/nitrogen6dl_defconfig | 5 +++++ configs/nitrogen6q2g_defconfig | 5 +++++ configs/nitrogen6q_defconfig | 5 +++++ configs/nitrogen6s1g_defconfig | 5 +++++ configs/nitrogen6s_defconfig | 5 +++++ 7 files changed, 34 insertions(+) diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index fe954ecdeb6..5a837282312 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -4,7 +4,9 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_NITROGEN6X=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set @@ -38,6 +40,7 @@ CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -50,6 +53,7 @@ CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 015336fd3bf..b1df37fb89d 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_NITROGEN6X=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -37,9 +39,11 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -51,6 +55,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index d7c6e7cfc6d..a7ce9d3cf0f 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_NITROGEN6X=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -37,9 +39,11 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -51,6 +55,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 782222e3cfe..3f8aac56ca9 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_NITROGEN6X=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -38,10 +40,12 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -53,6 +57,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 17521841491..0e06e0fddeb 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_NITROGEN6X=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -38,10 +40,12 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -53,6 +57,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 10d9c095869..8ad9cc5796c 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_NITROGEN6X=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -37,9 +39,11 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -51,6 +55,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index c297286bd4e..5b80306b94a 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_NITROGEN6X=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -37,9 +39,11 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -51,6 +55,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y From 1b51e5f4cd2a62673a5391a5e8d47a03daf1c12d Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 29 Jul 2019 12:15:56 -0700 Subject: [PATCH 021/190] nitrogen6x: reserve used gpios This prevents messages like gpio@20a0000: get_value: error: gpio GPIO2_2 not reserved when CONFIG_DM_GPIO is enabled. Also, when CONFIG_DM_GPIO is enabled, checkboard is too early to use gpio_get_value, so read it directly on failure. Signed-off-by: Troy Kisky --- board/boundary/nitrogen6x/nitrogen6x.c | 30 +++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 26af3f71025..33653b59495 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -382,6 +382,15 @@ int board_eth_init(bd_t *bis) struct phy_device *phydev = NULL; int ret; + gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq"); + gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc"); + gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0"); + gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1"); + gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2"); + gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3"); + gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl"); + gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite"); + gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x"); setup_iomux_enet(); #ifdef CONFIG_FEC_MXC @@ -912,7 +921,16 @@ int board_init(void) int checkboard(void) { - if (gpio_get_value(WL12XX_WL_IRQ_GP)) + int ret = gpio_get_value(WL12XX_WL_IRQ_GP); + + if (ret < 0) { + /* The gpios have not been probed yet. Read it myself */ + struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR; + int gpio = WL12XX_WL_IRQ_GP & 0x1f; + + ret = (readl(®s->gpio_psr) >> gpio) & 0x01; + } + if (ret) puts("Board: Nitrogen6X\n"); else puts("Board: SABRE Lite\n"); @@ -1014,6 +1032,16 @@ static const struct boot_mode board_boot_modes[] = { int misc_init_r(void) { + gpio_request(RGB_BACKLIGHT_GP, "lvds backlight"); + gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight"); + gpio_request(GP_USB_OTG_PWR, "usbotg power"); + gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset"); + gpio_request(IMX_GPIO_NR(2, 2), "back"); + gpio_request(IMX_GPIO_NR(2, 4), "home"); + gpio_request(IMX_GPIO_NR(2, 1), "menu"); + gpio_request(IMX_GPIO_NR(2, 3), "search"); + gpio_request(IMX_GPIO_NR(7, 13), "volup"); + gpio_request(IMX_GPIO_NR(4, 5), "voldown"); #ifdef CONFIG_PREBOOT preboot_keys(); #endif From 684efe2f480d29c2f7f475fe83ab5b405bce7242 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 29 Jul 2019 12:15:57 -0700 Subject: [PATCH 022/190] configs: nitrogen6x: Add DM_GPIO support Add CONFIG_DM_GPIO to all defconfigs whose board is nitrogen6x. mx6qsabrelite_defconfig nitrogen6dl2g_defconfig nitrogen6dl_defconfig nitrogen6q2g_defconfig nitrogen6q_defconfig nitrogen6s1g_defconfig This is in preparation for adding CONFIG_DM_SPI. Signed-off-by: Troy Kisky --- configs/mx6qsabrelite_defconfig | 1 + configs/nitrogen6dl2g_defconfig | 1 + configs/nitrogen6dl_defconfig | 1 + configs/nitrogen6q2g_defconfig | 1 + configs/nitrogen6q_defconfig | 1 + configs/nitrogen6s1g_defconfig | 1 + configs/nitrogen6s_defconfig | 1 + 7 files changed, 7 insertions(+) diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 5a837282312..41f8e1df61d 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -40,6 +40,7 @@ CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index b1df37fb89d..dd316c5b33e 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -43,6 +43,7 @@ CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index a7ce9d3cf0f..527735ebb8b 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -43,6 +43,7 @@ CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 3f8aac56ca9..351bbeb1711 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -45,6 +45,7 @@ CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 0e06e0fddeb..fca5dac8c9b 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -45,6 +45,7 @@ CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 8ad9cc5796c..f5b1669cb29 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -43,6 +43,7 @@ CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 5b80306b94a..b40d0fe204c 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -43,6 +43,7 @@ CONFIG_DM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y +CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 From b1f955cb4d5ba10e422e08d1d7577be71a39ac00 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 29 Jul 2019 12:15:58 -0700 Subject: [PATCH 023/190] configs: nitrogen6x: Add DM_SPI/DM_SPI_FLASH support Add CONFIG_DM_SPI/CONFIG_DM_SPI_FLASH to all defconfigs whose board is nitrogen6x. mx6qsabrelite_defconfig nitrogen6dl2g_defconfig nitrogen6dl_defconfig nitrogen6q2g_defconfig nitrogen6q_defconfig nitrogen6s1g_defconfig Signed-off-by: Troy Kisky --- configs/mx6qsabrelite_defconfig | 2 ++ configs/nitrogen6dl2g_defconfig | 2 ++ configs/nitrogen6dl_defconfig | 2 ++ configs/nitrogen6q2g_defconfig | 2 ++ configs/nitrogen6q_defconfig | 2 ++ configs/nitrogen6s1g_defconfig | 2 ++ configs/nitrogen6s_defconfig | 2 ++ 7 files changed, 14 insertions(+) diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 41f8e1df61d..e4a7441fbe9 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -42,6 +42,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -51,6 +52,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index dd316c5b33e..32bd4eedaff 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -54,6 +55,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 527735ebb8b..34166e557ab 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -54,6 +55,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 351bbeb1711..2c4def6fce9 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -47,6 +47,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -56,6 +57,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index fca5dac8c9b..a4ca672d135 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -47,6 +47,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -56,6 +57,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index f5b1669cb29..ff8d2affbe6 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -54,6 +55,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index b40d0fe204c..f5623cbb5df 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FSL_USDHC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -54,6 +55,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y From e92fca66a3966c54d86977539fabe57596b62d76 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Jul 2019 01:24:37 +0000 Subject: [PATCH 024/190] imx: i.MX7ULP: add get_boot_device Add get_boot_device for i.MX7ULP Signed-off-by: Peng Fan Tested-by: Fabio Estevam --- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 13 ++++++++++ arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 + arch/arm/mach-imx/mx7ulp/soc.c | 27 ++++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 63b02de0878..d58ed43199e 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -10,6 +10,8 @@ #define ARCH_MXC +#define ROM_SW_INFO_ADDR 0x000001E8 + #define CAAM_SEC_SRAM_BASE (0x26000000) #define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) @@ -1112,6 +1114,17 @@ struct usbphy_regs { u32 usb1_pfda_ctrl1_tog; /* 0x14c */ }; +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 rom_tick_freq; + u32 reserved_3[3]; +}; #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h index 6ecde7db937..0e4c8ad15d3 100644 --- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -17,4 +17,5 @@ enum bt_mode { SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ }; +enum boot_device get_boot_device(void); #endif diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index c72f0ed3fc6..6015c11869d 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include static char *get_reset_cause(char *); @@ -244,3 +245,29 @@ int mmc_get_env_dev(void) return board_mmc_get_env_dev(devno); } #endif + +enum boot_device get_boot_device(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; + + enum boot_device boot_dev = SD1_BOOT; + u8 boot_type = (*p)->boot_dev_type; + u8 boot_instance = (*p)->boot_dev_instance; + + switch (boot_type) { + case BOOT_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BOOT_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BOOT_TYPE_USB: + boot_dev = USB_BOOT; + break; + default: + break; + } + + return boot_dev; +} From bd1cc6ae6f8a8f2c1c44263e3a89f853c237306e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Jul 2019 01:24:39 +0000 Subject: [PATCH 025/190] i.MX7ULP: evk: Modify FDT file to disable SD3.0 for usb boot Since the SD3.0 kernel driver needs M4 image support, this causes problem for usb boot booting into kernel. To decouple the relationship, we modify the FDT file in u-boot to disable SD3.0. So the kernel won't depend on M4 image. Signed-off-by: Peng Fan --- board/freescale/mx7ulp_evk/mx7ulp_evk.c | 47 +++++++++++++++++++++++++ configs/mx7ulp_evk_defconfig | 1 + 2 files changed, 48 insertions(+) diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 3a12fe15514..7527263577f 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -45,3 +47,48 @@ int board_init(void) return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + const char *path; + int rc, nodeoff; + + if (get_boot_device() == USB_BOOT) { + path = fdt_get_alias(blob, "mmc0"); + if (!path) { + puts("Not found mmc0\n"); + return 0; + } + + nodeoff = fdt_path_offset(blob, path); + if (nodeoff < 0) + return 0; + + printf("Found usdhc0 node\n"); + if (fdt_get_property(blob, nodeoff, "vqmmc-supply", + NULL) != NULL) { + rc = fdt_delprop(blob, nodeoff, "vqmmc-supply"); + if (!rc) { + puts("Removed vqmmc-supply property\n"); +add: + rc = fdt_setprop(blob, nodeoff, + "no-1-8-v", NULL, 0); + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 32); + if (!rc) + goto add; + } else if (rc) { + printf("Failed to add no-1-8-v property, %d\n", rc); + } else { + puts("Added no-1-8-v property\n"); + } + } else { + printf("Failed to remove vqmmc-supply property, %d\n", rc); + } + } + } + + return 0; +} +#endif diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index df854436a04..dc6cc2ba37a 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_TARGET_MX7ULP_EVK=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y From 7777406a8a023bdfe18d106138c61eeaa15dd5b4 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Mon, 22 Jul 2019 01:24:42 +0000 Subject: [PATCH 026/190] i.MX7ULP: Fix system reset after a7 rtc alarm expired. The board will reboot if A7 core enter mem mode by rtc, then M4 core enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode to fix this issue. Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access it. So check the CPU rev and not apply the settings for B0. Signed-off-by: Bai Ping Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 7 +++++++ arch/arm/mach-imx/mx7ulp/soc.c | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index d58ed43199e..3c82e9921ed 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -58,6 +58,7 @@ #define USDHC1_AIPS2_SLOT (56) #define RGPIO2P0_AIPS0_SLOT (15) #define RGPIO2P1_AIPS2_SLOT (15) +#define SNVS_AIPS2_SLOT (35) #define IOMUXC0_AIPS0_SLOT (61) #define OCOTP_CTRL_AIPS1_SLOT (38) #define OCOTP_CTRL_PCC1_SLOT (38) @@ -177,6 +178,9 @@ #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) +#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) +#define SNVS_LP_LPCR (SNVS_BASE + 0x38) + #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) @@ -939,6 +943,9 @@ #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) +#define SNVS_LPCR_DPEN (0x20) +#define SNVS_LPCR_SRTC_ENV (0x1) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 6015c11869d..7119ee4a077 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -106,6 +106,10 @@ void s_init(void) /* clock configuration. */ clock_init(); + if (soc_rev() < CHIP_REV_2_0) { + /* enable dumb pmic */ + writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR); + } return; } From 3ed6734e698e4280361f1a509856c50b07861c99 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Mon, 22 Jul 2019 01:24:45 +0000 Subject: [PATCH 027/190] i.MX7ULP: Correct the clock index On i.MX7ULP, value zero is reserved in SCG1 RCCR register, so the val should be decreased by 1 to get the correct clock source index. Signed-off-by: Bai Ping Signed-off-by: Peng Fan --- arch/arm/mach-imx/mx7ulp/scg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index b4f2ea875af..85d726fe30d 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -440,7 +440,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk) case SCG_SCS_SLOW_IRC: case SCG_SCS_FAST_IRC: case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); + rate = scg_src_get_rate(scg_scs_array[val - 1]); break; case 5: rate = scg_apll_get_rate(); From a0f4f7ee606296ac1090bd358696ee822b67d8cc Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 22 Jul 2019 01:24:47 +0000 Subject: [PATCH 028/190] i.MX7ULP: Fix PCC register bits mask and offset issue The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx7ulp/pcc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h index 67a09361506..dee3cfcdc00 100644 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -289,10 +289,10 @@ enum pcc3_entry { #define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) #define PCC_PCS_OFFSET 24 #define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) -#define PCC_FRAC_OFFSET 4 +#define PCC_FRAC_OFFSET 3 #define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) #define PCC_PCD_OFFSET 0 -#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET) +#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) enum pcc_clksrc_type { From 911d7d356ab0f3e9dae007f3a864e425d27be585 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 22 Jul 2019 01:24:50 +0000 Subject: [PATCH 029/190] i.MX7ULP: Add CONFIG_MX7ULP to kconfig Since many drivers need this CONFIG_MX7ULP to distiguish the settings for i.MX7ULP only. Add this entry to cpu's kconfig. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/mx7ulp/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index d4b0299dbd1..ed5f0aeb2d5 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -3,12 +3,16 @@ if ARCH_MX7ULP config SYS_SOC default "mx7ulp" +config MX7ULP + bool + choice prompt "MX7ULP board select" optional config TARGET_MX7ULP_EVK - bool "Support mx7ulp EVK board" + bool "Support mx7ulp EVK board" + select MX7ULP select SYS_ARCH_TIMER endchoice From 61bf6173cd65f8c937c40759c923ba52ca03374b Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 22 Jul 2019 01:24:53 +0000 Subject: [PATCH 030/190] i.MX7ULP: Fix wrong i2c configuration name Wrong I2c driver configuration name is used in codes, so I2c driver is not built. Correct it. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx7ulp/clock.h | 2 +- arch/arm/mach-imx/mx7ulp/clock.c | 2 +- configs/mx7ulp_evk_defconfig | 1 + configs/mx7ulp_evk_plugin_defconfig | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index bf697858315..eb02a20fdc5 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -26,7 +26,7 @@ enum mxc_clock { u32 mxc_get_clock(enum mxc_clock clk); u32 get_lpuart_clk(void); -#ifdef CONFIG_SYS_LPI2C_IMX +#ifdef CONFIG_SYS_I2C_IMX_LPI2C int enable_i2c_clk(unsigned char enable, unsigned i2c_num); u32 imx_get_i2cclk(unsigned i2c_num); #endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index dc317fe810a..e333c7815b4 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -72,7 +72,7 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); } -#ifdef CONFIG_SYS_LPI2C_IMX +#ifdef CONFIG_SYS_I2C_IMX_LPI2C int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { /* Set parent to FIRC DIV2 clock */ diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index dc6cc2ba37a..b92e0fa3932 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -21,6 +21,7 @@ CONFIG_DM_GPIO=y CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index b2451adce70..970c0c7dbd4 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -20,6 +20,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y From 994ab731b3723f2a2918cf7adf112a4acf6e4f9b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Jul 2019 01:24:55 +0000 Subject: [PATCH 031/190] misc: Kconfig: make i.MX7ULP could use MXC_OCOTP Signed-off-by: Peng Fan --- drivers/misc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 8037b6ee2d7..ba50893b432 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -202,7 +202,7 @@ config JZ4780_EFUSE config MXC_OCOTP bool "Enable MXC OCOTP Driver" - depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610 + depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 default y help If you say Y here, you will get support for the One Time From 3399a2e1d25be46725ebfd4b5aba66232467c32d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Jul 2019 01:24:57 +0000 Subject: [PATCH 032/190] i.MX7ULP: evk: Enable fuse comamnd Enable fuse command Signed-off-by: Peng Fan --- configs/mx7ulp_evk_defconfig | 1 + configs/mx7ulp_evk_plugin_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index b92e0fa3932..ffd217d5155 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -9,6 +9,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 970c0c7dbd4..12106aad54f 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y From eb6d2e5920fa518fc924025e1e7987cd0dde73ad Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 22 Jul 2019 01:25:00 +0000 Subject: [PATCH 033/190] i.MX7ULP: Fix SPLL/APLL clock rate calculation issue The num/denom is a float value, but in the calculation it is convert to integer 0, and cause the result wrong. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/mx7ulp/scg.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 85d726fe30d..a28a2bc81b8 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -503,7 +503,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_A7_APLL: reg = readl(&scg1_regs->apllcsr); @@ -532,7 +535,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_USB: reg = readl(&scg1_regs->upllcsr); From eae4e0f3c10967386382b848ef80d9f8852d67a1 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 22 Jul 2019 01:25:03 +0000 Subject: [PATCH 034/190] i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem. The correct fix should let GPU handle the clock rate in kernel. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/mx7ulp/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index e333c7815b4..7012157078e 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -300,9 +300,9 @@ void clock_init(void) scg_a7_soscdiv_init(); - /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ + /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); - scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20); + scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12); init_clk_lpuart(); From e25dc290aa85ea3b68000295e352681acfa53617 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Jul 2019 01:25:05 +0000 Subject: [PATCH 035/190] i.MX7ULP: Add CPU revision check for B0 Since there is no register for CPU revision, we use ROM version to check the A0 or B0 chip. Signed-off-by: Peng Fan --- arch/arm/mach-imx/mx7ulp/soc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 7119ee4a077..6c53aa106e7 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -18,10 +18,13 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = { }; #endif +#define ROM_VERSION_ADDR 0x80 u32 get_cpu_rev(void) { - /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ - return (MXC_CPU_MX7ULP << 12) | (1 << 4); + /* Check the ROM version for cpu revision */ + u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR); + + return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF); } #ifdef CONFIG_REVISION_TAG From df3572e93033d7620767ed6dc9790dceb110636c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 22 Jul 2019 01:25:08 +0000 Subject: [PATCH 036/190] i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chip The normal target frequency for ULP A7 core is 500Mhz, but now ROM set the core frequency to 413Mhz. So change it to 500Mhz in u-boot. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx7ulp/scg.h | 1 + arch/arm/mach-imx/mx7ulp/clock.c | 2 ++ arch/arm/mach-imx/mx7ulp/scg.c | 41 ++++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index f1fae010da0..531d8f3a950 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -337,5 +337,6 @@ void scg_a7_nicclk_init(void); void scg_a7_sys_clk_sel(enum scg_sys_src clk); void scg_a7_info(void); void scg_a7_soscdiv_init(void); +void scg_a7_init_core_clk(void); #endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 7012157078e..7bf83170eb9 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -300,6 +300,8 @@ void clock_init(void) scg_a7_soscdiv_init(); + scg_a7_init_core_clk(); + /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index a28a2bc81b8..0d31352c77b 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -1091,3 +1091,44 @@ void scg_a7_info(void) debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr)); debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr)); } + +void scg_a7_init_core_clk(void) +{ + u32 val = 0; + + /* + * The normal target frequency for ULP B0 is 500Mhz, + * but ROM set it to 413Mhz, need to change SPLL PFD0 FRAC + */ + if (soc_rev() >= CHIP_REV_2_0) { + /* Switch RCCR SCG to SOSC, firstly check the SOSC is valid */ + if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) { + val = readl(&scg1_regs->rccr); + val &= (~SCG_CCR_SCS_MASK); + val |= ((SCG_SCS_SYS_OSC) << SCG_CCR_SCS_SHIFT); + writel(val, &scg1_regs->rccr); + + /* Switch the PLLS to SPLL clk */ + val = readl(&scg1_regs->spllcfg); + val &= ~SCG_PLL_CFG_PLLSEL_MASK; + writel(val, &scg1_regs->spllcfg); + + /* + * Re-configure PFD0 to 19, + * A7 SPLL(528MHz) * 18 / 19 = 500MHz + */ + scg_enable_pll_pfd(SCG_SPLL_PFD0_CLK, 19); + + /* Switch the PLLS to SPLL PFD0 */ + val = readl(&scg1_regs->spllcfg); + val |= SCG_PLL_CFG_PLLSEL_MASK; + writel(val, &scg1_regs->spllcfg); + + /* Set RCCR SCG to SPLL clk out */ + val = readl(&scg1_regs->rccr); + val &= (~SCG_CCR_SCS_MASK); + val |= ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT); + writel(val, &scg1_regs->rccr); + } + } +} From 971a71e114d00ceee7b486d4599d3c26756109fb Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 22 Jul 2019 01:25:10 +0000 Subject: [PATCH 037/190] i.MX7ULP: Change clock rate calculation for NIC1 BUS and EXT On i.MX7ULP B0, there is change in NIC clock dividers architecture. On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but on B0 they are parallel with NIC1 DIV. So now the dividers are independent. This patch modifies the scg_nic_get_rate function according to this change. Signed-off-by: Ye Li Acked-by: Peng Fan --- arch/arm/mach-imx/mx7ulp/scg.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 0d31352c77b..819c90af6ce 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -352,7 +352,7 @@ static u32 scg_ddr_get_rate(void) static u32 scg_nic_get_rate(enum scg_clk clk) { - u32 reg, val, rate; + u32 reg, val, rate, nic0_rate; u32 shift, mask; reg = readl(&scg1_regs->niccsr); @@ -370,6 +370,7 @@ static u32 scg_nic_get_rate(enum scg_clk clk) val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT; rate = rate / (val + 1); + nic0_rate = rate; clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate); @@ -411,6 +412,13 @@ static u32 scg_nic_get_rate(enum scg_clk clk) return 0; } + /* + * On RevB, the nic_bus and nic_ext dividers are parallel + * not chained with nic div + */ + if (soc_rev() >= CHIP_REV_2_0) + rate = nic0_rate; + val = (reg & mask) >> shift; rate = rate / (val + 1); From 91457597e3c95450ac42cf45a4a5fe7da174fd20 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 Jul 2019 12:20:46 -0300 Subject: [PATCH 038/190] mx6sabresd: Reduce overall SPL size Currently the SPL binary is 67 kB, which leaves only 1 kB of free internal RAM space. The following options can be safely removed to save some precious SPL space: - CONFIG_SPL_FS_EXT4: u-boot-dtb.img is stored in raw sector via dd command (at offset 69 kB) - CONFIG_SPL_I2C_SUPPORT: I2C is not used during SPL - CONFIG_SPL_OS_BOOT: no need to make Falcon mode supported by default After this change the SPL binary size gets down to 51 kB. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- configs/mx6sabresd_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 73cb32e291a..b2c77ff4dab 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -23,9 +23,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FIT_IMAGE_TINY=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_OS_BOOT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y From 5f2fe3b93a2583c266c67ea10ce454fc02bbd94e Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Thu, 18 Jul 2019 12:34:08 +0000 Subject: [PATCH 039/190] Kconfig: Migrate CONFIG_CSF_SIZE to Kconfig Move CONFIG_CSF_SIZE to Kconfig and define default value as 0x4000. mx8mqevk requires 0x2000 add this configuration in imx8mq_evk_defconfig file. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/Kconfig | 7 +++++++ configs/imx8mq_evk_defconfig | 1 + include/configs/cl-som-imx7.h | 1 - include/configs/imx8mq_evk.h | 4 ---- include/configs/mx6_common.h | 4 ---- include/configs/mx6sllevk.h | 6 ------ include/configs/mx6ullevk.h | 6 ------ include/configs/mx7_common.h | 4 ---- include/configs/mx7ulp_evk.h | 6 ------ scripts/config_whitelist.txt | 1 - 10 files changed, 8 insertions(+), 32 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index aeb54934888..d44f74e4745 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -43,6 +43,13 @@ config SECURE_BOOT This option enables the support for secure boot (HAB). See doc/README.mxc_hab for more details. +config CSF_SIZE + hex "Maximum size for Command Sequence File (CSF) binary" + default 0x4000 + help + Define the maximum size for Command Sequence File (CSF) binary + this information is used to define the image boot data. + config CMD_BMODE bool "Support the 'bmode' command" default y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 59ba4bcb520..8d3cdec22bb 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_IMX8MQ_EVK=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_CSF_SIZE=0x2000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 67c52d76e72..06f987d3ff1 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -19,7 +19,6 @@ /* Uncomment to enable secure boot support */ /* #define CONFIG_SECURE_BOOT */ -#define CONFIG_CSF_SIZE 0x4000 /* Network */ #define CONFIG_FEC_MXC diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 1ceec5ab5ab..d4d8d20850f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -9,10 +9,6 @@ #include #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ -#endif - #define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index f6c0e21d072..07b1e06f4f4 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -56,12 +56,8 @@ /* MMC */ -/* Secure boot (HAB) support */ -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE 0x4000 #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #endif -#endif #endif diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index fb8f44684b6..b96e63198d1 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -10,12 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SECURE_BOOT -#ifndef CONFIG_CSF_SIZE -#define CONFIG_CSF_SIZE 0x4000 -#endif -#endif - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index f5f3de6cd46..3bcd0d3ee34 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -13,12 +13,6 @@ #include "mx6_common.h" #include -#ifdef CONFIG_SECURE_BOOT -#ifndef CONFIG_CSF_SIZE -#define CONFIG_CSF_SIZE 0x4000 -#endif -#endif - #define PHYS_SDRAM_SIZE SZ_512M /* Size of malloc() pool */ diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 70dda35eb06..b6ded774cc4 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -45,13 +45,9 @@ #define CONFIG_ARMV7_PSCI_1_0 -/* Secure boot (HAB) support */ -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE 0x4000 #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #endif -#endif /* * If we have defined the OPTEE ram size and not OPTEE it means that we were diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 763a46b47fe..8964dcd40e5 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -14,12 +14,6 @@ /*Uncomment it to use secure boot*/ /*#define CONFIG_SECURE_BOOT*/ -#ifdef CONFIG_SECURE_BOOT -#ifndef CONFIG_CSF_SIZE -#define CONFIG_CSF_SIZE 0x4000 -#endif -#endif - #define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_SYS_BOOTM_LEN 0x1000000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5a007d37091..c7b02451e0c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -266,7 +266,6 @@ CONFIG_CPU_VR41XX CONFIG_CQSPI_REF_CLK CONFIG_CS8900_BUS16 CONFIG_CS8900_BUS32 -CONFIG_CSF_SIZE CONFIG_CTL_JTAG CONFIG_CTL_TBE CONFIG_CUSTOMER_BOARD_SUPPORT From 717143716602244037cb14359b02c14b0d75c464 Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Thu, 18 Jul 2019 12:34:23 +0000 Subject: [PATCH 040/190] imx6: spl: Reduce SPL limit size in case CONFIG_SECURE_BOOT is enabled In case CONFIG_SECURE_BOOT is enabled we need to limit the SPL size to avoid a possible HAB failure event: --------- HAB Event 1 ----------------- event data: 0xdb 0x00 0x14 0x42 0x33 0x22 0x33 0x00 0x00 0x00 0x00 0x0f 0x00 0x90 0x70 0x00 0x00 0x01 0x10 0x00 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ADDRESS (0x22) CTX = HAB_CTX_TARGET (0x33) ENG = HAB_ENG_ANY (0x00) As explained in Commit 23612534fe0f ("spl: imx6: Provide a SPL_SIZE_LIMIT default") the i.MX6 SPL size limit is 68KB. The ROM code is copying the image size defined in boot data to its respective load address, in case we exceed the OCRAM free region a HAB invalid address failure event is generated. The maximum CSF size is defined in CONFIG_CSF_SIZE, reduce SPL size limit based on this configuration. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam --- tools/spl_size_limit.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/spl_size_limit.c b/tools/spl_size_limit.c index 98ff491867a..8902e30129a 100644 --- a/tools/spl_size_limit.c +++ b/tools/spl_size_limit.c @@ -14,6 +14,9 @@ int main(int argc, char *argv[]) #ifdef CONFIG_SPL_SIZE_LIMIT spl_size_limit = CONFIG_SPL_SIZE_LIMIT; +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_CSF_SIZE) + spl_size_limit -= CONFIG_CSF_SIZE; +#endif #ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD spl_size_limit -= GENERATED_GBL_DATA_SIZE; #endif From e735c62701a1df86e5a43cbc8c003c5faeffed99 Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Thu, 18 Jul 2019 12:34:30 +0000 Subject: [PATCH 041/190] imx: configs: Cleanup CONFIG_SECURE_BOOT comments Since commit 6e1f4d2652e7 ("arm: imx-common: add SECURE_BOOT option to Kconfig") the SECURE_BOOT option is selected through Kconfig. Cleanup comments in code to align with this change. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam --- include/configs/cl-som-imx7.h | 3 --- include/configs/mx7ulp_evk.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 06f987d3ff1..d0a60c25f7a 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -17,9 +17,6 @@ #define CONFIG_BOARD_LATE_INIT -/* Uncomment to enable secure boot support */ -/* #define CONFIG_SECURE_BOOT */ - /* Network */ #define CONFIG_FEC_MXC #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 8964dcd40e5..3b023624984 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -11,9 +11,6 @@ #include #include -/*Uncomment it to use secure boot*/ -/*#define CONFIG_SECURE_BOOT*/ - #define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_SYS_BOOTM_LEN 0x1000000 From ebf4f0944d1cc6a0963abd830a947561289024dc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 14 Aug 2019 09:13:04 +0000 Subject: [PATCH 042/190] imx: mx6sabresd: fix usb start when DM enabled Enable CONFIG_DM_REGULATOR_FIXED to let vbus regulator work. Signed-off-by: Peng Fan --- configs/mx6sabresd_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index b2c77ff4dab..93f0ee9779b 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -84,6 +84,7 @@ CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y From 7932b1c9fdb73393aa110249c89bd426533c0649 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 14 Aug 2019 09:27:06 +0000 Subject: [PATCH 043/190] imx: imx6qdl: dtsi: move U-Boot specific change to u-boot.dtsi The changes were added by following patch: commit <9002e735e717> ("imx: mx6sabresd: fix boot hang with video") commit ("imx6: dts: add 'u-boot, dm-pre-reloc' to soc and ipu nodes") Let's move the U-Boot specific change to imx6qdl-u-boot.dtsi Signed-off-by: Peng Fan --- arch/arm/dts/imx6qdl-u-boot.dtsi | 6 ++++++ arch/arm/dts/imx6qdl.dtsi | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi index e161ebb9af4..1279cc2338b 100644 --- a/arch/arm/dts/imx6qdl-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-u-boot.dtsi @@ -6,10 +6,12 @@ / { aliases { usb0 = &usbotg; + video0 = &ipu1; }; soc { u-boot,dm-spl; + u-boot,dm-pre-reloc; aips-bus@2000000 { u-boot,dm-spl; @@ -31,3 +33,7 @@ &iomuxc { u-boot,dm-spl; }; + +&ipu1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index 83eeb5cc591..e4daf150881 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -33,7 +33,6 @@ i2c1 = &i2c2; i2c2 = &i2c3; ipu0 = &ipu1; - video0 = &ipu1; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -146,7 +145,6 @@ compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; - u-boot,dm-pre-reloc; dma_apbh: dma-apbh@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; @@ -1263,7 +1261,6 @@ <&clks IMX6QDL_CLK_IPU1_DI1>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; - u-boot,dm-pre-reloc; ipu1_csi0: port@0 { reg = <0>; From b152584283088b79b967f361e673c744d3ef325b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 21 Aug 2019 08:28:15 +0000 Subject: [PATCH 044/190] imx: imx8qxp_mek: fix CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR The first stage of flash.bin is larger than 584 * 512, so when writting u-boot.itb, some data will be override. Enlarge the CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to fix boot. Signed-off-by: Peng Fan --- board/freescale/imx8qxp_mek/README | 2 +- include/configs/imx8qxp_mek.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README index f32290e3a2b..9f2e2f7b126 100644 --- a/board/freescale/imx8qxp_mek/README +++ b/board/freescale/imx8qxp_mek/README @@ -43,7 +43,7 @@ $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make imx8qxp_mek_defconfig $ make flash.bin -$ dd if=u-boot.itb of=flash.bin bs=512 seek=528 +$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 Flash the binary into the SD card ================================= diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index c357c7bbe6a..872805cae61 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -13,7 +13,7 @@ #define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" From 7b86cd4274e66e0336b6da1399a0e7a7a4a1581e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 22 Aug 2019 07:42:33 +0000 Subject: [PATCH 045/190] imx8: support parsing i.MX8 Container file Add parsing i.MX8 Container file support, this is to let SPL could load images in a container file to destination address. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8/image.h | 56 +++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 ++ arch/arm/mach-imx/imx8/Makefile | 4 + arch/arm/mach-imx/imx8/parse-container.c | 120 +++++++++++++++++++++++ 4 files changed, 186 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/image.h create mode 100644 arch/arm/mach-imx/imx8/parse-container.c diff --git a/arch/arm/include/asm/arch-imx8/image.h b/arch/arm/include/asm/arch-imx8/image.h new file mode 100644 index 00000000000..c1e5700859d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/image.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef __CONTAINER_HEADER_H_ +#define __CONTAINER_HEADER_H_ + +#include +#include + +#define IV_MAX_LEN 32 +#define HASH_MAX_LEN 64 + +#define CONTAINER_HDR_ALIGNMENT 0x400 +#define CONTAINER_HDR_EMMC_OFFSET 0 +#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K +#define CONTAINER_HDR_QSPI_OFFSET SZ_4K +#define CONTAINER_HDR_NAND_OFFSET SZ_128M + +struct container_hdr { + u8 version; + u8 length_lsb; + u8 length_msb; + u8 tag; + u32 flags; + u16 sw_version; + u8 fuse_version; + u8 num_images; + u16 sig_blk_offset; + u16 reserved; +} __packed; + +struct boot_img_t { + u32 offset; + u32 size; + u64 dst; + u64 entry; + u32 hab_flags; + u32 meta; + u8 hash[HASH_MAX_LEN]; + u8 iv[IV_MAX_LEN]; +} __packed; + +struct signature_block_hdr { + u8 version; + u8 length_lsb; + u8 length_msb; + u8 tag; + u16 srk_table_offset; + u16 cert_offset; + u16 blob_offset; + u16 signature_offset; + u32 reserved; +} __packed; +#endif diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index bbe323d5ca4..e9496cb6112 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -23,6 +23,12 @@ config IMX8QXP config SYS_SOC default "imx8" +config SPL_LOAD_IMX_CONTAINER + bool "Enable SPL loading U-Boot as a i.MX Container image" + depends on SPL + help + This is to let SPL could load i.MX8 Container image + choice prompt "i.MX8 board select" optional diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 92b5c56acb2..5f62b2826e2 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -5,3 +5,7 @@ # obj-y += cpu.o iomux.o misc.o + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += parse-container.o +endif diff --git a/arch/arm/mach-imx/imx8/parse-container.c b/arch/arm/mach-imx/imx8/parse-container.c new file mode 100644 index 00000000000..32f78bdddfb --- /dev/null +++ b/arch/arm/mach-imx/imx8/parse-container.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + */ + +#include +#include +#include +#include + +static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, + struct spl_load_info *info, + struct container_hdr *container, + int image_index, + u32 container_sector) +{ + struct boot_img_t *images; + ulong sector; + u32 sectors; + + if (image_index > container->num_images) { + debug("Invalid image number\n"); + return NULL; + } + + images = (struct boot_img_t *)((u8 *)container + + sizeof(struct container_hdr)); + + if (images[image_index].offset % info->bl_len) { + printf("%s: image%d offset not aligned to %u\n", + __func__, image_index, info->bl_len); + return NULL; + } + + sectors = roundup(images[image_index].size, info->bl_len) / + info->bl_len; + sector = images[image_index].offset / info->bl_len + + container_sector; + + debug("%s: container: %p sector: %lu sectors: %u\n", __func__, + container, sector, sectors); + if (info->read(info, sector, sectors, + (void *)images[image_index].entry) != sectors) { + printf("%s wrong\n", __func__); + return NULL; + } + + return &images[image_index]; +} + +static int read_auth_container(struct spl_image_info *spl_image, + struct spl_load_info *info, ulong sector) +{ + struct container_hdr *container = NULL; + u16 length; + u32 sectors; + int i, size; + + size = roundup(CONTAINER_HDR_ALIGNMENT, info->bl_len); + sectors = size / info->bl_len; + + /* + * It will not override the ATF code, so safe to use it here, + * no need malloc + */ + container = (struct container_hdr *)spl_get_load_buffer(-size, size); + + debug("%s: container: %p sector: %lu sectors: %u\n", __func__, + container, sector, sectors); + if (info->read(info, sector, sectors, container) != sectors) + return -EIO; + + if (container->tag != 0x87 && container->version != 0x0) { + printf("Wrong container header"); + return -ENOENT; + } + + if (!container->num_images) { + printf("Wrong container, no image found"); + return -ENOENT; + } + + length = container->length_lsb + (container->length_msb << 8); + debug("Container length %u\n", length); + + if (length > CONTAINER_HDR_ALIGNMENT) { + size = roundup(length, info->bl_len); + sectors = size / info->bl_len; + + container = (struct container_hdr *)spl_get_load_buffer(-size, size); + + debug("%s: container: %p sector: %lu sectors: %u\n", + __func__, container, sector, sectors); + if (info->read(info, sector, sectors, container) != + sectors) + return -EIO; + } + + for (i = 0; i < container->num_images; i++) { + struct boot_img_t *image = read_auth_image(spl_image, info, + container, i, + sector); + + if (!image) + return -EINVAL; + + if (i == 0) { + spl_image->load_addr = image->dst; + spl_image->entry_point = image->entry; + } + } + + return 0; +} + +int spl_load_imx_container(struct spl_image_info *spl_image, + struct spl_load_info *info, ulong sector) +{ + return read_auth_container(spl_image, info, sector); +} From dd7d0911e0048e4ddb8a4084d2221242aed8c62b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 22 Aug 2019 07:42:38 +0000 Subject: [PATCH 046/190] spl: mmc: support loading i.MX container format file i.MX8 only support AHAB secure boot with Container format image, we could not use FIT to support secure boot, so introduce container support to let SPL could load container images. Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: York Sun Cc: Marek Vasut Cc: Alex Kiernan Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Heiko Schocher Signed-off-by: Peng Fan --- common/spl/spl_mmc.c | 10 ++++++++++ include/spl.h | 12 ++++++++++++ 2 files changed, 22 insertions(+) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index b3619889f79..6c6eaf4ec87 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -79,6 +79,16 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, load.bl_len = mmc->read_bl_len; load.read = h_spl_load_read; ret = spl_load_simple_fit(spl_image, &load, sector, header); + } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { + struct spl_load_info load; + + load.dev = mmc; + load.priv = NULL; + load.filename = NULL; + load.bl_len = mmc->read_bl_len; + load.read = h_spl_load_read; + + ret = spl_load_imx_container(spl_image, &load, sector); } else { ret = mmc_load_legacy(spl_image, mmc, sector, header); } diff --git a/include/spl.h b/include/spl.h index fd4747b44e4..f9c674d33bf 100644 --- a/include/spl.h +++ b/include/spl.h @@ -134,6 +134,18 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, #define SPL_COPY_PAYLOAD_ONLY 1 #define SPL_FIT_FOUND 2 +/** + * spl_load_imx_container() - Loads a imx container image from a device. + * @spl_image: Image description to set up + * @info: Structure containing the information required to load data. + * @sector: Sector number where container image is located in the device + * + * Reads the container image @sector in the device. Loads u-boot image to + * specified load address. + */ +int spl_load_imx_container(struct spl_image_info *spl_image, + struct spl_load_info *info, ulong sector); + /* SPL common functions */ void preloader_console_init(void); u32 spl_boot_device(void); From 700315c9ac4d44740884ed6a02a5dc56bec92868 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 22 Aug 2019 07:42:41 +0000 Subject: [PATCH 047/190] imx: add container target To support SPL loading container file, add a new Makefile target, and introduce a new Kconfig file to source the cfg file which will be parsed by mkimage. Signed-off-by: Peng Fan --- Makefile | 8 ++++++++ arch/arm/mach-imx/Makefile | 14 ++++++++++++-- arch/arm/mach-imx/imx8/Kconfig | 7 +++++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 54da5cd51ce..733bcecd081 100644 --- a/Makefile +++ b/Makefile @@ -1365,9 +1365,17 @@ SPL: spl/u-boot-spl.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y) +ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y) +u-boot.cnt: u-boot.bin FORCE + $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ + +flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE + $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +else flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ endif +endif u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 08ee52edbff..17b241ae996 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -90,6 +90,11 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) +IMX_CONTAINER_CFG = $(CONFIG_IMX_CONTAINER_CFG:"%"=%) +container.cfg: $(IMX_CONTAINER_CFG) FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cpp_cfg) + ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image @@ -158,10 +163,15 @@ SPL: MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout -T $(IMAGE_TYPE) -e 0x100000 flash.bin: MKIMAGEOUTPUT = flash.log -flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE -ifeq ($(SPL_DEPFILE_EXISTS),0) +MKIMAGEFLAGS_u-boot.cnt = -n container.cfg -T $(IMAGE_TYPE) -e 0x100000 +u-boot.cnt: MKIMAGEOUTPUT = u-boot.cnt.log + +ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y) +u-boot.cnt: u-boot.bin container.cfg FORCE $(call if_changed,mkimage) endif +flash.bin: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) endif else diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index e9496cb6112..d17760e3337 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -29,6 +29,13 @@ config SPL_LOAD_IMX_CONTAINER help This is to let SPL could load i.MX8 Container image +config IMX_CONTAINER_CFG + string "i.MX Container config file" + depends on SPL + help + This is to specific the cfg file for generating container + image which will be loaded by SPL. + choice prompt "i.MX8 board select" optional From d94049ce19e20a07e12dbf2175981cbfeb43d8a7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 22 Aug 2019 07:42:43 +0000 Subject: [PATCH 048/190] imx8qxp_mek: switch to use container image Because FIT could not be used for AHAB secure boot on i.MX8, so switch to use container image that could let SPL verify ATF and U-Boot with AHAB. Note: The AHAB related code has not been added. Signed-off-by: Peng Fan --- board/freescale/imx8qxp_mek/README | 4 +--- board/freescale/imx8qxp_mek/uboot-container.cfg | 13 +++++++++++++ configs/imx8qxp_mek_defconfig | 5 ++--- 3 files changed, 16 insertions(+), 6 deletions(-) create mode 100644 board/freescale/imx8qxp_mek/uboot-container.cfg diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README index 9f2e2f7b126..1ee03579614 100644 --- a/board/freescale/imx8qxp_mek/README +++ b/board/freescale/imx8qxp_mek/README @@ -39,11 +39,9 @@ $ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin . Build U-Boot ============ -$ export ATF_LOAD_ADDR=0x80000000 -$ export BL33_LOAD_ADDR=0x80020000 $ make imx8qxp_mek_defconfig $ make flash.bin -$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 +$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984 Flash the binary into the SD card ================================= diff --git a/board/freescale/imx8qxp_mek/uboot-container.cfg b/board/freescale/imx8qxp_mek/uboot-container.cfg new file mode 100644 index 00000000000..81658118185 --- /dev/null +++ b/board/freescale/imx8qxp_mek/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QX +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index f4cc86ec1d0..580d75751ee 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -7,15 +7,14 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" CONFIG_TARGET_IMX8QXP_MEK=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y From f31f8b0434fd3f6f855b1d58cc66fc9b4c0b8cd9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 22 Aug 2019 07:42:46 +0000 Subject: [PATCH 049/190] imx8qm_mek: switch to use container image Because FIT could not be used for AHAB secure boot on i.MX8, so switch to use container image that could let SPL verify ATF and U-Boot with AHAB. Enable HUSH_PARSER in defconfig to make run netboot could work. Note: The AHAB related code has not been added. Signed-off-by: Peng Fan --- board/freescale/imx8qm_mek/README | 4 +--- board/freescale/imx8qm_mek/uboot-container.cfg | 13 +++++++++++++ configs/imx8qm_mek_defconfig | 8 +++++--- 3 files changed, 19 insertions(+), 6 deletions(-) create mode 100644 board/freescale/imx8qm_mek/uboot-container.cfg diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README index c3523801ae9..ebf630c446a 100644 --- a/board/freescale/imx8qm_mek/README +++ b/board/freescale/imx8qm_mek/README @@ -39,11 +39,9 @@ $ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin . Build U-Boot ============ -$ export ATF_LOAD_ADDR=0x80000000 -$ export BL33_LOAD_ADDR=0x80020000 $ make imx8qm_mek_defconfig $ make flash.bin -$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 +$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984 Flash the binary into the SD card ================================= diff --git a/board/freescale/imx8qm_mek/uboot-container.cfg b/board/freescale/imx8qm_mek/uboot-container.cfg new file mode 100644 index 00000000000..6cc47cd1027 --- /dev/null +++ b/board/freescale/imx8qm_mek/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QM +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 42591c77812..ee29be4930f 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -6,23 +6,25 @@ CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" CONFIG_TARGET_IMX8QM_MEK=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_IMPORTENV is not set From b5661caf84cdc28315bb759f823c83ae7d4a4ab6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 22 Aug 2019 07:42:49 +0000 Subject: [PATCH 050/190] doc: imx: mkimage: introduce i.MX8 image format Introduce i.MX8 container set configuration file and add example Signed-off-by: Peng Fan --- doc/imx/mkimage/imx8image.txt | 45 +++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 doc/imx/mkimage/imx8image.txt diff --git a/doc/imx/mkimage/imx8image.txt b/doc/imx/mkimage/imx8image.txt new file mode 100644 index 00000000000..76664a86fa4 --- /dev/null +++ b/doc/imx/mkimage/imx8image.txt @@ -0,0 +1,45 @@ +Introduction: +============= + +This documentation entry describes the i.MX8 container format and how +to use. + +A Boot image consists of: + - Primary Boot Container Set + - Optional Secondary Boot Container Set + +The imx8image only support the Primary Boot Container Set. + +The Primary Boot Container Set contains two containers. The 1st container +only contain the SECO firmware image, the 2nd container can contain +multiple images and typically have: + - SCF FW image + - M4 FW image + - AP FW image + +For more details, refer i.MX8 Reference Mannual Chapter 5 +"System Boot and section", "5.9 (Boot image) of the processor's manual" + +Configuration file: +================== +BOOT_FROM [sd|emmc_fastboot|fspi|nand_4k|nand_8k|nand_16k] [sector_size] + - indicates the boot media +SOC_TYPE [IMX8QM|IMX8QX] + - indicates the soc +APPEND [ahab container image] + - indicates the ahah image that will be put in the 1st container + When creating container image will be loaded by SPL, this entry + should not this included +CONTAINER + - indicates to create the 2nd container +IMAGE [SCU|M40|M41|A35|A53|A72] [image file] [load address] + - indicates images will be put in the 2nd container + +Example: +======= +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QM +APPEND mx8qm-ahab-container.img +CONTAINER +IMAGE SCU mx8qm-mek-scfw-tcm.bin +IMAGE A35 spl/u-boot-spl.bin 0x00100000 From bcf94abd1cab06d066142aa39aa044b94071c5b7 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 26 Aug 2019 08:11:42 +0000 Subject: [PATCH 051/190] imx8: Probe the SCU driver by using uclass function Since SCU MU driver has been bound in dm_init, so we don't need to bind it again. Just replace by using uclass function to probe it. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/cpu.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f2fa262ac89..667f829acd5 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -60,17 +60,10 @@ int arch_cpu_init_dm(void) int node, ret; node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); - ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu", - offset_to_ofnode(node), &devp); + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); if (ret) { - printf("could not find scu %d\n", ret); - return ret; - } - - ret = device_probe(devp); - if (ret) { - printf("scu probe failed %d\n", ret); + printf("could not get scu %d\n", ret); return ret; } From b5fd5fd5a4d770d6ea39a69355c95c4acabb7cac Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:11:46 +0000 Subject: [PATCH 052/190] imx: sys_proto: add is_imx8qm helper Add is_imx8qm helper which could be used by SoC and Driver code. Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/sys_proto.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 260608062e1..449366fa8d4 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -44,6 +44,7 @@ #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) +#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #ifdef CONFIG_MX6 From 8f99438b095aaf9b6472a21e2f087483439826da Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:11:49 +0000 Subject: [PATCH 053/190] imx8qm: power up SMMU There is SMMU in i.MX8QM. To use SMMU in Linux, need power up it. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 667f829acd5..1a5d8113732 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -67,6 +67,13 @@ int arch_cpu_init_dm(void) return ret; } + if (is_imx8qm()) { + ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU, + SC_PM_PW_MODE_ON); + if (ret) + return ret; + } + return 0; } From ed2ebd8629618b6964fd4bcceba3d69fe139063f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:11:53 +0000 Subject: [PATCH 054/190] imx8qm: correct fdt_file imx8qm-mek.dtb is the correct fdt file, not fsl-imx8qxp-mek.dtb Signed-off-by: Peng Fan --- include/configs/imx8qm_mek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 7a790ef1581..869035172e3 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -64,7 +64,7 @@ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ - "fdt_file=fsl-imx8qxp-mek.dtb\0" \ + "fdt_file=imx8qm-mek.dtb\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ From 9f779fa4105f463920e5a857d775672fd0890c41 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:11:56 +0000 Subject: [PATCH 055/190] imx8: disable node when the resource is not owned When resource is not assigned to non-secure Linux, if linux continue to use the node, linux may crash or hang. So need to set the node status to disabled for not owned resources. The resource id is in the power-domains property in device tree, so parse the power-domains property to get the resource id and use scfw api to check whether it is owned by current partition. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/Makefile | 1 + arch/arm/mach-imx/imx8/fdt.c | 108 ++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/fdt.c diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 5f62b2826e2..7fc34762a2a 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -5,6 +5,7 @@ # obj-y += cpu.o iomux.o misc.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += parse-container.o diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c new file mode 100644 index 00000000000..d20cb6973ac --- /dev/null +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static bool check_owned_resource(sc_rsrc_t rsrc_id) +{ + bool owned; + + owned = sc_rm_is_resource_owned(-1, rsrc_id); + + return owned; +} + +static int disable_fdt_node(void *blob, int nodeoffset) +{ + int rc, ret; + const char *status = "disabled"; + + do { + rc = fdt_setprop(blob, nodeoffset, "status", status, + strlen(status) + 1); + if (rc) { + if (rc == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob, 512); + if (ret) + return ret; + } + } + } while (rc == -FDT_ERR_NOSPACE); + + return rc; +} + +static void update_fdt_with_owned_resources(void *blob) +{ + /* + * Traverses the fdt nodes, check its power domain and use + * the resource id in the power domain for checking whether + * it is owned by current partition + */ + struct fdtdec_phandle_args args; + int offset = 0, depth = 0; + u32 rsrc_id; + int rc, i; + + for (offset = fdt_next_node(blob, offset, &depth); offset > 0; + offset = fdt_next_node(blob, offset, &depth)) { + debug("Node name: %s, depth %d\n", + fdt_get_name(blob, offset, NULL), depth); + + if (!fdt_get_property(blob, offset, "power-domains", NULL)) { + debug(" - ignoring node %s\n", + fdt_get_name(blob, offset, NULL)); + continue; + } + + if (!fdtdec_get_is_enabled(blob, offset)) { + debug(" - ignoring node %s\n", + fdt_get_name(blob, offset, NULL)); + continue; + } + + i = 0; + while (true) { + rc = fdtdec_parse_phandle_with_args(blob, offset, + "power-domains", + "#power-domain-cells", + 0, i++, &args); + if (rc == -ENOENT) { + break; + } else if (rc) { + printf("Parse power-domains of %s wrong: %d\n", + fdt_get_name(blob, offset, NULL), rc); + continue; + } + + rsrc_id = args.args[0]; + + if (!check_owned_resource(rsrc_id)) { + rc = disable_fdt_node(blob, offset); + if (!rc) { + printf("Disable %s rsrc %u not owned\n", + fdt_get_name(blob, offset, NULL), + rsrc_id); + } else { + printf("Unable to disable %s, err=%s\n", + fdt_get_name(blob, offset, NULL), + fdt_strerror(rc)); + } + } + } + } +} + +int ft_system_setup(void *blob, bd_t *bd) +{ + update_fdt_with_owned_resources(blob); + + return 0; +} From 6e92cae3cdbdad119bdfc5af73cf92bb028d3cc9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:00 +0000 Subject: [PATCH 056/190] configs: imx8qm/qxp_mek: enable CONFIG_OF_SYSTEM_SETUP Enable CONFIG_OF_SYSTEM_SETUP to let U-Boot could disable device tree nodes that could not be used by Linux. Signed-off-by: Peng Fan --- configs/imx8qm_mek_defconfig | 1 + configs/imx8qxp_mek_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index ee29be4930f..57cf659b25e 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_SPL=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 580d75751ee..ded6036be9e 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_SPL=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y From 268644735b24b127ad832a18279f63967293c83d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:03 +0000 Subject: [PATCH 057/190] imx: scu_api: add sc_rm_set_master_sid Add sc_rm_set_master_sid to set stream sid of masters to make sure they could use smmu. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8/sci/sci.h | 1 + drivers/misc/imx8/scu_api.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index 901b90d705f..48810e251c4 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -80,6 +80,7 @@ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end); sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); +int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); /* PAD API */ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 031bc0048b6..1856f3a44af 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -332,6 +332,28 @@ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) return (sc_bool_t)result; } +int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_SET_MASTER_SID; + RPC_U16(&msg, 0U) = (u16)resource; + RPC_U16(&msg, 2U) = (u16)sid; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: resource:%d sid:%d: res:%d\n", + __func__, resource, sid, RPC_R8(&msg)); + + return ret; +} + int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end) { From 01cacf9682f5f1988a63705620ce37c1fe840b9c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:06 +0000 Subject: [PATCH 058/190] imx8: fdt: configure sid for masters On i.MX8QM, sid is programmable, so we could program sid according the value encoded in device tree. This patch support legacy bindings which are still being used by XEN and new bindings used by Linux Kernel. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/fdt.c | 138 ++++++++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index d20cb6973ac..b2e7cf09cf4 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -100,9 +101,142 @@ static void update_fdt_with_owned_resources(void *blob) } } -int ft_system_setup(void *blob, bd_t *bd) +static int config_smmu_resource_sid(int rsrc, int sid) { - update_fdt_with_owned_resources(blob); + int err; + + if (!check_owned_resource(rsrc)) { + printf("%s rsrc[%d] not owned\n", __func__, rsrc); + return -1; + } + err = sc_rm_set_master_sid(-1, rsrc, sid); + debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); + if (err != SC_ERR_NONE) { + pr_err("fail set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); + return -EINVAL; + } + + return 0; +} + +static int config_smmu_fdt_device_sid(void *blob, int device_offset, int sid) +{ + const char *name = fdt_get_name(blob, device_offset, NULL); + struct fdtdec_phandle_args args; + int rsrc, ret; + int proplen; + const fdt32_t *prop; + int i; + + prop = fdt_getprop(blob, device_offset, "fsl,sc_rsrc_id", &proplen); + if (prop) { + int i; + + debug("configure node %s sid 0x%x for %d resources\n", + name, sid, (int)(proplen / sizeof(fdt32_t))); + for (i = 0; i < proplen / sizeof(fdt32_t); ++i) { + ret = config_smmu_resource_sid(fdt32_to_cpu(prop[i]), + sid); + if (ret) + return ret; + } + + return 0; + } + + i = 0; + while (true) { + ret = fdtdec_parse_phandle_with_args(blob, device_offset, + "power-domains", + "#power-domain-cells", + 0, i++, &args); + if (ret == -ENOENT) { + break; + } else if (ret) { + printf("Parse power-domains of node %s wrong: %d\n", + fdt_get_name(blob, device_offset, NULL), ret); + continue; + } + + debug("configure node %s sid 0x%x rsrc=%d\n", + name, sid, rsrc); + rsrc = args.args[0]; + + ret = config_smmu_resource_sid(rsrc, sid); + if (ret) + break; + } + + return ret; +} + +static int config_smmu_fdt(void *blob) +{ + int offset, proplen, i, ret; + const fdt32_t *prop; + const char *name; + + /* Legacy smmu bindings, still used by xen. */ + offset = fdt_node_offset_by_compatible(blob, 0, "arm,mmu-500"); + prop = fdt_getprop(blob, offset, "mmu-masters", &proplen); + if (offset > 0 && prop) { + debug("found legacy mmu-masters property\n"); + + for (i = 0; i < proplen / 8; ++i) { + u32 phandle = fdt32_to_cpu(prop[2 * i]); + int sid = fdt32_to_cpu(prop[2 * i + 1]); + int device_offset; + + device_offset = fdt_node_offset_by_phandle(blob, + phandle); + if (device_offset < 0) { + pr_err("Not find device from mmu_masters: %d", + device_offset); + continue; + } + ret = config_smmu_fdt_device_sid(blob, device_offset, + sid); + if (ret) + return ret; + } + + /* Ignore new bindings if old bindings found, just like linux. */ + return 0; + } + + /* Generic smmu bindings */ + offset = 0; + while ((offset = fdt_next_node(blob, offset, NULL)) > 0) { + name = fdt_get_name(blob, offset, NULL); + prop = fdt_getprop(blob, offset, "iommus", &proplen); + if (!prop) + continue; + debug("node %s iommus proplen %d\n", name, proplen); + + if (proplen == 12) { + int sid = fdt32_to_cpu(prop[1]); + + config_smmu_fdt_device_sid(blob, offset, sid); + } else if (proplen != 4) { + debug("node %s ignore unexpected iommus proplen=%d\n", + name, proplen); + } + } + + return 0; +} + +int ft_system_setup(void *blob, bd_t *bd) +{ + int ret; + + update_fdt_with_owned_resources(blob); + + if (is_imx8qm()) { + ret = config_smmu_fdt(blob); + if (ret) + return ret; + } return 0; } From fefe051335aa99147420fee607f7596e6e9c9044 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:09 +0000 Subject: [PATCH 059/190] imx8: save args passed from ATF We use information from ATF to know whether OP-TEE is running or not. So save args passed from ATF. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8/sys_proto.h | 1 + arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/lowlevel_init.S | 36 ++++++++++++++++++++++ 3 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/imx8/lowlevel_init.S diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index b8d2a0b8f0c..0e981ae950e 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -16,6 +16,7 @@ struct pass_over_info_t { u32 g_ap_mu; }; +extern unsigned long boot_pointer[]; void build_info(void); enum boot_device get_boot_device(void); int print_bootinfo(void); diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 7fc34762a2a..97f9d229451 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o iomux.o misc.o +obj-y += cpu.o iomux.o misc.o lowlevel_init.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-imx/imx8/lowlevel_init.S b/arch/arm/mach-imx/imx8/lowlevel_init.S new file mode 100644 index 00000000000..a66243c5e4f --- /dev/null +++ b/arch/arm/mach-imx/imx8/lowlevel_init.S @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#include + +.align 8 +.global boot_pointer +boot_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + adr x0, boot_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + /* + * We use absolute address not PC relative address for return. + * When running SPL on iMX8, the A core starts at address 0, + * an alias to OCRAM 0x100000, our linker address for SPL is + * from 0x100000. So using absolute address can jump to the OCRAM + * address from the alias. The alias only map first 96KB of OCRAM, + * so this require the SPL size can't beyond 96KB. + * But when using SPL DM, the size increase significantly and + * always beyonds 96KB. That's why we have to jump to OCRAM. + * Normal u-boot also runs into this codes, but there is no impact. + */ + ldr x1, =save_boot_params_ret + br x1 From 94e4d028b29fb4c012b4ae1942b4d58d7937b63a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:13 +0000 Subject: [PATCH 060/190] imx8: fdt: add optee node Add OP-TEE device tree node for Linux according to args passed from ATF. If ATF has been built with OP-TEE running, boot_pointer[1] will indicate that. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/fdt.c | 52 +++++++++++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index b2e7cf09cf4..65c8ac1a7e2 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -226,6 +226,56 @@ static int config_smmu_fdt(void *blob) return 0; } +static int ft_add_optee_node(void *fdt, bd_t *bd) +{ + const char *path, *subpath; + int offs; + + /* + * No TEE space allocated indicating no TEE running, so no + * need to add optee node in dts + */ + if (!boot_pointer[1]) + return 0; + + offs = fdt_increase_size(fdt, 512); + if (offs) { + printf("No Space for dtb\n"); + return 1; + } + + path = "/firmware"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + path = "/"; + offs = fdt_path_offset(fdt, path); + + if (offs < 0) { + printf("Could not find root node.\n"); + return offs; + } + + subpath = "firmware"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + return offs; + } + } + + subpath = "optee"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + return offs; + } + + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); + fdt_setprop_string(fdt, offs, "method", "smc"); + + return 0; +} + int ft_system_setup(void *blob, bd_t *bd) { int ret; @@ -238,5 +288,5 @@ int ft_system_setup(void *blob, bd_t *bd) return ret; } - return 0; + return ft_add_optee_node(blob, bd); } From 8cacd788b40d1cbb80aafe2ee561ac7d74291446 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:16 +0000 Subject: [PATCH 061/190] imx: scu_api: add sc_pm_is_partition_started Add sc_pm_is_partition_started to check whether a partition has been started. This will be used to detect M4 partition booted up or not, then we could choose which dtb to use. If M4 is up, we need use dtb, such as imx8qm-mek-rpmsg.dtb. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8/sci/rpc.h | 5 ++++- arch/arm/include/asm/arch-imx8/sci/sci.h | 1 + drivers/misc/imx8/scu_api.c | 27 ++++++++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 746c2fa24d5..0dfd89ad11a 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -32,7 +32,9 @@ #define SC_RPC_SVC_PAD 6U #define SC_RPC_SVC_MISC 7U #define SC_RPC_SVC_IRQ 8U -#define SC_RPC_SVC_ABORT 9U +#define SC_RPC_SVC_SECO 9U +#define SC_RPC_SVC_ABORT 10U + /* Types */ @@ -74,6 +76,7 @@ struct sc_rpc_msg_s { #define PM_FUNC_REBOOT 9U #define PM_FUNC_REBOOT_PARTITION 12U #define PM_FUNC_CPU_START 11U +#define PM_FUNC_IS_PARTITION_STARTED 24U /* MISC RPC */ #define MISC_FUNC_UNKNOWN 0 diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index 48810e251c4..55b392fde15 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -81,6 +81,7 @@ int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end); sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); /* PAD API */ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 1856f3a44af..000a31f1b7b 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -119,6 +119,33 @@ int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, return ret; } +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + struct udevice *dev = gd->arch.scu_dev; + int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; + int ret; + u8 result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = (u8)(PM_FUNC_IS_PARTITION_STARTED); + RPC_U8(&msg, 0U) = (u8)(pt); + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + + result = RPC_R8(&msg); + if (result != 0 && result != 1) { + printf("%s: partition:%d res:%d\n", + __func__, pt, RPC_R8(&msg)); + if (ret) + printf("%s: partition:%d res:%d\n", __func__, pt, + RPC_R8(&msg)); + } + return !!result; +} + /* PAD */ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val) { From 43c50873854204cc5ca810516e160afb512303be Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:19 +0000 Subject: [PATCH 062/190] imx8: move i.MX8 cpu desc code to drivers/cpu/imx8_cpu.c Move cpu desc code to cpu driver directory and name it imx8_cpu.c No functional change. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/cpu.c | 168 -------------------------------- drivers/cpu/Makefile | 1 + drivers/cpu/imx8_cpu.c | 182 +++++++++++++++++++++++++++++++++++ 3 files changed, 183 insertions(+), 168 deletions(-) create mode 100644 drivers/cpu/imx8_cpu.c diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 1a5d8113732..4e6120cc035 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -528,171 +528,3 @@ u32 get_cpu_rev(void) return (id << 12) | rev; } -#if CONFIG_IS_ENABLED(CPU) -struct cpu_imx_platdata { - const char *name; - const char *rev; - const char *type; - u32 cpurev; - u32 freq_mhz; -}; - -const char *get_imx8_type(u32 imxtype) -{ - switch (imxtype) { - case MXC_CPU_IMX8QXP: - case MXC_CPU_IMX8QXP_A0: - return "QXP"; - case MXC_CPU_IMX8QM: - return "QM"; - default: - return "??"; - } -} - -const char *get_imx8_rev(u32 rev) -{ - switch (rev) { - case CHIP_REV_A: - return "A"; - case CHIP_REV_B: - return "B"; - default: - return "?"; - } -} - -const char *get_core_name(void) -{ - if (is_cortex_a35()) - return "A35"; - else if (is_cortex_a53()) - return "A53"; - else if (is_cortex_a72()) - return "A72"; - else - return "?"; -} - -#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL) -static int cpu_imx_get_temp(void) -{ - struct udevice *thermal_dev; - int cpu_tmp, ret; - - ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0", - &thermal_dev); - - if (!ret) { - ret = thermal_get_temp(thermal_dev, &cpu_tmp); - if (ret) - return 0xdeadbeef; - } else { - return 0xdeadbeef; - } - - return cpu_tmp; -} -#else -static int cpu_imx_get_temp(void) -{ - return 0; -} -#endif - -int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) -{ - struct cpu_imx_platdata *plat = dev_get_platdata(dev); - int ret; - - if (size < 100) - return -ENOSPC; - - ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz", - plat->type, plat->rev, plat->name, plat->freq_mhz); - - if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { - buf = buf + ret; - size = size - ret; - ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp()); - } - - snprintf(buf + ret, size - ret, "\n"); - - return 0; -} - -static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info) -{ - struct cpu_imx_platdata *plat = dev_get_platdata(dev); - - info->cpu_freq = plat->freq_mhz * 1000; - info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU); - return 0; -} - -static int cpu_imx_get_count(struct udevice *dev) -{ - return 4; -} - -static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size) -{ - snprintf(buf, size, "NXP"); - return 0; -} - -static const struct cpu_ops cpu_imx8_ops = { - .get_desc = cpu_imx_get_desc, - .get_info = cpu_imx_get_info, - .get_count = cpu_imx_get_count, - .get_vendor = cpu_imx_get_vendor, -}; - -static const struct udevice_id cpu_imx8_ids[] = { - { .compatible = "arm,cortex-a35" }, - { .compatible = "arm,cortex-a53" }, - { } -}; - -static ulong imx8_get_cpu_rate(void) -{ - ulong rate; - int ret; - int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ? - SC_R_A53 : SC_R_A72; - - ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU, - (sc_pm_clock_rate_t *)&rate); - if (ret) { - printf("Could not read CPU frequency: %d\n", ret); - return 0; - } - - return rate; -} - -static int imx8_cpu_probe(struct udevice *dev) -{ - struct cpu_imx_platdata *plat = dev_get_platdata(dev); - u32 cpurev; - - cpurev = get_cpu_rev(); - plat->cpurev = cpurev; - plat->name = get_core_name(); - plat->rev = get_imx8_rev(cpurev & 0xFFF); - plat->type = get_imx8_type((cpurev & 0xFF000) >> 12); - plat->freq_mhz = imx8_get_cpu_rate() / 1000000; - return 0; -} - -U_BOOT_DRIVER(cpu_imx8_drv) = { - .name = "imx8x_cpu", - .id = UCLASS_CPU, - .of_match = cpu_imx8_ids, - .ops = &cpu_imx8_ops, - .probe = imx8_cpu_probe, - .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata), - .flags = DM_FLAG_PRE_RELOC, -}; -#endif diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index be0300cd4a8..0b5dbc7c88e 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o +obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o obj-$(CONFIG_SANDBOX) += cpu_sandbox.o diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c new file mode 100644 index 00000000000..95653683ac2 --- /dev/null +++ b/drivers/cpu/imx8_cpu.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct cpu_imx_platdata { + const char *name; + const char *rev; + const char *type; + u32 cpurev; + u32 freq_mhz; +}; + +const char *get_imx8_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX8QXP: + case MXC_CPU_IMX8QXP_A0: + return "QXP"; + case MXC_CPU_IMX8QM: + return "QM"; + default: + return "??"; + } +} + +const char *get_imx8_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_A: + return "A"; + case CHIP_REV_B: + return "B"; + default: + return "?"; + } +} + +const char *get_core_name(void) +{ + if (is_cortex_a35()) + return "A35"; + else if (is_cortex_a53()) + return "A53"; + else if (is_cortex_a72()) + return "A72"; + else + return "?"; +} + +#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL) +static int cpu_imx_get_temp(void) +{ + struct udevice *thermal_dev; + int cpu_tmp, ret; + + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0", + &thermal_dev); + + if (!ret) { + ret = thermal_get_temp(thermal_dev, &cpu_tmp); + if (ret) + return 0xdeadbeef; + } else { + return 0xdeadbeef; + } + + return cpu_tmp; +} +#else +static int cpu_imx_get_temp(void) +{ + return 0; +} +#endif + +int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) +{ + struct cpu_imx_platdata *plat = dev_get_platdata(dev); + int ret; + + if (size < 100) + return -ENOSPC; + + ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz", + plat->type, plat->rev, plat->name, plat->freq_mhz); + + if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { + buf = buf + ret; + size = size - ret; + ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp()); + } + + snprintf(buf + ret, size - ret, "\n"); + + return 0; +} + +static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info) +{ + struct cpu_imx_platdata *plat = dev_get_platdata(dev); + + info->cpu_freq = plat->freq_mhz * 1000; + info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU); + return 0; +} + +static int cpu_imx_get_count(struct udevice *dev) +{ + return 4; +} + +static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size) +{ + snprintf(buf, size, "NXP"); + return 0; +} + +static const struct cpu_ops cpu_imx8_ops = { + .get_desc = cpu_imx_get_desc, + .get_info = cpu_imx_get_info, + .get_count = cpu_imx_get_count, + .get_vendor = cpu_imx_get_vendor, +}; + +static const struct udevice_id cpu_imx8_ids[] = { + { .compatible = "arm,cortex-a35" }, + { .compatible = "arm,cortex-a53" }, + { } +}; + +static ulong imx8_get_cpu_rate(void) +{ + ulong rate; + int ret; + int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ? + SC_R_A53 : SC_R_A72; + + ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU, + (sc_pm_clock_rate_t *)&rate); + if (ret) { + printf("Could not read CPU frequency: %d\n", ret); + return 0; + } + + return rate; +} + +static int imx8_cpu_probe(struct udevice *dev) +{ + struct cpu_imx_platdata *plat = dev_get_platdata(dev); + u32 cpurev; + + cpurev = get_cpu_rev(); + plat->cpurev = cpurev; + plat->name = get_core_name(); + plat->rev = get_imx8_rev(cpurev & 0xFFF); + plat->type = get_imx8_type((cpurev & 0xFF000) >> 12); + plat->freq_mhz = imx8_get_cpu_rate() / 1000000; + return 0; +} + +U_BOOT_DRIVER(cpu_imx8_drv) = { + .name = "imx8x_cpu", + .id = UCLASS_CPU, + .of_match = cpu_imx8_ids, + .ops = &cpu_imx8_ops, + .probe = imx8_cpu_probe, + .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata), + .flags = DM_FLAG_PRE_RELOC, +}; From bae4e8cb92295302ece0057e52a7666483878343 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Aug 2019 08:12:23 +0000 Subject: [PATCH 063/190] imx8: cpu: fix mac fuse word for i.MX8QM i.MX8QM does not share same FUSE MAC word index, so update the word index for i.MX8QM. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 4e6120cc035..d393a011782 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -475,10 +475,17 @@ u64 get_page_table_size(void) } #endif +#if defined(CONFIG_IMX8QM) +#define FUSE_MAC0_WORD0 452 +#define FUSE_MAC0_WORD1 453 +#define FUSE_MAC1_WORD0 454 +#define FUSE_MAC1_WORD1 455 +#elif defined(CONFIG_IMX8QXP) #define FUSE_MAC0_WORD0 708 #define FUSE_MAC0_WORD1 709 #define FUSE_MAC1_WORD0 710 #define FUSE_MAC1_WORD1 711 +#endif void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { From 40af7d39aab46383e3b0d52b4b06928231807637 Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Thu, 18 Jul 2019 12:34:15 +0000 Subject: [PATCH 064/190] habv4: tools: Avoid hardcoded CSF size for SPL targets Currently it's not possible to authenticate the U-Boot proper of mx6ul_14x14_evk_defconfig target: Authenticate image from DDR location 0x877fffc0... bad magic magic=0x0 length=0x00 version=0x3 bad length magic=0x0 length=0x00 version=0x3 bad version magic=0x0 length=0x00 version=0x3 spl: ERROR: image authentication fail Commit 0633e134784a ("imx: hab: Increase CSF_SIZE for i.MX6 and i.MX7 devices") has increased CSF_SIZE to avoid a possible issue when booting encrypted boot images. Commit d21bd69b6e95 ("tools: mkimage: add firmware-ivt image type for HAB verification") is hardcoding the CSF and IVT sizes, the new CSF size is not being considered and u-boot-ivt.img fails to boot. Avoid hardcoded CSF and IVT size to fix this issue. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam --- common/image.c | 8 +++++--- tools/default_image.c | 5 ++++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/common/image.c b/common/image.c index 179eef0bd2d..9badb915f48 100644 --- a/common/image.c +++ b/common/image.c @@ -61,6 +61,8 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, #endif /* !USE_HOSTCC*/ #include +#include +#include #ifndef CONFIG_SYS_BARGSIZE #define CONFIG_SYS_BARGSIZE 512 @@ -378,9 +380,9 @@ void image_print_contents(const void *ptr) } } else if (image_check_type(hdr, IH_TYPE_FIRMWARE_IVT)) { printf("HAB Blocks: 0x%08x 0x0000 0x%08x\n", - image_get_load(hdr) - image_get_header_size(), - image_get_size(hdr) + image_get_header_size() - - 0x1FE0); + image_get_load(hdr) - image_get_header_size(), + (int)(image_get_size(hdr) + image_get_header_size() + + sizeof(flash_header_v2_t) - CONFIG_CSF_SIZE)); } } diff --git a/tools/default_image.c b/tools/default_image.c index 4b7d1ed4a1a..7a262327798 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include static image_header_t header; @@ -106,7 +108,8 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, if (params->type == IH_TYPE_FIRMWARE_IVT) /* Add size of CSF minus IVT */ - imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0; + imagesize = sbuf->st_size - sizeof(image_header_t) + + CONFIG_CSF_SIZE - sizeof(flash_header_v2_t); else imagesize = sbuf->st_size - sizeof(image_header_t); From 70026345ed9131ef74b923f6b81196581235f127 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 13 Sep 2019 18:53:03 +0200 Subject: [PATCH 065/190] Revert "habv4: tools: Avoid hardcoded CSF size for SPL targets" This reverts commit 62a52f3f85bf33e286632e99f0d39b2c166af0c4. --- common/image.c | 8 +++----- tools/default_image.c | 5 +---- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/common/image.c b/common/image.c index 9badb915f48..179eef0bd2d 100644 --- a/common/image.c +++ b/common/image.c @@ -61,8 +61,6 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, #endif /* !USE_HOSTCC*/ #include -#include -#include #ifndef CONFIG_SYS_BARGSIZE #define CONFIG_SYS_BARGSIZE 512 @@ -380,9 +378,9 @@ void image_print_contents(const void *ptr) } } else if (image_check_type(hdr, IH_TYPE_FIRMWARE_IVT)) { printf("HAB Blocks: 0x%08x 0x0000 0x%08x\n", - image_get_load(hdr) - image_get_header_size(), - (int)(image_get_size(hdr) + image_get_header_size() - + sizeof(flash_header_v2_t) - CONFIG_CSF_SIZE)); + image_get_load(hdr) - image_get_header_size(), + image_get_size(hdr) + image_get_header_size() + - 0x1FE0); } } diff --git a/tools/default_image.c b/tools/default_image.c index 7a262327798..4b7d1ed4a1a 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include static image_header_t header; @@ -108,8 +106,7 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, if (params->type == IH_TYPE_FIRMWARE_IVT) /* Add size of CSF minus IVT */ - imagesize = sbuf->st_size - sizeof(image_header_t) - + CONFIG_CSF_SIZE - sizeof(flash_header_v2_t); + imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0; else imagesize = sbuf->st_size - sizeof(image_header_t); From 998800108928873d83d2da243623c937510fc3ef Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sun, 7 Apr 2019 16:43:02 -0300 Subject: [PATCH 066/190] pico-imx6ul: Add DWARF baseboard support This add the boot menu option for the DWARF baseboard as well as a specific config file for users which wish to use it as a pre-defined board. Signed-off-by: Otavio Salvador --- configs/pico-dwarf-imx6ul_defconfig | 64 +++++++++++++++++++++++++++++ include/configs/pico-imx6ul.h | 6 ++- 2 files changed, 68 insertions(+), 2 deletions(-) create mode 100644 configs/pico-dwarf-imx6ul_defconfig diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig new file mode 100644 index 00000000000..e7af415abd3 --- /dev/null +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PICO_IMX6UL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb" +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index cd051bf263f..39c83a8c78d 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -63,9 +63,11 @@ "rootfs part 0 1\0" \ #define BOOTMENU_ENV \ - "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ + "bootmenu_0=Boot using PICO-Dwarf baseboard=" \ + "setenv fdtfile imx6ul-pico-dwarf.dtb\0" \ + "bootmenu_1=Boot using PICO-Hobbit baseboard=" \ "setenv fdtfile imx6ul-pico-hobbit.dtb\0" \ - "bootmenu_1=Boot using PICO-Pi baseboard=" \ + "bootmenu_2=Boot using PICO-Pi baseboard=" \ "setenv fdtfile imx6ul-pico-pi.dtb\0" \ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 From 831824c0a795286f4ba2a83c4eefb2162c054f2b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 12 Sep 2019 11:15:54 -0300 Subject: [PATCH 067/190] pico-imx6ul: Increase the CONFIG_ENV_OFFSET size U-Boot binary has grown in such a way that it goes beyond the reserved area for the environment variables. Running "saveenv" causes U-Boot to hang because of this overlap. Fix this problem by increasing the CONFIG_ENV_OFFSET size. Also, in order to prevent this same problem in the future, use CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time. CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare CONFIG_ENV_OFFSET with its direct value instead. Signed-off-by: Fabio Estevam Signed-off-by: Fabio Berton Signed-off-by: Otavio Salvador --- include/configs/pico-imx6ul.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 39c83a8c78d..2666e7ac523 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -134,7 +134,19 @@ /* environment organization */ #define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) +/* Environment starts at 768k = 768 * 1024 = 786432 */ +#define CONFIG_ENV_OFFSET 786432 +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 715776 + #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 0 From 5d1ed3024aa394976dada14a373e5b4cf1353fea Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 9 Sep 2019 22:23:39 -0300 Subject: [PATCH 068/190] pico-imx6ul: Add LCD support Add support for the VXT VL050-8048NT-C01 panel connected through the 24 bit parallel LCDIF interface. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx6ul/pico-imx6ul.c | 55 +++++++++++++++++++++- configs/pico-dwarf-imx6ul_defconfig | 1 + configs/pico-hobbit-imx6ul_defconfig | 1 + configs/pico-imx6ul_defconfig | 1 + configs/pico-pi-imx6ul_defconfig | 1 + include/configs/pico-imx6ul.h | 13 +++++ 6 files changed, 71 insertions(+), 1 deletion(-) diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 95b482a602f..e27a03c2125 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -42,6 +42,9 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + #define RMII_PHY_RESET IMX_GPIO_NR(1, 28) static iomux_v3_cfg_t const fec_pads[] = { @@ -105,6 +108,54 @@ static int setup_fec(void) return 0; } +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + /* LCD_BLT_CTRL: GPIO for Brightness adjustment */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LCD_VDD_EN: LCD enabled */ + MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_lcd(void) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + gpio_request(IMX_GPIO_NR(4, 10), "lcd_brightness"); + gpio_request(IMX_GPIO_NR(1, 11), "lcd_enable"); + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(4, 10) , 1); + /* Set LCD enable to high */ + gpio_direction_output(IMX_GPIO_NR(1, 11) , 1); +} +#endif + int board_phy_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); @@ -214,7 +265,9 @@ int board_init(void) setup_fec(); setup_usb(); - +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif return 0; } diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index e7af415abd3..33bb70bf1f5 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -62,3 +62,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index dda8ef4c4ba..9cf206ae731 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -65,3 +65,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index a0ac01d85d5..81c5110f794 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -67,3 +67,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 7463b3ff0d3..4836050ea5a 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -65,3 +65,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 2666e7ac523..22dfac7fec0 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -75,10 +75,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ + "splashpos=m,m\0" \ "console=ttymxc5\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ BOOTMENU_ENV \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ @@ -151,4 +153,15 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 0 +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#endif + #endif /* __PICO_IMX6UL_CONFIG_H */ From e7cef770fbce18b1484a0fcbf690b7be74816d0a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Sep 2019 14:32:29 -0300 Subject: [PATCH 069/190] pico-imx6ul: Update the Falcon mode instructions Sync the Falcon mode instructions with the ones fro pico-imx7d. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx6ul/README | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/technexion/pico-imx6ul/README b/board/technexion/pico-imx6ul/README index bb8ee3f4634..40d43441429 100644 --- a/board/technexion/pico-imx6ul/README +++ b/board/technexion/pico-imx6ul/README @@ -75,7 +75,7 @@ $ make imx_v6_v7_defconfig (Using the default imx_v6_v7_defconfig configuration just for an example. In order to boot faster the user should customize the defconfig by only enabling the minimal required drivers). -$ make -j4 uImage LOADADDR=0x80800000 +$ make -j4 uImage LOADADDR=0x80008000 $ cp arch/arm/boot/uImage /tftpboot $ cp arch/arm/boot/dts/imx6ul-pico-hobbit.dtb /tftpboot @@ -93,7 +93,7 @@ Get the kernel: => tftp ${loadaddr} uImage Write the kernel at 2MB offset: -=> mmc write ${loadaddr} 0x1000 0x4000 +=> mmc write ${loadaddr} 0x1000 0x5000 Setup the bootargs: => setenv bootargs 'console=ttymxc5,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw' @@ -104,8 +104,8 @@ Prepare args: Image Name: Linux-4.19.0-rc2-next-20180905-0 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 8365608 Bytes = 8 MiB - Load Address: 80800000 - Entry Point: 80800000 + Load Address: 80008000 + Entry Point: 80008000 Verifying Checksum ... OK ## Flattened Device Tree blob at 83000000 Booting using the fdt blob at 0x83000000 From f6432ecea666eb4b7cbe48bde804fb886f0a8cae Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Sep 2019 14:33:44 -0300 Subject: [PATCH 070/190] pico-imx6ul: Provide a way to escape the Falcon mode When CONFIG_SPL_OS_BOOT is selected, it is still convenient to be able to escape from Falcon mode and boot to U-Boot proper. Add a mechanism that allows booting in U-Boot proper when the key 'c' is entered on console at boot time. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx6ul/spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index 284aa40db67..7f520beeb08 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -19,6 +19,10 @@ #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { + /* Break into full U-Boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + return 0; } #endif From cca5c036440462f76cd7c8e77bc618c84f57f894 Mon Sep 17 00:00:00 2001 From: Fabio Berton Date: Fri, 23 Aug 2019 15:01:00 -0300 Subject: [PATCH 071/190] pico-imx7d: Sync pico-hobbit-imx7d_defconfig Update pico-hobbit-imx7d_defconfig using pico-imx7d_defconfig as base to fix device tree file generation. With this all pico-imx7d are creating u-boot-dtb.img files. Signed-off-by: Fabio Berton --- configs/pico-hobbit-imx7d_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 62a942338c9..3ce57d170c3 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-hobbit" +CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 From e82e2927510303e19330c396fa3d10687baa476a Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 11 Apr 2019 09:17:48 -0300 Subject: [PATCH 072/190] pico-imx7d: Add DWARF baseboard support This add the boot menu option for the DWARF baseboard as well as a specific config file for users which wish to use it as a pre-defined board. Signed-off-by: Otavio Salvador --- configs/pico-dwarf-imx7d_defconfig | 68 ++++++++++++++++++++++++++++++ include/configs/pico-imx7d.h | 4 +- 2 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 configs/pico-dwarf-imx7d_defconfig diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig new file mode 100644 index 00000000000..b8a5fb60ad8 --- /dev/null +++ b/configs/pico-dwarf-imx7d_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PICO_IMX7D=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPL_TEXT_BASE=0x00911000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MII is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" +CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 91015402efd..e66fa3e5e15 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -70,7 +70,9 @@ #define PICO_BOOT_ENV \ "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ "setenv fdtfile imx7d-pico-hobbit.dtb\0" \ - "bootmenu_1=Boot using PICO-Pi baseboard=" \ + "bootmenu_1=Boot using PICO-Dwarf baseboard=" \ + "setenv fdtfile imx7d-pico-dwarf.dtb\0" \ + "bootmenu_2=Boot using PICO-Pi baseboard=" \ "setenv fdtfile imx7d-pico-pi.dtb\0" \ BOOTENV #endif From 34ac994245093c3b22ba106dcb66b2b207418b7f Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 11 Apr 2019 09:19:42 -0300 Subject: [PATCH 073/190] pico-imx7d: Add NYMPH baseboard support This add the boot menu option for the NYMPH baseboard as well as a specific config file for users which wish to use it as a pre-defined board. Signed-off-by: Otavio Salvador --- configs/pico-nymph-imx7d_defconfig | 68 ++++++++++++++++++++++++++++++ include/configs/pico-imx7d.h | 4 +- 2 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 configs/pico-nymph-imx7d_defconfig diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig new file mode 100644 index 00000000000..b8a5fb60ad8 --- /dev/null +++ b/configs/pico-nymph-imx7d_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PICO_IMX7D=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPL_TEXT_BASE=0x00911000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MII is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" +CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index e66fa3e5e15..cd86cf2d2d2 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -72,7 +72,9 @@ "setenv fdtfile imx7d-pico-hobbit.dtb\0" \ "bootmenu_1=Boot using PICO-Dwarf baseboard=" \ "setenv fdtfile imx7d-pico-dwarf.dtb\0" \ - "bootmenu_2=Boot using PICO-Pi baseboard=" \ + "bootmenu_2=Boot using PICO-Nymph baseboard=" \ + "setenv fdtfile imx7d-pico-nymph.dtb\0" \ + "bootmenu_3=Boot using PICO-Pi baseboard=" \ "setenv fdtfile imx7d-pico-pi.dtb\0" \ BOOTENV #endif From 26e85def4c8d405936444bf3f5d4c4128f44dfc3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Sep 2019 14:29:52 -0300 Subject: [PATCH 074/190] pico-imx7d: Add instructions for booting in Falcon mode Improve the README by adding instructions on how to boot using Falcon mode, which allows the SPL to load the kernel directly, without using U-Boot proper. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx7d/README | 91 ++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README index 6aa0d25af51..4d57cdbfa89 100644 --- a/board/technexion/pico-imx7d/README +++ b/board/technexion/pico-imx7d/README @@ -66,3 +66,94 @@ Remove power from the pico board. Put pico board into normal boot mode. Power up the board and the new updated U-Boot should boot from eMMC. + +Booting in Falcon mode +====================== + +Generate a uImage kernel: + +$ make imx_v6_v7_defconfig (Using the default imx_v6_v7_defconfig configuration +just for an example. In order to boot faster the user should customize the +defconfig by only enabling the minimal required drivers). + +$ make -j4 uImage LOADADDR=0x80008000 + +$ cp arch/arm/boot/uImage /tftpboot +$ cp arch/arm/boot/dts/imx7d-pico-pi.dtb /tftpboot + +In the U-Boot prompt: + +Setup the server and board IP addresses: +=> setenv serverip 192.168.0.10 +=> setenv ipaddr 192.168.0.11 + +Get the dtb file: +=> tftp ${fdt_addr} imx7d-pico-pi.dtb + +Get the kernel: +=> tftp ${loadaddr} uImage + +Write the kernel at 2MB offset: +=> mmc write ${loadaddr} 0x1000 0x5000 + +Setup the bootargs: +=> setenv bootargs 'console=ttymxc4,115200 root=/dev/mmcblk2p1 rootfstype=ext4 rootwait rw' + +Prepare args: +=> spl export fdt ${loadaddr} - ${fdt_addr} +## Booting kernel from Legacy Image at 80800000 ... + Image Name: Linux-5.2.14 + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 9077544 Bytes = 8.7 MiB + Load Address: 80008000 + Entry Point: 80008000 + Verifying Checksum ... OK +## Flattened Device Tree blob at 83000000 + Booting using the fdt blob at 0x83000000 + Loading Kernel Image + Using Device Tree in place at 83000000, end 8300b615 +subcommand not supported +subcommand not supported + Using Device Tree in place at 83000000, end 8300e615 +Argument image is now in RAM: 0x83000000 +=> + +Write 1MB of args data (0x800 sectors) to 1MB offset (0x800 sectors): + +=> mmc write ${fdt_addr} 0x800 0x800 + +In order to boot with Falcon mode, activate the CONFIG_SPL_OS_BOOT +option in the defconfig + +--- a/configs/pico-imx7d_defconfig ++++ b/configs/pico-imx7d_defconfig +@@ -67,3 +67,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 + CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + CONFIG_CI_UDC=y + CONFIG_VIDEO=y ++CONFIG_SPL_OS_BOOT=y + +Then rebuild U-Boot: + +$ make pico-imx7d_defconfig +$ make -j4 + +Launch UMS: +=> ums 0 mmc 0 + +Flash the new binaries: + +$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync +$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1k seek=69; sync + +And then SPL binary will load and jump directly to the kernel: + +U-Boot SPL 2019.10-rc3-00284-g001c8ea94a-dirty (Sep 10 2019 - 12:46:01 -0300) +Trying to boot from MMC1 +[ 0.000000] Booting Linux on physical CPU 0x0 +[ 0.000000] Linux version 5.2.14 (fabio@fabio-OptiPlex-7010) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #30 SMP Wed Sep 10 12:36:27 -03 2019 +[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d +[ 0.000000] CPU: div instructions available: patching division code +[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache +[ 0.000000] OF: fdt: Machine model: TechNexion PICO-IMX7D Board and PI baseboard +... From b446ce2977e12eba8de6d04d6c608e1b1a766c9f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Sep 2019 14:30:28 -0300 Subject: [PATCH 075/190] pico-imx7d: Provide a way to escape the Falcon mode When CONFIG_SPL_OS_BOOT is selected, it is still convenient to be able to escape from Falcon mode and boot to U-Boot proper. Add a mechanism that allows booting in U-Boot proper when the key 'c' is entered on console at boot time. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx7d/spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index c55a35d864a..8955622b815 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -21,6 +21,10 @@ #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { + /* Break into full U-Boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + return 0; } #endif From dc3e6c8305dc739efce8f6395d52e9880af9f7f1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Dec 2018 00:06:49 -0200 Subject: [PATCH 076/190] logos: Add the TechNexion's logo Add the TechNexion's logo from their internal U-Boot tree. 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zx*OqguI0{kv%hg12PM{ZWw0{^jTIAwhGQYEW~ScgrDg?1srOy~OZflu|LIk*EtoIeQT(Nn4^NQ= zoHbPkM(Ayx>gIST?r$^u3hs3$Ai5im5}+)UI{g!yEN}d!l1o>W*tYXWsYwDSe9Xvp z_E{lr@pjn1cjcR_4cr@`0=@-BLoE-K&hi~?4w&)1zW(VYPpfuS9Q=8dQM>iMbuJ4# zMwYlWiF`t?fm{Q*267GL8pt(}YarJ^u7O+wxdw6# Date: Sat, 14 Sep 2019 09:14:19 -0300 Subject: [PATCH 077/190] pico: Convert to CONFIG_FSL_USDHC The eSDHC config symbol has been converted to CONFIG_FSL_USDHC, so adjust it accordingly in order to fix the build errors: https://travis-ci.org/sbabic/u-boot-imx/jobs/584781580#L1287 Reported-by: Anatolij Gustschin Signed-off-by: Fabio Estevam --- configs/pico-dwarf-imx6ul_defconfig | 2 +- configs/pico-dwarf-imx7d_defconfig | 2 +- configs/pico-nymph-imx7d_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index 33bb70bf1f5..f1f6506868f 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -44,7 +44,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index b8a5fb60ad8..3ba7adcc256 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -52,7 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index b8a5fb60ad8..3ba7adcc256 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -52,7 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y From 42899127154563daad80ad63d4b1a6f361ab19e8 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 14 Sep 2019 13:30:49 +0200 Subject: [PATCH 078/190] imx: sksimx6_defconfig: remove SPL misc option to fix build error Remove CONFIG_SPL_DRIVERS_MISC_SUPPORT since it is already defined in include/configs/mx6_common.h for SPL builds. When this option is in defconfig, we get build warnings (or errors when building with -Werror). Signed-off-by: Anatolij Gustschin --- configs/sksimx6_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig index 5fbc94ae856..d8739fdae98 100644 --- a/configs/sksimx6_defconfig +++ b/configs/sksimx6_defconfig @@ -8,7 +8,6 @@ CONFIG_MX6_DDRCAL=y CONFIG_TARGET_SKSIMX6=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y From 95fd8326eefc89a04276bcce434037751e48e1ce Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 16 Sep 2019 08:36:23 +0200 Subject: [PATCH 079/190] imx: fix missing MAINTAINERS pico boards Add missing files pico-nymph-imx7d_defconfig and c>onfigs/pico-dwarf-imx7d_defconfig Signed-off-by: Stefano Babic Reviewed-by: Peng Fan CC: Fabio Estevam CC: Otavio Salvador --- board/technexion/pico-imx7d/MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/technexion/pico-imx7d/MAINTAINERS b/board/technexion/pico-imx7d/MAINTAINERS index 6e7316be9f6..325e1735c39 100644 --- a/board/technexion/pico-imx7d/MAINTAINERS +++ b/board/technexion/pico-imx7d/MAINTAINERS @@ -8,3 +8,5 @@ F: configs/pico-imx7d_defconfig F: configs/pico-imx7d_bl33_defconfig F: configs/pico-hobbit-imx7d_defconfig F: configs/pico-pi-imx7d_defconfig +F: configs/pico-nymph-imx7d_defconfig +F: configs/pico-dwarf-imx7d_defconfig From a89b1feabb87f31e32900f5c06790bd88b9aa5b8 Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Fri, 30 Aug 2019 14:39:49 +0200 Subject: [PATCH 080/190] ARM: dts: pico-imx7d: Add u-boot.dtsi for uboot specific dts change This commit introduce u-boot.dtsi Signed-off-by: Joris Offouga Suggested-by: Peng Fan --- arch/arm/dts/imx7d-pico-u-boot.dtsi | 11 +++++++++++ arch/arm/dts/imx7d-pico.dtsi | 8 +------- 2 files changed, 12 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/imx7d-pico-u-boot.dtsi diff --git a/arch/arm/dts/imx7d-pico-u-boot.dtsi b/arch/arm/dts/imx7d-pico-u-boot.dtsi new file mode 100644 index 00000000000..1bd7f4f1026 --- /dev/null +++ b/arch/arm/dts/imx7d-pico-u-boot.dtsi @@ -0,0 +1,11 @@ +/{ + aliases { + mmc0 = &usdhc3; + usb0 = &usbotg1; + }; +}; + +&usbotg1 { + dr_mode = "peripheral"; + }; + diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi index 7cd8be24c87..33b308ac24e 100644 --- a/arch/arm/dts/imx7d-pico.dtsi +++ b/arch/arm/dts/imx7d-pico.dtsi @@ -5,14 +5,9 @@ /dts-v1/; #include "imx7d.dtsi" - +#include "imx7d-pico-u-boot.dtsi" / { - aliases { - mmc0 = &usdhc3; - usb0 = &usbotg1; - }; - /* Will be filled by the bootloader */ memory@80000000 { device_type = "memory"; @@ -297,7 +292,6 @@ &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; - dr_mode = "peripheral"; status = "okay"; }; From 8787a70c521ab728f9b00ec837efd175d30e94d4 Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Fri, 30 Aug 2019 14:42:59 +0200 Subject: [PATCH 081/190] ARM: dts: pico-imx7d: sync device tree with v5.3-rc6 Synchronize device tree with v5.3-rc6 label Signed-off-by: Joris Offouga --- arch/arm/dts/imx7d-pico.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi index 33b308ac24e..57391fc0524 100644 --- a/arch/arm/dts/imx7d-pico.dtsi +++ b/arch/arm/dts/imx7d-pico.dtsi @@ -93,7 +93,7 @@ <&clks IMX7D_ENET1_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,magic-packet; phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; From d89f0a889f30c58a3c0f9e4ce72b938dc5f05094 Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Fri, 30 Aug 2019 14:44:36 +0200 Subject: [PATCH 082/190] configs: pico-imx7d: Convert to DM_VIDEO This commit convert all pico-imx7d to DM_VIDEO Signed-off-by: Joris Offouga --- arch/arm/dts/imx7d-pico-u-boot.dtsi | 113 +++++++++++++++++++++++ board/technexion/pico-imx7d/pico-imx7d.c | 48 ++++------ configs/pico-dwarf-imx7d_defconfig | 2 +- configs/pico-hobbit-imx7d_defconfig | 2 +- configs/pico-imx7d_bl33_defconfig | 2 +- configs/pico-imx7d_defconfig | 2 +- configs/pico-nymph-imx7d_defconfig | 2 +- configs/pico-pi-imx7d_defconfig | 2 +- include/configs/pico-imx7d.h | 2 +- 9 files changed, 137 insertions(+), 38 deletions(-) diff --git a/arch/arm/dts/imx7d-pico-u-boot.dtsi b/arch/arm/dts/imx7d-pico-u-boot.dtsi index 1bd7f4f1026..ef19de2b308 100644 --- a/arch/arm/dts/imx7d-pico-u-boot.dtsi +++ b/arch/arm/dts/imx7d-pico-u-boot.dtsi @@ -2,10 +2,123 @@ aliases { mmc0 = &usdhc3; usb0 = &usbotg1; + display0 = &lcdif; }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm4 0 50000 0>; + brightness-levels = <0 36 72 108 144 180 216 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel { + compatible = "vxt,vl050-8048nt-c01"; + backlight = <&backlight>; + power-supply = <®_lcd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; }; &usbotg1 { dr_mode = "peripheral"; }; +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + display = <&display0>; + u-boot,dm-pre-reloc; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <11>; + hfront-porch = <11>; + vback-porch = <12>; + vfront-porch = <11>; + hsync-len = <46>; + vsync-len = <210>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + interlaced = <0>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_backlight: backlight { + fsl,pins = < + MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0 + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78 + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 + >; + }; + +}; diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 216475c8dec..916220516e4 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -19,6 +19,10 @@ #include #include #include "../../freescale/common/pfuze.h" +#ifdef CONFIG_DM_VIDEO +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -223,37 +227,8 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_VIDEO_MXS +#ifdef CONFIG_DM_VIDEO static iomux_v3_cfg_t const lcd_pads[] = { - MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL), - MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL), - MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL), - MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL), MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -274,8 +249,19 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_VIDEO_MXS +#ifdef CONFIG_DM_VIDEO + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; + setup_lcd(); + + ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, 0, 0, true); + if (ret) + return ret; #endif #ifdef CONFIG_FEC_MXC setup_fec(); diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 3ba7adcc256..e59ef5783d5 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -65,4 +65,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 3ce57d170c3..f3ed298087b 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -66,4 +66,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index a2cddfcf4f3..ba347d2507e 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -62,5 +62,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 37854775ddb..1e54bcc0312 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -66,4 +66,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 3ba7adcc256..e59ef5783d5 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -65,4 +65,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index cf20fd2c6bd..c44bc778ca1 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -66,4 +66,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index cd86cf2d2d2..956c383a312 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -167,7 +167,7 @@ #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -#ifdef CONFIG_VIDEO +#ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO #define CONFIG_SPLASH_SCREEN From 9b1fd3c834d29644436ac3aae7469bb07eed79a7 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 16 Sep 2019 08:14:48 -0300 Subject: [PATCH 083/190] configs: Sync all baseboard specific pico-imx7d This syncs all baseboard specific defconfig using the pico-imx7d_defconfig as base. It changes: - pico-dwarf-imx7d_defconfig - pico-hobbit-imx7d_defconfig - pico-nymph-imx7d_defconfig - pico-pi-imx7d_defconfig Signed-off-by: Otavio Salvador --- configs/pico-dwarf-imx7d_defconfig | 3 ++- configs/pico-nymph-imx7d_defconfig | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index e59ef5783d5..97de873e7cb 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -12,12 +12,12 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_BOUNCE_BUFFER=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y @@ -58,6 +58,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_GADGET=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index e59ef5783d5..97de873e7cb 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -12,12 +12,12 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_BOUNCE_BUFFER=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y @@ -58,6 +58,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_GADGET=y From 31bd001b21272dacdf74e2795323ec10ff887605 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 20 Sep 2019 08:51:29 +0200 Subject: [PATCH 084/190] board: imx6dl_mamoj: set the value for CSF size Default value is too high and it covers the worst case. SPL for imx6dl_mamoj becomes too big and cannot fit into the OCRAM, but CSF size can be reduced. Signed-off-by: Stefano Babic CC: Jagan Teki CC: Breno Lima --- configs/imx6dl_mamoj_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index b568dfdc956..983d98536ce 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SECURE_BOOT=y CONFIG_TARGET_MX6DL_MAMOJ=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_CSF_SIZE=0x2060 # CONFIG_CMD_BMODE is not set CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_DISTRO_DEFAULTS=y From 033f6ea5fa5fce63d52c8c2b63d8284144415b88 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 30 Aug 2019 13:58:29 -0300 Subject: [PATCH 085/190] mx53loco: Fix U-Boot corruption after saving the environment U-Boot binary has grown in such a way that it goes beyond the reserved area for the environment variables. Running "saveenv" causes U-Boot to hang because of this overlap. Fix this problem by increasing the CONFIG_ENV_OFFSET size. Also, in order to prevent this same problem in the future, use CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time. CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare CONFIG_ENV_OFFSET with its direct value instead. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- include/configs/mx53loco.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index b734b822ddf..65a5993f614 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -163,8 +163,18 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +/* Environment starts at 768k = 768 * 1024 = 786432 */ +#define CONFIG_ENV_OFFSET 786432 +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 From b8bffab76fcde37fba3a2d4afcb8dbaa7c5c08d8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 12 Jul 2019 09:10:35 -0300 Subject: [PATCH 086/190] mx6: clock: Allow enable_ipu_clock() to be built for SPL code Allow enable_ipu_clock() to be built for SPL code. This is done in preparation for configuring the NoC registers on i.MX6QP in SPL. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- arch/arm/mach-imx/mx6/clock.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 366a4e3c6b9..5af1ae7cf38 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1275,6 +1275,22 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return 0; } +#ifndef CONFIG_MX6SX +void enable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; + writel(reg, &mxc_ccm->CCGR3); + + if (is_mx6dqp()) { + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + } +} +#endif + #ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. @@ -1311,22 +1327,6 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#ifndef CONFIG_MX6SX -void enable_ipu_clock(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; - writel(reg, &mxc_ccm->CCGR3); - - if (is_mx6dqp()) { - setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); - } -} -#endif - #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) static void disable_ldb_di_clock_sources(void) From 004eee86f1181f712345370163baa0d158716196 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 10 Jun 2019 22:24:12 -0300 Subject: [PATCH 087/190] pico-imx6: Add initial support Add the initial support for the pico-imx6 variants. DDR initialization is based on the TechNexion's U-Boot code. Signed-off-by: Fabio Estevam Signed-off-by: Fabio Berton Signed-off-by: Otavio Salvador --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6dl-pico.dts | 17 + arch/arm/dts/imx6q-pico.dts | 17 + arch/arm/dts/imx6qdl-pico.dtsi | 424 +++++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/technexion/pico-imx6/Kconfig | 15 + board/technexion/pico-imx6/MAINTAINERS | 9 + board/technexion/pico-imx6/Makefile | 5 + board/technexion/pico-imx6/README | 73 +++++ board/technexion/pico-imx6/pico-imx6.c | 78 +++++ board/technexion/pico-imx6/spl.c | 303 ++++++++++++++++++ configs/pico-imx6_defconfig | 71 +++++ include/configs/pico-imx6.h | 130 ++++++++ 13 files changed, 1155 insertions(+) create mode 100644 arch/arm/dts/imx6dl-pico.dts create mode 100644 arch/arm/dts/imx6q-pico.dts create mode 100644 arch/arm/dts/imx6qdl-pico.dtsi create mode 100644 board/technexion/pico-imx6/Kconfig create mode 100644 board/technexion/pico-imx6/MAINTAINERS create mode 100644 board/technexion/pico-imx6/Makefile create mode 100644 board/technexion/pico-imx6/README create mode 100644 board/technexion/pico-imx6/pico-imx6.c create mode 100644 board/technexion/pico-imx6/spl.c create mode 100644 configs/pico-imx6_defconfig create mode 100644 include/configs/pico-imx6.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 90e877322be..7a0b05b8cac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -560,6 +560,7 @@ dtb-y += \ imx6dl-icore-rqs.dtb \ imx6dl-mamoj.dtb \ imx6dl-nitrogen6x.dtb \ + imx6dl-pico.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ imx6dl-wandboard-revb1.dtb \ @@ -578,6 +579,7 @@ dtb-y += \ imx6q-logicpd.dtb \ imx6q-nitrogen6x.dtb \ imx6q-novena.dtb \ + imx6q-pico.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ diff --git a/arch/arm/dts/imx6dl-pico.dts b/arch/arm/dts/imx6dl-pico.dts new file mode 100644 index 00000000000..43763c1faa6 --- /dev/null +++ b/arch/arm/dts/imx6dl-pico.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo"; + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-pico.dts b/arch/arm/dts/imx6q-pico.dts new file mode 100644 index 00000000000..bfc6f9c744a --- /dev/null +++ b/arch/arm/dts/imx6q-pico.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad"; + compatible = "technexion,imx6q-pico", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6qdl-pico.dtsi b/arch/arm/dts/imx6qdl-pico.dtsi new file mode 100644 index 00000000000..50379d04b70 --- /dev/null +++ b/arch/arm/dts/imx6qdl-pico.dtsi @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen + +#include + +/ { + aliases { + mmc0 = &usdhc3; + usb0 = &usbotg; + }; + + chosen { + stdout-path = &uart1; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reset>; + reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { /* Bluetooth module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { /* Wifi/BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x4001b0b5 /* PICO_P25 */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie_reset: pciegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 36e1c98fb59..01f0121beb6 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -422,6 +422,16 @@ config TARGET_OT1200 select SUPPORT_SPL imply CMD_SATA +config TARGET_PICO_IMX6 + bool "PICO-IMX6" + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select MX6QDL + select SUPPORT_SPL + imply CMD_DM + config TARGET_PICO_IMX6UL bool "PICO-IMX6UL-EMMC" select MX6UL @@ -609,6 +619,7 @@ source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/sks-kinkel/sksimx6/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" +source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" diff --git a/board/technexion/pico-imx6/Kconfig b/board/technexion/pico-imx6/Kconfig new file mode 100644 index 00000000000..4af18e53bcf --- /dev/null +++ b/board/technexion/pico-imx6/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PICO_IMX6 + +config SYS_BOARD + default "pico-imx6" + +config SYS_VENDOR + default "technexion" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "pico-imx6" + +endif diff --git a/board/technexion/pico-imx6/MAINTAINERS b/board/technexion/pico-imx6/MAINTAINERS new file mode 100644 index 00000000000..dd6fb96e441 --- /dev/null +++ b/board/technexion/pico-imx6/MAINTAINERS @@ -0,0 +1,9 @@ +TECHNEXION PICO-IMX6 BOARD +M: Fabio Estevam +S: Maintained +F: arch/arm/dts/imx6qdl-pico.dtsi +F: arch/arm/dts/imx6q-pico.dts +F: arch/arm/dts/imx6dl-pico.dts +F: board/technexion/pico-imx6/ +F: include/configs/pico-imx6.h +F: configs/pico-imx6_defconfig diff --git a/board/technexion/pico-imx6/Makefile b/board/technexion/pico-imx6/Makefile new file mode 100644 index 00000000000..ddb1604f1df --- /dev/null +++ b/board/technexion/pico-imx6/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. + +obj-y := pico-imx6.o spl.o diff --git a/board/technexion/pico-imx6/README b/board/technexion/pico-imx6/README new file mode 100644 index 00000000000..f1e84bfe829 --- /dev/null +++ b/board/technexion/pico-imx6/README @@ -0,0 +1,73 @@ +How to Update U-Boot on pico-imx6q/dl boards +-------------------------------------------- + +Required software on the host PC: + +- UUU: https://github.com/NXPmicro/mfgtools + +Build U-Boot for pico: + +$ make mrproper +$ make pico-imx6_defconfig +$ make + +This generates the SPL and u-boot-dtb.img binaries. + +1. Loading U-Boot via USB Serial Download Protocol + +Note: This method is convenient for development purposes. +If the eMMC has already a U-Boot flashed then the user can +go to step 2 below in order to update U-Boot. + +Put pico board in USB download mode (Refer to the following link for details: +https://www.technexion.com/support/knowledgebase/boot-configuration-settings-for-pico-baseboards/). + +Connect a USB to serial adapter between the host PC and pico. + +Connect a USB cable between the OTG pico port and the host PC. + +Open a terminal program such as minicom. + +Copy SPL and u-boot-dtb.img to the uuu folder. + +Load the U-Boot via USB: + +$ sudo ./uuu -v uuu_script + +where uuu_script contains the following: + +SDP: boot -f SPL +SDPU: write -f u-boot-dtb.img -addr 0x10000000 +SDPU: jump -addr 0x10000000 + +Then U-Boot starts and its messages appear in the console program. + +Use the default environment variables: + +=> env default -f -a +=> saveenv + +2. Flashing U-Boot into the eMMC + +The default U-Boot environment expects the use of eMMC user +partition. To ensure we are using the proper eMMC partition for boot, +please run: + +=> mmc partconf 0 0 0 0 + +Next, run the DFU agent so we can flash the new images using dfu-util +tool: + +=> dfu 0 mmc 0 + +Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC: + +$ sudo dfu-util -D SPL -a spl + +$ sudo dfu-util -D u-boot-dtb.img -a u-boot + +Remove power from the pico board. + +Put pico board into normal boot mode. + +Power up the board and the new updated U-Boot should boot from eMMC. diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c new file mode 100644 index 00000000000..717f20d9d71 --- /dev/null +++ b/board/technexion/pico-imx6/pico-imx6.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014 O.S. Systems Software LTDA. + * + * Author: Fabio Estevam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int overwrite_console(void) +{ + return 1; +} + +int board_late_init(void) +{ + if (is_mx6dq()) + env_set("board_rev", "MX6Q"); + else + env_set("board_rev", "MX6DL"); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: PICO-IMX6\n"); + + return 0; +} diff --git a/board/technexion/pico-imx6/spl.c b/board/technexion/pico-imx6/spl.c new file mode 100644 index 00000000000..5bf87023acb --- /dev/null +++ b/board/technexion/pico-imx6/spl.c @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Technexion Ltd. + * + * Author: Richard Hu + * Fabio Estevam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPL_BUILD) +#include + +#define IMX6DQ_DRIVE_STRENGTH 0x30 +#define IMX6SDL_DRIVE_STRENGTH 0x28 + +/* configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, + .dram_cas = IMX6DQ_DRIVE_STRENGTH, + .dram_ras = IMX6DQ_DRIVE_STRENGTH, + .dram_reset = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6DQ_DRIVE_STRENGTH, + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, + .dram_cas = IMX6SDL_DRIVE_STRENGTH, + .dram_ras = IMX6SDL_DRIVE_STRENGTH, + .dram_reset = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6SDL_DRIVE_STRENGTH, + .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, +}; + +/* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */ +static struct mx6_ddr3_cfg h5t04g63afr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1500, + .trcmin = 5250, + .trasmin = 3750, +}; + +/* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */ +static struct mx6_ddr3_cfg h5tq2g63ffr = { + .mem_speed = 800, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1500, + .trcmin = 5250, + .trasmin = 3750, +}; + +static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpwldectrl1 = 0x00000000, + .p1_mpwldectrl0 = 0x00000000, + .p1_mpwldectrl1 = 0x00000000, + .p0_mpdgctrl0 = 0x032C0340, + .p0_mpdgctrl1 = 0x03300324, + .p1_mpdgctrl0 = 0x032C0338, + .p1_mpdgctrl1 = 0x03300274, + .p0_mprddlctl = 0x423A383E, + .p1_mprddlctl = 0x3638323E, + .p0_mpwrdlctl = 0x363C4640, + .p1_mpwrdlctl = 0x4034423C, +}; + +/* DDR 32bit */ +static struct mx6_ddr_sysinfo mem_s = { + .dsize = 1, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { + .p0_mpwldectrl0 = 0x001f001f, + .p0_mpwldectrl1 = 0x001f001f, + .p1_mpwldectrl0 = 0x001f001f, + .p1_mpwldectrl1 = 0x001f001f, + .p0_mpdgctrl0 = 0x420e020e, + .p0_mpdgctrl1 = 0x02000200, + .p1_mpdgctrl0 = 0x42020202, + .p1_mpdgctrl1 = 0x01720172, + .p0_mprddlctl = 0x494c4f4c, + .p1_mprddlctl = 0x4a4c4c49, + .p0_mpwrdlctl = 0x3f3f3133, + .p1_mpwrdlctl = 0x39373f2e, +}; + +static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = { + .p0_mpwldectrl0 = 0x0040003c, + .p0_mpwldectrl1 = 0x0032003e, + .p0_mpdgctrl0 = 0x42350231, + .p0_mpdgctrl1 = 0x021a0218, + .p0_mprddlctl = 0x4b4b4e49, + .p0_mpwrdlctl = 0x3f3f3035, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF03000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + if (is_mx6solo()) { + mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr); + } else if (is_mx6dl()) { + mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr); + } else if (is_mx6dq()) { + mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr); + } + + udelay(100); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + gpr_init(); + + /* iomux */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* SOM MicroSD Card Detect */ + IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (is_mx6dq() && !strcmp(name, "imx6q-pico")) + return 0; + else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico")) + return 0; + + return -EINVAL; +} +#endif diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig new file mode 100644 index 00000000000..a0448b22363 --- /dev/null +++ b/configs/pico-imx6_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PICO_IMX6=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_FIT_PRINT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTCOMMAND="run findbaseboard; run findfdt; run finduuid; run distro_bootcmd" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_DEFAULT_FDT_FILE="ask" +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_FIT_IMAGE_TINY=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-pico" +CONFIG_OF_LIST="imx6dl-pico imx6q-pico" +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h new file mode 100644 index 00000000000..2ea50f54889 --- /dev/null +++ b/include/configs/pico-imx6.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the pico-imx6 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=" \ + "spl raw 0x2 0x400;" \ + "u-boot raw 0x8a 0x1000;" \ + "/boot/zImage ext4 0 1;" \ + "rootfs part 0 1\0" \ + +#define BOOTMENU_ENV \ + "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ + "setenv baseboard hobbit\0" \ + "bootmenu_1=Boot using PICO-Pi baseboard=" \ + "setenv baseboard pi\0" \ + "bootmenu_2=Boot using PICO-Dwarf baseboard=" \ + "setenv baseboard dwarf\0" \ + "bootmenu_3=Boot using PICO-Nymph baseboard=" \ + "setenv baseboard nymph\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTMENU_ENV \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + CONFIG_DFU_ENV_SETTINGS \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "findbaseboard=" \ + "if test $baseboard = ask ; then " \ + "bootmenu -1; fi;" \ + "if test $baseboard != ask ; then " \ + "saveenv; fi;\0" \ + "findfdt="\ + "if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-hobbit.dtb; fi; " \ + "if test $baseboard = pi && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-pi.dtb; fi; " \ + "if test $baseboard = dwarf && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-dwarf.dtb; fi; " \ + "if test $baseboard = nymph && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-nymph.dtb; fi; " \ + "if test $baseboard = hobbit && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-hobbit.dtb; fi; " \ + "if test $baseboard = pi && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-pi.dtb; fi; " \ + "if test $baseboard = dwarf && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-dwarf.dtb; fi; " \ + "if test $baseboard = nymph && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-nymph.dtb; fi; " \ + "if test $fdtfile = ask; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) + +#include + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (8 * 1024) + +/* Environment starts at 768k = 768 * 1024 = 786432 */ +#define CONFIG_ENV_OFFSET 786432 +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 715776 +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif /* __CONFIG_H * */ From 7efe52a0a7142354e428ed81f8d84a22884b8be3 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Wed, 19 Jun 2019 15:03:44 -0300 Subject: [PATCH 088/190] pico-imx6: Fix bootmenu handling We should use a common script to allow booting the U-Boot console as fallback so we ended using a 'default_boot' and 'base_boot' environment scripts to accomplish that. Signed-off-by: Fabio Berton Signed-off-by: Otavio Salvador --- configs/pico-imx6_defconfig | 2 +- include/configs/pico-imx6.h | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index a0448b22363..4291f6fab06 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -15,7 +15,7 @@ CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTCOMMAND="run findbaseboard; run findfdt; run finduuid; run distro_bootcmd" +CONFIG_BOOTCOMMAND="run default_boot" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_DEFAULT_FDT_FILE="ask" diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 2ea50f54889..d151da07f27 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -42,13 +42,13 @@ #define BOOTMENU_ENV \ "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ - "setenv baseboard hobbit\0" \ + "setenv baseboard hobbit; saveenv; run base_boot\0" \ "bootmenu_1=Boot using PICO-Pi baseboard=" \ - "setenv baseboard pi\0" \ + "setenv baseboard pi; saveenv; run base_boot\0" \ "bootmenu_2=Boot using PICO-Dwarf baseboard=" \ - "setenv baseboard dwarf\0" \ + "setenv baseboard dwarf; saveenv; run base_boot\0" \ "bootmenu_3=Boot using PICO-Nymph baseboard=" \ - "setenv baseboard nymph\0" \ + "setenv baseboard nymph; saveenv; run base_boot\0" \ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ @@ -61,11 +61,6 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ CONFIG_DFU_ENV_SETTINGS \ "finduuid=part uuid mmc 0:1 uuid\0" \ - "findbaseboard=" \ - "if test $baseboard = ask ; then " \ - "bootmenu -1; fi;" \ - "if test $baseboard != ask ; then " \ - "saveenv; fi;\0" \ "findfdt="\ "if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \ "setenv fdtfile imx6q-pico-hobbit.dtb; fi; " \ @@ -85,6 +80,13 @@ "setenv fdtfile imx6dl-pico-nymph.dtb; fi; " \ "if test $fdtfile = ask; then " \ "echo WARNING: Could not determine dtb to use; fi; \0" \ + "default_boot=" \ + "if test $baseboard = ask ; then " \ + "bootmenu -1; " \ + "else " \ + "run base_boot;" \ + "fi; \0" \ + "base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ From d9033f2f422eb3d82c9e914a85ab73bcf7b2a1d5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 16 Sep 2019 14:15:00 -0300 Subject: [PATCH 089/190] pico-imx6: Add Ethernet support Add Ethernet support. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx6/pico-imx6.c | 74 ++++++++++++++++++++++++++ include/configs/pico-imx6.h | 10 ++++ 2 files changed, 84 insertions(+) diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c index 717f20d9d71..2ae5af83d2f 100644 --- a/board/technexion/pico-imx6/pico-imx6.c +++ b/board/technexion/pico-imx6/pico-imx6.c @@ -17,6 +17,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -24,6 +27,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ETH_PHY_RESET IMX_GPIO_NR(1, 26) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -41,6 +49,39 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* AR8035 PHY Reset */ + IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + + /* Reset AR8031 PHY */ + gpio_request(ETH_PHY_RESET, "enet_phy_reset"); + gpio_direction_output(ETH_PHY_RESET, 0); + udelay(500); + gpio_set_value(ETH_PHY_RESET, 1); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -48,6 +89,39 @@ int board_early_init_f(void) return 0; } +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe7; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + int overwrite_console(void) { return 1; diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index d151da07f27..d539b88bf77 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -129,4 +129,14 @@ #define CONFIG_BOARD_SIZE_LIMIT 715776 #define CONFIG_SYS_MMC_ENV_DEV 0 +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + #endif /* __CONFIG_H * */ From 953c2500bc0c0d72d9099319381542feb9905ea3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 17 Sep 2019 14:17:07 -0300 Subject: [PATCH 090/190] pico-imx6: Add splashscreen support Add splashscreen support. Tested with the parallel FT5x06-WVGA panel. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx6/pico-imx6.c | 210 +++++++++++++++++++++++++ configs/pico-imx6_defconfig | 2 + include/configs/pico-imx6.h | 10 ++ 3 files changed, 222 insertions(+) diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c index 2ae5af83d2f..f8eeb40555b 100644 --- a/board/technexion/pico-imx6/pico-imx6.c +++ b/board/technexion/pico-imx6/pico-imx6.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -31,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) #define ETH_PHY_RESET IMX_GPIO_NR(1, 26) +#define LVDS0_EN IMX_GPIO_NR(2, 8) +#define LVDS0_BL_EN IMX_GPIO_NR(2, 9) int dram_init(void) { @@ -49,6 +53,15 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } +static iomux_v3_cfg_t const lvds_pads[] = { + /* lvds */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), @@ -82,10 +95,207 @@ static void setup_iomux_enet(void) gpio_set_value(ETH_PHY_RESET, 1); } +#if defined(CONFIG_VIDEO_IPUV3) +static iomux_v3_cfg_t const ft5x06_wvga_pads[] = { + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */ + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */ + IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */ + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */ + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), + IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18), + IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19), + IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20), + IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21), + IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22), + IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23), + IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */ +}; + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + + /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + + /* Enable Backlight - use GPIO for Brightness adjustment */ + SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09); + gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable"); + gpio_direction_output(IMX_GPIO_NR(2, 9), 1); + + gpio_request(IMX_GPIO_NR(2, 8), "brightness"); + SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08); + gpio_direction_output(IMX_GPIO_NR(2, 8), 1); +} + +static void enable_ft5x06_wvga(struct display_info_t const *dev) +{ + SETUP_IOMUX_PADS(ft5x06_wvga_pads); + + gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable"); + gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness"); + gpio_direction_output(IMX_GPIO_NR(2, 10), 1); + gpio_direction_output(IMX_GPIO_NR(2, 11), 1); +} + +struct display_info_t const displays[] = {{ + .bus = 1, + .addr = 0x38, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_ft5x06_wvga, + .mode = { + .name = "FT5x06-WVGA", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30303, + .left_margin = 45, + .right_margin = 210, + .upper_margin = 22, + .lower_margin = 22, + .hsync_len = 1, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "hj070na", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ + SETUP_IOMUX_PADS(lvds_pads); + gpio_request(LVDS0_EN, "lvds0_enable"); + gpio_request(LVDS0_BL_EN, "lvds0_bl_enable"); + gpio_direction_output(LVDS0_EN, 1); + gpio_direction_output(LVDS0_BL_EN, 1); + + enable_ipu_clock(); + imx_setup_hdmi(); + + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + reg = readl(&iomux->gpr[3]); + + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; } diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 4291f6fab06..02787f8250e 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -69,3 +69,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index d539b88bf77..467d5ff4f59 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -139,4 +139,14 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS +/* Framebuffer */ +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + #endif /* __CONFIG_H * */ From 77ecf95f22dc5cb0a9709805dd22555007d60b34 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 17 Sep 2019 22:04:57 -0300 Subject: [PATCH 091/190] pico-imx6: Add Falcon mode Add Falcon mode support, which allows the SPL to load and jump to the Linux kernel directly, without the need of loading U-Boot proper. CONFIG_SPL_OS_BOOT=y needs to be passed in the defconfig in order to use Falcon mode. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx6/spl.c | 11 +++++++++++ include/configs/pico-imx6.h | 12 ++++++++++++ 2 files changed, 23 insertions(+) diff --git a/board/technexion/pico-imx6/spl.c b/board/technexion/pico-imx6/spl.c index 5bf87023acb..06ad0a8c322 100644 --- a/board/technexion/pico-imx6/spl.c +++ b/board/technexion/pico-imx6/spl.c @@ -27,6 +27,17 @@ #define IMX6DQ_DRIVE_STRENGTH 0x30 #define IMX6SDL_DRIVE_STRENGTH 0x28 +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* Break into full U-Boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif + /* configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 467d5ff4f59..5bbb9ea8f70 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -12,6 +12,18 @@ #include "imx6_spl.h" +#ifdef CONFIG_SPL_OS_BOOT +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ From 1ff6c1f75b292cd789995689770bfbcd90d2421d Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Sun, 28 Jul 2019 00:17:05 +0200 Subject: [PATCH 092/190] imx: bk4: Print proper HW revision of VF610's BK4 board This code uses HW difference on the USB_RESET pin (added PULL UP resistor on the L333 rev) to distinguish between two BK4 HW revisions. Signed-off-by: Lukasz Majewski --- board/phytec/pcm052/pcm052.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index e1ebe8e75d0..b52432e6536 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -403,7 +403,20 @@ int board_phy_config(struct phy_device *phydev) int checkboard(void) { #ifdef CONFIG_TARGET_BK4R1 - puts("Board: BK4r1 (L333)\n"); + u32 *gpio3_pdir = (u32 *)(GPIO3_BASE_ADDR + 0x10); + + /* + * USB_RESET_N (PTC30 - GPIO103 - PORT3[7]): + * L333 -> pull up added -> read 1 + * L320 -> no pull up -> read 0 + * + * Default iomuxc_ptc30 value after reset: 0x300061 -> RCON28 + * - input enabled, pull (up/down) disabled + */ + if (*gpio3_pdir & BIT(7)) + puts("Board: BK4r1 (L333)\n"); + else + puts("Board: BK4r1 (L320)\n"); #else puts("Board: PCM-052\n"); #endif From 4c3c29e3b04f34e1aa4bcc0096db7197f65619da Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:37 +0200 Subject: [PATCH 093/190] fix: defconfig: Enable OF_CONTROL for display5_factory This change fixes issue with building display5 "factory" U-Boot variant when the display5 board gains DM/DTS support. Signed-off-by: Lukasz Majewski --- configs/display5_factory_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 5b790570741..070de97e5b5 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -62,6 +62,8 @@ CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),4m(swu-kernel),16m(swu-initramfs),1m(factory),-(reserved)" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y @@ -88,4 +90,3 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y From 5ca7094668401f68aa9b8380114097270fcd0d36 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:38 +0200 Subject: [PATCH 094/190] ARM: imx: defconfig: Enable CONFIG_PINCTRL{_IMX6} on display5's defconfig Enable PINCTRL for i.MX6 soc based display5 after DM/DTS conversion. Signed-off-by: Lukasz Majewski --- configs/display5_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/display5_defconfig b/configs/display5_defconfig index e48b6467e6d..6703251e0a2 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -46,6 +46,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y @@ -79,6 +80,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y From dac9a8f8a2ae3a116748d056305251cfc035a6e4 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:39 +0200 Subject: [PATCH 095/190] DM: I2C: Switch display5 board to use DM_I2C After this commit the display5 device would use I2C driver supporting driver model (DM_I2C). The 'i2c' and 'eeprom' commands now use DM I2C drivers and initialize on-bus devices according to device tree description. Signed-off-by: Lukasz Majewski --- arch/arm/mach-imx/mx6/Kconfig | 2 ++ board/liebherr/display5/display5.c | 48 ------------------------------ configs/display5_defconfig | 14 +++++++++ include/configs/display5.h | 8 ----- 4 files changed, 16 insertions(+), 56 deletions(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 01f0121beb6..ba2ab51de37 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -197,6 +197,8 @@ config TARGET_DHCOMIMX6 config TARGET_DISPLAY5 bool "LWN DISPLAY5 board" select DM + select DM_I2C + select DM_GPIO select DM_SERIAL select SUPPORT_SPL imply CMD_DM diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index 037c4e69e59..5ebc8529e9c 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -119,49 +118,6 @@ int dram_init(void) return 0; } -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1: TFA9879 */ -struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -/* I2C2: TIVO TM4C123 */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, - .gp = IMX_GPIO_NR(3, 16) - } -}; - -/* I2C3: PMIC PF0100, EEPROM AT24C256C */ -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - iomux_v3_cfg_t const misc_pads[] = { /* Prod ID GPIO pins */ MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -369,10 +325,6 @@ int board_init(void) udelay(25); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - return 0; } diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 6703251e0a2..8de5ec6306e 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -67,6 +67,19 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD_DEVICE=y @@ -85,4 +98,5 @@ CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_I2C_EDID=y CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/display5.h b/include/configs/display5.h index e503e4a0ce4..59f6c649f18 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -57,15 +57,7 @@ #define CONFIG_MXC_UART_BASE UART5_BASE /* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_EDID -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Ethernet */ #ifdef CONFIG_FEC_MXC From 1b20e3a281975ce3aa842c2d62fac1c253bc7f6e Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:40 +0200 Subject: [PATCH 096/190] ARM: imx: defconfig: Enable 'regulator' and 'pmic' commands on display5 Signed-off-by: Lukasz Majewski --- configs/display5_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 8de5ec6306e..b1267b16938 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -54,6 +54,8 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y @@ -95,6 +97,10 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y From 19e874c6d75b58f7707b0b80a7fcbf5dbdf750bc Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:41 +0200 Subject: [PATCH 097/190] DM: mmc: Switch display5 board to use DM_MMC and BLK (USDHC) After this commit the display5 device would use eMMC driver supporting driver model (DM_MMC and BLK). Signed-off-by: Lukasz Majewski --- arch/arm/mach-imx/mx6/Kconfig | 1 + board/liebherr/display5/common.c | 6 ------ board/liebherr/display5/common.h | 1 - board/liebherr/display5/display5.c | 22 ---------------------- 4 files changed, 1 insertion(+), 29 deletions(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index ba2ab51de37..7ccebc37ca6 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -198,6 +198,7 @@ config TARGET_DISPLAY5 bool "LWN DISPLAY5 board" select DM select DM_I2C + select DM_MMC select DM_GPIO select DM_SERIAL select SUPPORT_SPL diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c index 8390d9a0f31..754c442427f 100644 --- a/board/liebherr/display5/common.c +++ b/board/liebherr/display5/common.c @@ -109,12 +109,6 @@ void displ5_set_iomux_usdhc_spl(void) SETUP_IOMUX_PADS(usdhc4_pads); } -void displ5_set_iomux_usdhc(void) -{ - SETUP_IOMUX_PADS(usdhc4_pads); -} - #else void displ5_set_iomux_usdhc_spl(void) {} -void displ5_set_iomux_usdhc(void) {} #endif diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h index 78c64b02e28..231cefc9600 100644 --- a/board/liebherr/display5/common.h +++ b/board/liebherr/display5/common.h @@ -36,7 +36,6 @@ void displ5_set_iomux_uart(void); void displ5_set_iomux_ecspi_spl(void); void displ5_set_iomux_ecspi(void); void displ5_set_iomux_usdhc_spl(void); -void displ5_set_iomux_usdhc(void); void displ5_set_iomux_misc_spl(void); #endif /* __DISPL5_COMMON_H_ */ diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index 5ebc8529e9c..0cc77dac0fa 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -20,8 +20,6 @@ #include #include #include -#include -#include #include #include #include @@ -142,26 +140,6 @@ iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[1] = { - { USDHC4_BASE_ADDR, 0, 8, }, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - displ5_set_iomux_usdhc(); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif /* CONFIG_FSL_ESDHC_IMX */ - static void displ5_setup_ecspi(void) { int ret; From 32e07513833515c6684f8819e176cb62adb55c4d Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:42 +0200 Subject: [PATCH 098/190] DM: eth: Switch display5 board to use DM_ETH After this commit the display5 device would use FEC driver supporting driver model (DM_ETH). Signed-off-by: Lukasz Majewski --- arch/arm/mach-imx/mx6/Kconfig | 1 + board/liebherr/display5/display5.c | 136 +++++++---------------------- include/configs/display5.h | 8 -- 3 files changed, 32 insertions(+), 113 deletions(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7ccebc37ca6..032fd56562b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -197,6 +197,7 @@ config TARGET_DHCOMIMX6 config TARGET_DISPLAY5 bool "LWN DISPLAY5 board" select DM + select DM_ETH select DM_I2C select DM_MMC select DM_GPIO diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index 0cc77dac0fa..e008ea9a3fb 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -155,111 +155,6 @@ static void displ5_setup_ecspi(void) gpio_direction_output(IMX_GPIO_NR(7, 0), 1); } -#ifdef CONFIG_FEC_MXC -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - - /* for old evalboard with R159 present and R160 not populated */ - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), - - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - /*INT#_GBE*/ - MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - SETUP_IOMUX_PADS(enet_pads); - gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ -} - -static int setup_mac_from_fuse(void) -{ - unsigned char enetaddr[6]; - int ret; - - ret = eth_env_get_enetaddr("ethaddr", enetaddr); - if (ret) /* ethaddr is already set */ - return 0; - - imx_get_mac_from_fuse(0, enetaddr); - - if (is_valid_ethaddr(enetaddr)) { - eth_env_set_enetaddr("ethaddr", enetaddr); - return 0; - } - - return 0; -} - -int board_eth_init(bd_t *bd) -{ - struct phy_device *phydev; - struct mii_dev *bus; - int ret; - - setup_iomux_enet(); - - iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); - - ret = enable_fec_anatop_clock(0, ENET_125MHZ); - if (ret) - return ret; - - setup_mac_from_fuse(); - - bus = fec_get_miibus(IMX_FEC_BASE, -1); - if (!bus) - return -ENODEV; - - /* - * We use here the "rgmii-id" mode of operation and allow M88E1512 - * PHY to use its internally callibrated RX/TX delays - */ - phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */, - PHY_INTERFACE_MODE_RGMII_ID); - if (!phydev) { - ret = -ENODEV; - goto err_phy; - } - - /* display5 due to PCB routing can only work with 100 Mbps */ - phydev->advertising &= ~(ADVERTISED_1000baseX_Half | - ADVERTISED_1000baseX_Full | - SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full); - - ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev); - if (ret) - goto err_sw; - - return 0; - -err_sw: - free(phydev); -err_phy: - mdio_unregister(bus); - free(bus); - return ret; -} -#endif /* CONFIG_FEC_MXC */ - /* * Do not overwrite the console * Always use serial for U-Boot console @@ -277,8 +172,25 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif +int board_phy_config(struct phy_device *phydev) +{ + /* display5 due to PCB routing can only work with 100 Mbps */ + phydev->advertising &= ~(ADVERTISED_1000baseX_Half | + ADVERTISED_1000baseX_Full | + SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + int board_init(void) { + struct gpio_desc phy_int_gbe; + int ret; + debug("board init\n"); /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; @@ -288,6 +200,7 @@ int board_init(void) displ5_setup_ecspi(); + /* Setup misc (application specific) stuff */ SETUP_IOMUX_PADS(misc_pads); get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0], @@ -303,6 +216,19 @@ int board_init(void) udelay(25); + /* Setup low level FEC (ETH) */ + ret = dm_gpio_lookup_name("GPIO1_28", &phy_int_gbe); + if (ret) { + printf("Cannot get GPIO1_28\n"); + } else { + ret = dm_gpio_request(&phy_int_gbe, "INT_GBE"); + if (!ret) + dm_gpio_set_dir_flags(&phy_int_gbe, GPIOD_IS_IN); + } + + iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); + enable_fec_anatop_clock(0, ENET_125MHZ); + return 0; } diff --git a/include/configs/display5.h b/include/configs/display5.h index 59f6c649f18..6f19e55c706 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -59,14 +59,6 @@ /* I2C Configs */ #define CONFIG_I2C_MULTI_BUS -/* Ethernet */ -#ifdef CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#endif - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 From e95b4bdd8dcadeecd516406387604aa56b76804c Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:43 +0200 Subject: [PATCH 099/190] DM: SPI: Convert display5 to use SPI with DM/DTS (but no in SPL) The DM/DTS support for SPI is disabled on purpose for SPL, as it is not supported as of time of this conversion. Signed-off-by: Lukasz Majewski --- arch/arm/mach-imx/mx6/Kconfig | 1 + board/liebherr/display5/common.c | 18 --------------- board/liebherr/display5/common.h | 1 - board/liebherr/display5/display5.c | 37 ++++++++++-------------------- configs/display5_defconfig | 3 +++ include/configs/display5.h | 7 ++++-- 6 files changed, 21 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 032fd56562b..7e5a667e81e 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -200,6 +200,7 @@ config TARGET_DISPLAY5 select DM_ETH select DM_I2C select DM_MMC + select DM_SPI select DM_GPIO select DM_SERIAL select SUPPORT_SPL diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c index 754c442427f..d2d174beaa0 100644 --- a/board/liebherr/display5/common.c +++ b/board/liebherr/display5/common.c @@ -45,18 +45,6 @@ void displ5_set_iomux_misc_spl(void) } #ifdef CONFIG_MXC_SPI -iomux_v3_cfg_t const ecspi_pads[] = { - /* SPI3 */ - MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - iomux_v3_cfg_t const ecspi2_pads[] = { /* SPI2, NOR Flash nWP, CS0 */ MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -79,14 +67,8 @@ void displ5_set_iomux_ecspi_spl(void) SETUP_IOMUX_PADS(ecspi2_pads); } -void displ5_set_iomux_ecspi(void) -{ - SETUP_IOMUX_PADS(ecspi_pads); -} - #else void displ5_set_iomux_ecspi_spl(void) {} -void displ5_set_iomux_ecspi(void) {} #endif #ifdef CONFIG_FSL_ESDHC_IMX diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h index 231cefc9600..2bbd934e7a7 100644 --- a/board/liebherr/display5/common.h +++ b/board/liebherr/display5/common.h @@ -34,7 +34,6 @@ void displ5_set_iomux_uart_spl(void); void displ5_set_iomux_uart(void); void displ5_set_iomux_ecspi_spl(void); -void displ5_set_iomux_ecspi(void); void displ5_set_iomux_usdhc_spl(void); void displ5_set_iomux_misc_spl(void); diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index e008ea9a3fb..541e3e94a5e 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -28,11 +27,6 @@ #include #include -#ifndef CONFIG_MXC_SPI -#error "CONFIG_SPI must be set for this board" -#error "Please check your config file" -#endif - #include "common.h" DECLARE_GLOBAL_DATA_PTR; @@ -140,21 +134,6 @@ iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static void displ5_setup_ecspi(void) -{ - int ret; - - displ5_set_iomux_ecspi(); - - ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0"); - if (!ret) - gpio_direction_output(IMX_GPIO_NR(5, 29), 1); - - ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp"); - if (!ret) - gpio_direction_output(IMX_GPIO_NR(7, 0), 1); -} - /* * Do not overwrite the console * Always use serial for U-Boot console @@ -188,7 +167,7 @@ int board_phy_config(struct phy_device *phydev) int board_init(void) { - struct gpio_desc phy_int_gbe; + struct gpio_desc phy_int_gbe, spi2_wp; int ret; debug("board init\n"); @@ -197,9 +176,6 @@ int board_init(void) /* Setup iomux for non console UARTS */ displ5_set_iomux_uart(); - - displ5_setup_ecspi(); - /* Setup misc (application specific) stuff */ SETUP_IOMUX_PADS(misc_pads); @@ -229,6 +205,17 @@ int board_init(void) iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); enable_fec_anatop_clock(0, ENET_125MHZ); + /* Setup #WP for SPI-NOR memory */ + ret = dm_gpio_lookup_name("GPIO7_0", &spi2_wp); + if (ret) { + printf("Cannot get GPIO7_0\n"); + } else { + ret = dm_gpio_request(&spi2_wp, "spi2_#wp"); + if (!ret) + dm_gpio_set_dir_flags(&spi2_wp, GPIOD_IS_OUT | + GPIOD_IS_OUT_ACTIVE); + } + return 0; } diff --git a/configs/display5_defconfig b/configs/display5_defconfig index b1267b16938..875ccce1c8c 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -85,12 +85,15 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_FEC_MXC=y diff --git a/include/configs/display5.h b/include/configs/display5.h index 6f19e55c706..bbcb5da7bbd 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -35,8 +35,11 @@ * 0x1540000 - 0x1640000 : SPI.factory (1MiB) */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_MTD +/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD #endif /* Below values are "dummy" - only to avoid build break */ From 1743d6676d2cc50948f7227916d559677e31b546 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:44 +0200 Subject: [PATCH 100/190] ARM: display5: Remove UART initialization code after DM/DTS conversion (non-console) This UART is not used in U-Boot, so there is no need to initialize it. Signed-off-by: Lukasz Majewski --- board/liebherr/display5/common.c | 13 ------------- board/liebherr/display5/common.h | 1 - board/liebherr/display5/display5.c | 2 -- 3 files changed, 16 deletions(-) diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c index d2d174beaa0..5e714076a49 100644 --- a/board/liebherr/display5/common.c +++ b/board/liebherr/display5/common.c @@ -8,14 +8,6 @@ #include #include "common.h" -iomux_v3_cfg_t const uart_pads[] = { - /* UART4 */ - MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - iomux_v3_cfg_t const uart_console_pads[] = { /* UART5 */ MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -29,11 +21,6 @@ void displ5_set_iomux_uart_spl(void) SETUP_IOMUX_PADS(uart_console_pads); } -void displ5_set_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart_pads); -} - iomux_v3_cfg_t const misc_pads_spl[] = { /* Emergency recovery pin */ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h index 2bbd934e7a7..4eb70dc42fb 100644 --- a/board/liebherr/display5/common.h +++ b/board/liebherr/display5/common.h @@ -32,7 +32,6 @@ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) void displ5_set_iomux_uart_spl(void); -void displ5_set_iomux_uart(void); void displ5_set_iomux_ecspi_spl(void); void displ5_set_iomux_usdhc_spl(void); void displ5_set_iomux_misc_spl(void); diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index 541e3e94a5e..5713401ed95 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -174,8 +174,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - /* Setup iomux for non console UARTS */ - displ5_set_iomux_uart(); /* Setup misc (application specific) stuff */ SETUP_IOMUX_PADS(misc_pads); From d5354f59d072210b469f099c8ee313e0f17c28e6 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:45 +0200 Subject: [PATCH 101/190] DM: WDT: Convert WDT driver to use DM/DTS (including SYSRESET) This commit enables support for CONFIG_WDT in the U-Boot proper. Moreover, the SYSRESET_WATCHDOG driver is used to support 'reset' command. As SPL is not yet ready for DM conversion, the CONFIG_HW_WATCHDOG is enabled for it. This allows the legacy SPL code to work properly. Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx6q-display5-u-boot.dtsi | 5 +++++ configs/display5_defconfig | 3 +++ include/configs/display5.h | 6 +++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi b/arch/arm/dts/imx6q-display5-u-boot.dtsi index b942218b7ab..aa660b5aeb6 100644 --- a/arch/arm/dts/imx6q-display5-u-boot.dtsi +++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi @@ -31,6 +31,11 @@ chosen { stdout-path = &uart5; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; }; &i2c3 { diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 875ccce1c8c..46bcdaffc83 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_PART=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -107,5 +108,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_I2C_EDID=y CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/display5.h b/include/configs/display5.h index bbcb5da7bbd..de11ff61c66 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -342,7 +342,11 @@ /* Watchdog */ #define CONFIG_WATCHDOG_TIMEOUT_MSECS 15000 - +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_WDT +#undef CONFIG_WATCHDOG +#define CONFIG_HW_WATCHDOG +#endif /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE (SZ_64K) From 21c7d34279a4f4247e1f20492b87828187a090df Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:46 +0200 Subject: [PATCH 102/190] ARM: display5: Remove common.c file (after DM/DTS U-Boot proper conversion) The common.c file content can be safely moved to spl.c file after performing the DM/DTS conversion for the U-Boot proper. It contains the non DM/DTS setup code, which now is only used by SPL. Signed-off-by: Lukasz Majewski --- board/liebherr/display5/Makefile | 4 +- board/liebherr/display5/common.c | 83 -------------------------------- board/liebherr/display5/common.h | 5 -- board/liebherr/display5/spl.c | 74 ++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 90 deletions(-) delete mode 100644 board/liebherr/display5/common.c diff --git a/board/liebherr/display5/Makefile b/board/liebherr/display5/Makefile index f934672428a..ee503add75d 100644 --- a/board/liebherr/display5/Makefile +++ b/board/liebherr/display5/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # ifdef CONFIG_SPL_BUILD -obj-y = common.o spl.o +obj-y = spl.o else -obj-y := common.o display5.o +obj-y := display5.o endif diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c deleted file mode 100644 index 5e714076a49..00000000000 --- a/board/liebherr/display5/common.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 DENX Software Engineering - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -#include -#include -#include "common.h" - -iomux_v3_cfg_t const uart_console_pads[] = { - /* UART5 */ - MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -void displ5_set_iomux_uart_spl(void) -{ - SETUP_IOMUX_PADS(uart_console_pads); -} - -iomux_v3_cfg_t const misc_pads_spl[] = { - /* Emergency recovery pin */ - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -void displ5_set_iomux_misc_spl(void) -{ - SETUP_IOMUX_PADS(misc_pads_spl); -} - -#ifdef CONFIG_MXC_SPI -iomux_v3_cfg_t const ecspi2_pads[] = { - /* SPI2, NOR Flash nWP, CS0 */ - MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_spi_cs_gpio(unsigned int bus, unsigned int cs) -{ - if (bus != 1 || cs != 0) - return -EINVAL; - - return IMX_GPIO_NR(5, 29); -} - -void displ5_set_iomux_ecspi_spl(void) -{ - SETUP_IOMUX_PADS(ecspi2_pads); -} - -#else -void displ5_set_iomux_ecspi_spl(void) {} -#endif - -#ifdef CONFIG_FSL_ESDHC_IMX -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -void displ5_set_iomux_usdhc_spl(void) -{ - SETUP_IOMUX_PADS(usdhc4_pads); -} - -#else -void displ5_set_iomux_usdhc_spl(void) {} -#endif diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h index 4eb70dc42fb..44c7470074c 100644 --- a/board/liebherr/display5/common.h +++ b/board/liebherr/display5/common.h @@ -31,9 +31,4 @@ #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -void displ5_set_iomux_uart_spl(void); -void displ5_set_iomux_ecspi_spl(void); -void displ5_set_iomux_usdhc_spl(void); -void displ5_set_iomux_misc_spl(void); - #endif /* __DISPL5_COMMON_H_ */ diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c index 354b63e431f..311edaf939c 100644 --- a/board/liebherr/display5/spl.c +++ b/board/liebherr/display5/spl.c @@ -104,6 +104,80 @@ static const struct mx6_ddr3_cfg mt41k128m16jt_125 = { .trasmin = 3500, }; +iomux_v3_cfg_t const uart_console_pads[] = { + /* UART5 */ + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void displ5_set_iomux_uart_spl(void) +{ + SETUP_IOMUX_PADS(uart_console_pads); +} + +iomux_v3_cfg_t const misc_pads_spl[] = { + /* Emergency recovery pin */ + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void displ5_set_iomux_misc_spl(void) +{ + SETUP_IOMUX_PADS(misc_pads_spl); +} + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi2_pads[] = { + /* SPI2, NOR Flash nWP, CS0 */ + MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + if (bus != 1 || cs != 0) + return -EINVAL; + + return IMX_GPIO_NR(5, 29); +} + +void displ5_set_iomux_ecspi_spl(void) +{ + SETUP_IOMUX_PADS(ecspi2_pads); +} + +#else +void displ5_set_iomux_ecspi_spl(void) {} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +void displ5_set_iomux_usdhc_spl(void) +{ + SETUP_IOMUX_PADS(usdhc4_pads); +} + +#else +void displ5_set_iomux_usdhc_spl(void) {} +#endif + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; From 5ec7d1b49566a686aa7c40280a526ab0401c1092 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:47 +0200 Subject: [PATCH 103/190] ARM: Update display5_factory_defconfig after switch to DM/DTS and uuu utility This commit updates the display5_factory_defconfig file after the switch to DM/DTS for this board. Moreover, the VID and PID for SPL running SDP gadget have been updated to allow seamless work with 'uuu' utility from NXP (the imx_usb doesn't work properly after embedding the u-boot proper into fitImage - problem with IVT embedding in FIT). Example to use 'uuu' session: cat << EOF > display5_recovery.lst uuu_version 1.2.135 SDP: boot -f /srv/tftp/SPL SDPU: write -f /srv/tftp/u-boot-dtb.img -addr 0x10000000 SDPU: jump -addr 0x10000000 SDPU: done EOF sudo ./uuu/uuu display5_recovery.lst Signed-off-by: Lukasz Majewski --- configs/display5_factory_defconfig | 38 ++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 070de97e5b5..c515d14a80e 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -4,14 +4,19 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_DISPLAY5=y +CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" CONFIG_BOOTDELAY=3 @@ -47,11 +52,14 @@ CONFIG_CMD_PART=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB_SDP=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -67,26 +75,52 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y +CONFIG_PHY_MARVELL=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Liebherr" -CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 -CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_I2C_EDID=y CONFIG_IMX_WATCHDOG=y +CONFIG_PANIC_HANG=y From feeff1567f1e98775b1b0070b106ecc09059ecc1 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:49 +0200 Subject: [PATCH 104/190] imx: Convert emergency pad of display5 to use dm_gpio* functions After this change the display5's emergency gpio use dm_gpio* functions instead of legacy ones (gpio*) to read its state. Signed-off-by: Lukasz Majewski --- board/liebherr/display5/display5.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index 5713401ed95..b8dcd03fd9b 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -36,7 +36,6 @@ static bool sw_ids_valid; static u32 cpu_id; static u32 unit_id; -#define EM_PAD IMX_GPIO_NR(3, 29) #define SW0 IMX_GPIO_NR(2, 4) #define SW1 IMX_GPIO_NR(2, 5) #define SW2 IMX_GPIO_NR(2, 6) @@ -236,21 +235,24 @@ static inline void setup_boot_modes(void) {} int misc_init_r(void) { + struct gpio_desc em_pad; int ret; setup_boot_modes(); - ret = gpio_request(EM_PAD, "Emergency_PAD"); + ret = dm_gpio_lookup_name("GPIO3_29", &em_pad); + if (ret) { + printf("Can't find emergency PAD gpio\n"); + return ret; + } + + ret = dm_gpio_request(&em_pad, "Emergency_PAD"); if (ret) { printf("Can't request emergency PAD gpio\n"); return ret; } - ret = gpio_direction_input(EM_PAD); - if (ret) { - printf("Can't set emergency PAD direction\n"); - return ret; - } + dm_gpio_set_dir_flags(&em_pad, GPIOD_IS_IN); return 0; } From 45aac6dd7afe73be69ab432c06eb97f9920c491f Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 3 Sep 2019 16:38:50 +0200 Subject: [PATCH 105/190] imx: Rewrite display5 get_board_id() function to use dm_gpio_* API The get_board_id() function was using the old gpio_* compatibility layer to read HW and SW ID numbers encoded on the PCB board. After this change the new dm_gpio* API is used for this purpose. Signed-off-by: Lukasz Majewski --- board/liebherr/display5/display5.c | 53 ++++++++++++------------------ 1 file changed, 21 insertions(+), 32 deletions(-) diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index b8dcd03fd9b..85ca777c1d2 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -36,60 +36,49 @@ static bool sw_ids_valid; static u32 cpu_id; static u32 unit_id; -#define SW0 IMX_GPIO_NR(2, 4) -#define SW1 IMX_GPIO_NR(2, 5) -#define SW2 IMX_GPIO_NR(2, 6) -#define SW3 IMX_GPIO_NR(2, 7) -#define HW0 IMX_GPIO_NR(6, 7) -#define HW1 IMX_GPIO_NR(6, 9) -#define HW2 IMX_GPIO_NR(6, 10) -#define HW3 IMX_GPIO_NR(6, 11) -#define HW4 IMX_GPIO_NR(4, 7) -#define HW5 IMX_GPIO_NR(4, 11) -#define HW6 IMX_GPIO_NR(4, 13) -#define HW7 IMX_GPIO_NR(4, 15) - -int gpio_table_sw_ids[] = { - SW0, SW1, SW2, SW3 +const char *gpio_table_sw_names[] = { + "GPIO2_4", "GPIO2_5", "GPIO2_6", "GPIO2_7" }; const char *gpio_table_sw_ids_names[] = { "sw0", "sw1", "sw2", "sw3" }; -int gpio_table_hw_ids[] = { - HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7 +const char *gpio_table_hw_names[] = { + "GPIO6_7", "GPIO6_9", "GPIO6_10", "GPIO6_11", + "GPIO4_7", "GPIO4_11", "GPIO4_13", "GPIO4_15" }; const char *gpio_table_hw_ids_names[] = { "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7" }; -static int get_board_id(int *ids, const char **c, int size, - bool *valid, u32 *id) +static int get_board_id(const char **pin_names, const char **ids_names, + int size, bool *valid, u32 *id) { + struct gpio_desc desc; int i, ret, val; *valid = false; for (i = 0; i < size; i++) { - ret = gpio_request(ids[i], c[i]); + memset(&desc, 0, sizeof(desc)); + + ret = dm_gpio_lookup_name(pin_names[i], &desc); if (ret) { - printf("Can't request SWx gpios\n"); + printf("Can't lookup request SWx gpios\n"); return ret; } - } - for (i = 0; i < size; i++) { - ret = gpio_direction_input(ids[i]); + ret = dm_gpio_request(&desc, ids_names[i]); if (ret) { - printf("Can't set SWx gpios direction\n"); + printf("Can't lookup request SWx gpios\n"); return ret; } - } - for (i = 0; i < size; i++) { - val = gpio_get_value(ids[i]); + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + val = dm_gpio_get_value(&desc); if (val < 0) { printf("Can't get SW%d ID\n", i); *id = 0; @@ -176,12 +165,12 @@ int board_init(void) /* Setup misc (application specific) stuff */ SETUP_IOMUX_PADS(misc_pads); - get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0], - ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id); + get_board_id(gpio_table_sw_names, &gpio_table_sw_ids_names[0], + ARRAY_SIZE(gpio_table_sw_names), &sw_ids_valid, &unit_id); debug("SWx unit_id 0x%x\n", unit_id); - get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0], - ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id); + get_board_id(gpio_table_hw_names, &gpio_table_hw_ids_names[0], + ARRAY_SIZE(gpio_table_hw_names), &hw_ids_valid, &cpu_id); debug("HWx cpu_id 0x%x\n", cpu_id); if (hw_ids_valid && sw_ids_valid) From 772b55723bcbe8ebe84f579d9cdc831d8e18579d Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Mon, 9 Sep 2019 15:32:13 +0200 Subject: [PATCH 106/190] imx: Introduce CONFIG_SPL_FORCE_MMC_BOOT to force MMC boot on falcon mode This change tries to fix the following problem: - The board boots (to be more precise - ROM loads SPL) from a slow SPI-NOR memory. As a result the spl_boot_device() will return SPI-NOR as a boot device (which is correct). - The problem is that in 'falcon boot' the eMMC is used as a boot medium to load kernel from its partition. Calling spl_boot_device() will break things as it returns SPI-NOR device. To fix this issue the new CONFIG_SPL_FORCE_MMC_BOOT Kconfig flag is introduced to handle this special use case. By default it is not defined, so there is no change in the legacy code flow. Signed-off-by: Lukasz Majewski --- arch/arm/mach-imx/spl.c | 11 +++++++++++ common/spl/Kconfig | 9 +++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index a98fab8f1ce..cda719226aa 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -178,7 +178,18 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ u32 spl_boot_mode(const u32 boot_device) { +/* + * When CONFIG_SPL_FORCE_MMC_BOOT is defined the 'boot_device' is used + * unconditionally to decide about device to use for booting. + * This is crucial for falcon boot mode, when board boots up (i.e. ROM + * loads SPL) from slow SPI-NOR memory and afterwards the SPL's 'falcon' boot + * mode is used to load Linux OS from eMMC partition. + */ +#ifdef CONFIG_SPL_FORCE_MMC_BOOT + switch (boot_device) { +#else switch (spl_boot_device()) { +#endif /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2ca219995dd..f59b6f5b51f 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -608,6 +608,15 @@ config SPL_MMC_SUPPORT this option to build the drivers in drivers/mmc as part of an SPL build. +config SPL_FORCE_MMC_BOOT + bool "Force SPL booting from MMC" + depends on SPL_MMC_SUPPORT + default n + help + Force SPL to use MMC device for Linux kernel booting even when the + SoC ROM recognized boot medium is not eMMC/SD. This is crucial for + factory or 'falcon mode' booting. + config SPL_MMC_TINY bool "Tiny MMC framework in SPL" depends on SPL_MMC_SUPPORT From f1e323a0a58e6d6b60456bf8e8565f628f33b88c Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Sep 2019 09:54:55 +0200 Subject: [PATCH 107/190] dts: imx28: Remove #include "imx28.dtsi" from imx28-u-boot.dtsi file After this change it is possible to use imx28--u-boot.dtsi with the imx28-u-boot.dtsi explicitly included without breaking setup from imx28-.dts file. The problem is that the imx28.dtsi included in a wrong place overrides the changes made in imx28-.dts. As a result some devices are "disabled" in the final DTB. Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-u-boot.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/imx28-u-boot.dtsi b/arch/arm/dts/imx28-u-boot.dtsi index d545b402a78..9db72a6be3c 100644 --- a/arch/arm/dts/imx28-u-boot.dtsi +++ b/arch/arm/dts/imx28-u-boot.dtsi @@ -5,7 +5,6 @@ * * SPDX-License-Identifier: GPL-2.0+ or X11 */ -#include "imx28.dtsi" &gpio0 { gpio-ranges = <&pinctrl 0 0 29>; From 3c50e0156644bf3223db11a57e23cc38de88af3b Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Sep 2019 09:54:56 +0200 Subject: [PATCH 108/190] spl: Init proper struct driver member (platdata_auto_alloc_size) for mxs_spi This change initializes proper member of struct driver - platdata_auto_alloc_size instead of priv_auto_alloc_size, which is setup twice. Signed-off-by: Lukasz Majewski --- drivers/spi/mxs_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 3a9756fbf1b..b1cc83aab10 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -584,7 +584,7 @@ U_BOOT_DRIVER(mxs_spi) = { .of_match = mxs_spi_ids, .ofdata_to_platdata = mxs_ofdata_to_platdata, #endif - .priv_auto_alloc_size = sizeof(struct mxs_spi_platdata), + .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata), .ops = &mxs_spi_ops, .priv_auto_alloc_size = sizeof(struct mxs_spi_priv), .probe = mxs_spi_probe, From c2050e10e11b7226f01aa18d49b9d4a2322723ca Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Sep 2019 09:54:57 +0200 Subject: [PATCH 109/190] spi: fix: Call mxs_reset_block() during DM/DTS probe Without this change the DM/DTS version of mxs_spi driver doesn't reset the SPI IP block in probe. As a result this driver (when used solely on U-Boot proper) relies on reset performed by mxs spi driver in SPL. In the use case where eMMC is used in SPL as a boot primary device, the mxs_reset_block() is not called at all and DM/DTS aware SPI driver in U-Boot proper is malfunctioning. Signed-off-by: Lukasz Majewski --- drivers/spi/mxs_spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index b1cc83aab10..d475830f178 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -436,6 +436,8 @@ static int mxs_spi_probe(struct udevice *bus) priv->dma_channel = plat->dma_id; priv->clk_id = plat->clk_id; + mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg); + ret = mxs_dma_init_channel(priv->dma_channel); if (ret) { printf("%s: DMA init channel error %d\n", __func__, ret); From ec0c81f8edb81de9ab7ad50150ee634d36cbcf9c Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Sep 2019 09:54:58 +0200 Subject: [PATCH 110/190] spi: Add support for SPL_OF_PLATDATA to mxs_spi.c driver After this patch the mxs_spi.c DM/DTS driver can be used at early SPL to read payload from SPI-NOR memories. It was necessary to adjust its name to 'fsl_imx_2{38}_spi' to match requirements for SPL_OF_PLATDATA usage. Signed-off-by: Lukasz Majewski --- drivers/spi/mxs_spi.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index d475830f178..58b1c67a191 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -57,7 +57,18 @@ static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) #else #include #include +#include + +#ifdef CONFIG_MX28 +#define dtd_fsl_imx_spi dtd_fsl_imx28_spi +#else /* CONFIG_MX23 */ +#define dtd_fsl_imx_spi dtd_fsl_imx23_spi +#endif + struct mxs_spi_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_fsl_imx_spi dtplat; +#endif s32 frequency; /* Default clock frequency, -1 for none */ fdt_addr_t base; /* SPI IP block base address */ int num_cs; /* Number of CSes supported */ @@ -430,11 +441,26 @@ static int mxs_spi_probe(struct udevice *bus) int ret; debug("%s: probe\n", __func__); + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_fsl_imx_spi *dtplat = &plat->dtplat; + struct phandle_1_arg *p1a = &dtplat->clocks[0]; + + priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0]; + priv->dma_channel = dtplat->dmas[1]; + priv->clk_id = p1a->arg[0]; + priv->max_freq = dtplat->spi_max_frequency; + plat->num_cs = dtplat->num_cs; + + debug("OF_PLATDATA: regs: 0x%x max freq: %d clkid: %d\n", + (unsigned int)priv->regs, priv->max_freq, priv->clk_id); +#else priv->regs = (struct mxs_ssp_regs *)plat->base; priv->max_freq = plat->frequency; priv->dma_channel = plat->dma_id; priv->clk_id = plat->clk_id; +#endif mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg); @@ -571,16 +597,20 @@ static int mxs_ofdata_to_platdata(struct udevice *bus) return 0; } -#endif static const struct udevice_id mxs_spi_ids[] = { { .compatible = "fsl,imx23-spi" }, { .compatible = "fsl,imx28-spi" }, { } }; +#endif U_BOOT_DRIVER(mxs_spi) = { - .name = "mxs_spi", +#ifdef CONFIG_MX28 + .name = "fsl_imx28_spi", +#else /* CONFIG_MX23 */ + .name = "fsl_imx23_spi", +#endif .id = UCLASS_SPI, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = mxs_spi_ids, From 6116f4c56fe786893d33a4ee2786a4eb59ec0a94 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Sep 2019 09:54:59 +0200 Subject: [PATCH 111/190] mmc: Convert mxsmmc eMMC driver for i.MX2{38} to DM/DTS This patch converts the mxsmmc driver to support DM/DTS. Moreover, it is also possible to use it in early SPL with SPL_OF_PLATDATA enabled. Signed-off-by: Lukasz Majewski --- drivers/mmc/mxsmmc.c | 835 +++++++++++++++++++++++++++++-------------- 1 file changed, 569 insertions(+), 266 deletions(-) diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 92db4ae5a66..7ea47f98017 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -2,6 +2,9 @@ /* * Freescale i.MX28 SSP MMC driver * + * Copyright (C) 2019 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * * Copyright (C) 2011 Marek Vasut * on behalf of DENX Software Engineering GmbH * @@ -16,6 +19,7 @@ * (C) Copyright 2003 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net */ + #include #include #include @@ -27,19 +31,56 @@ #include #include -struct mxsmmc_priv { - int id; - struct mxs_ssp_regs *regs; - uint32_t buswidth; - int (*mmc_is_wp)(int); - int (*mmc_cd)(int); - struct mxs_dma_desc *desc; - struct mmc_config cfg; /* mmc configuration */ -}; - #define MXSMMC_MAX_TIMEOUT 10000 #define MXSMMC_SMALL_TRANSFER 512 +#if !CONFIG_IS_ENABLED(DM_MMC) +struct mxsmmc_priv { + int id; + int (*mmc_is_wp)(int); + int (*mmc_cd)(int); + struct mmc_config cfg; /* mmc configuration */ + struct mxs_dma_desc *desc; + uint32_t buswidth; + struct mxs_ssp_regs *regs; +}; +#else /* CONFIG_IS_ENABLED(DM_MMC) */ +#include +#include +#include + +#ifdef CONFIG_MX28 +#define dtd_fsl_imx_mmc dtd_fsl_imx28_mmc +#else /* CONFIG_MX23 */ +#define dtd_fsl_imx_mmc dtd_fsl_imx23_mmc +#endif + +struct mxsmmc_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_fsl_imx_mmc dtplat; +#endif + struct mmc_config cfg; + struct mmc mmc; + fdt_addr_t base; + int non_removable; + int buswidth; + int dma_id; + int clk_id; +}; + +struct mxsmmc_priv { + int clkid; + struct mxs_dma_desc *desc; + u32 buswidth; + struct mxs_ssp_regs *regs; + unsigned int dma_channel; +}; +#endif + +#if !CONFIG_IS_ENABLED(DM_MMC) +static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data); + static int mxsmmc_cd(struct mxsmmc_priv *priv) { struct mxs_ssp_regs *ssp_regs = priv->regs; @@ -50,259 +91,6 @@ static int mxsmmc_cd(struct mxsmmc_priv *priv) return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT); } -static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) -{ - struct mxs_ssp_regs *ssp_regs = priv->regs; - uint32_t *data_ptr; - int timeout = MXSMMC_MAX_TIMEOUT; - uint32_t reg; - uint32_t data_count = data->blocksize * data->blocks; - - if (data->flags & MMC_DATA_READ) { - data_ptr = (uint32_t *)data->dest; - while (data_count && --timeout) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_EMPTY)) { - *data_ptr++ = readl(&ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = MXSMMC_MAX_TIMEOUT; - } else - udelay(1000); - } - } else { - data_ptr = (uint32_t *)data->src; - timeout *= 100; - while (data_count && --timeout) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_FULL)) { - writel(*data_ptr++, &ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = MXSMMC_MAX_TIMEOUT; - } else - udelay(1000); - } - } - - return timeout ? 0 : -ECOMM; -} - -static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) -{ - uint32_t data_count = data->blocksize * data->blocks; - int dmach; - struct mxs_dma_desc *desc = priv->desc; - void *addr; - unsigned int flags; - struct bounce_buffer bbstate; - - memset(desc, 0, sizeof(struct mxs_dma_desc)); - desc->address = (dma_addr_t)desc; - - if (data->flags & MMC_DATA_READ) { - priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; - addr = data->dest; - flags = GEN_BB_WRITE; - } else { - priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; - addr = (void *)data->src; - flags = GEN_BB_READ; - } - - bounce_buffer_start(&bbstate, addr, data_count, flags); - - priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer; - - priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | - (data_count << MXS_DMA_DESC_BYTES_OFFSET); - - dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; - mxs_dma_desc_append(dmach, priv->desc); - if (mxs_dma_go(dmach)) { - bounce_buffer_stop(&bbstate); - return -ECOMM; - } - - bounce_buffer_stop(&bbstate); - - return 0; -} - -/* - * Sends a command out on the bus. Takes the mmc pointer, - * a command pointer, and an optional data pointer. - */ -static int -mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) -{ - struct mxsmmc_priv *priv = mmc->priv; - struct mxs_ssp_regs *ssp_regs = priv->regs; - uint32_t reg; - int timeout; - uint32_t ctrl0; - int ret; - - debug("MMC%d: CMD%d\n", mmc->block_dev.devnum, cmd->cmdidx); - - /* Check bus busy */ - timeout = MXSMMC_MAX_TIMEOUT; - while (--timeout) { - udelay(1000); - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & - (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | - SSP_STATUS_CMD_BUSY))) { - break; - } - } - - if (!timeout) { - printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.devnum); - return -ETIMEDOUT; - } - - /* See if card is present */ - if (!mxsmmc_cd(priv)) { - printf("MMC%d: No card detected!\n", mmc->block_dev.devnum); - return -ENOMEDIUM; - } - - /* Start building CTRL0 contents */ - ctrl0 = priv->buswidth; - - /* Set up command */ - if (!(cmd->resp_type & MMC_RSP_CRC)) - ctrl0 |= SSP_CTRL0_IGNORE_CRC; - if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ - ctrl0 |= SSP_CTRL0_GET_RESP; - if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ - ctrl0 |= SSP_CTRL0_LONG_RESP; - - if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) - writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); - else - writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); - - /* Command index */ - reg = readl(&ssp_regs->hw_ssp_cmd0); - reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); - reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; - if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) - reg |= SSP_CMD0_APPEND_8CYC; - writel(reg, &ssp_regs->hw_ssp_cmd0); - - /* Command argument */ - writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); - - /* Set up data */ - if (data) { - /* READ or WRITE */ - if (data->flags & MMC_DATA_READ) { - ctrl0 |= SSP_CTRL0_READ; - } else if (priv->mmc_is_wp && - priv->mmc_is_wp(mmc->block_dev.devnum)) { - printf("MMC%d: Can not write a locked card!\n", - mmc->block_dev.devnum); - return -EOPNOTSUPP; - } - - ctrl0 |= SSP_CTRL0_DATA_XFER; - - reg = data->blocksize * data->blocks; -#if defined(CONFIG_MX23) - ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK; - - clrsetbits_le32(&ssp_regs->hw_ssp_cmd0, - SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK, - ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) | - ((ffs(data->blocksize) - 1) << - SSP_CMD0_BLOCK_SIZE_OFFSET)); -#elif defined(CONFIG_MX28) - writel(reg, &ssp_regs->hw_ssp_xfer_size); - - reg = ((data->blocks - 1) << - SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | - ((ffs(data->blocksize) - 1) << - SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); - writel(reg, &ssp_regs->hw_ssp_block_size); -#endif - } - - /* Kick off the command */ - ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; - writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); - - /* Wait for the command to complete */ - timeout = MXSMMC_MAX_TIMEOUT; - while (--timeout) { - udelay(1000); - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_CMD_BUSY)) - break; - } - - if (!timeout) { - printf("MMC%d: Command %d busy\n", - mmc->block_dev.devnum, cmd->cmdidx); - return -ETIMEDOUT; - } - - /* Check command timeout */ - if (reg & SSP_STATUS_RESP_TIMEOUT) { - printf("MMC%d: Command %d timeout (status 0x%08x)\n", - mmc->block_dev.devnum, cmd->cmdidx, reg); - return -ETIMEDOUT; - } - - /* Check command errors */ - if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { - printf("MMC%d: Command %d error (status 0x%08x)!\n", - mmc->block_dev.devnum, cmd->cmdidx, reg); - return -ECOMM; - } - - /* Copy response to response buffer */ - if (cmd->resp_type & MMC_RSP_136) { - cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); - cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); - cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); - cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); - } else - cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); - - /* Return if no data to process */ - if (!data) - return 0; - - if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { - ret = mxsmmc_send_cmd_pio(priv, data); - if (ret) { - printf("MMC%d: Data timeout with command %d " - "(status 0x%08x)!\n", - mmc->block_dev.devnum, cmd->cmdidx, reg); - return ret; - } - } else { - ret = mxsmmc_send_cmd_dma(priv, data); - if (ret) { - printf("MMC%d: DMA transfer failed\n", - mmc->block_dev.devnum); - return ret; - } - } - - /* Check data errors */ - reg = readl(&ssp_regs->hw_ssp_status); - if (reg & - (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | - SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { - printf("MMC%d: Data error with command %d (status 0x%08x)!\n", - mmc->block_dev.devnum, cmd->cmdidx, reg); - return -ECOMM; - } - - return 0; -} - static int mxsmmc_set_ios(struct mmc *mmc) { struct mxsmmc_priv *priv = mmc->priv; @@ -329,7 +117,7 @@ static int mxsmmc_set_ios(struct mmc *mmc) SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); debug("MMC%d: Set %d bits bus width\n", - mmc->block_dev.devnum, mmc->bus_width); + mmc->block_dev.devnum, mmc->bus_width); return 0; } @@ -415,14 +203,529 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) * CLOCK_RATE could be any integer from 0 to 255. */ priv->cfg.f_min = 400000; - priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; + priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) + * 1000 / 2; priv->cfg.b_max = 0x20; mmc = mmc_create(&priv->cfg, priv); - if (mmc == NULL) { + if (!mmc) { mxs_dma_desc_free(priv->desc); free(priv); return -ENOMEM; } return 0; } +#endif /* CONFIG_IS_ENABLED(DM_MMC) */ + +static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) +{ + struct mxs_ssp_regs *ssp_regs = priv->regs; + uint32_t *data_ptr; + int timeout = MXSMMC_MAX_TIMEOUT; + uint32_t reg; + uint32_t data_count = data->blocksize * data->blocks; + + if (data->flags & MMC_DATA_READ) { + data_ptr = (uint32_t *)data->dest; + while (data_count && --timeout) { + reg = readl(&ssp_regs->hw_ssp_status); + if (!(reg & SSP_STATUS_FIFO_EMPTY)) { + *data_ptr++ = readl(&ssp_regs->hw_ssp_data); + data_count -= 4; + timeout = MXSMMC_MAX_TIMEOUT; + } else + udelay(1000); + } + } else { + data_ptr = (uint32_t *)data->src; + timeout *= 100; + while (data_count && --timeout) { + reg = readl(&ssp_regs->hw_ssp_status); + if (!(reg & SSP_STATUS_FIFO_FULL)) { + writel(*data_ptr++, &ssp_regs->hw_ssp_data); + data_count -= 4; + timeout = MXSMMC_MAX_TIMEOUT; + } else + udelay(1000); + } + } + + return timeout ? 0 : -ECOMM; +} + +static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) +{ + uint32_t data_count = data->blocksize * data->blocks; + int dmach; + struct mxs_dma_desc *desc = priv->desc; + void *addr; + unsigned int flags; + struct bounce_buffer bbstate; + + memset(desc, 0, sizeof(struct mxs_dma_desc)); + desc->address = (dma_addr_t)desc; + + if (data->flags & MMC_DATA_READ) { + priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; + addr = data->dest; + flags = GEN_BB_WRITE; + } else { + priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; + addr = (void *)data->src; + flags = GEN_BB_READ; + } + + bounce_buffer_start(&bbstate, addr, data_count, flags); + + priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer; + + priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | + (data_count << MXS_DMA_DESC_BYTES_OFFSET); + +#if !CONFIG_IS_ENABLED(DM_MMC) + dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; +#else + dmach = priv->dma_channel; +#endif + mxs_dma_desc_append(dmach, priv->desc); + if (mxs_dma_go(dmach)) { + bounce_buffer_stop(&bbstate); + return -ECOMM; + } + + bounce_buffer_stop(&bbstate); + + return 0; +} + +#if !CONFIG_IS_ENABLED(DM_MMC) +/* + * Sends a command out on the bus. Takes the mmc pointer, + * a command pointer, and an optional data pointer. + */ +static int +mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + struct mxsmmc_priv *priv = mmc->priv; + struct mxs_ssp_regs *ssp_regs = priv->regs; +#else +static int +mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) +{ + struct mxsmmc_platdata *plat = dev_get_platdata(dev); + struct mxsmmc_priv *priv = dev_get_priv(dev); + struct mxs_ssp_regs *ssp_regs = priv->regs; + struct mmc *mmc = &plat->mmc; +#endif + uint32_t reg; + int timeout; + uint32_t ctrl0; + int ret; +#if !CONFIG_IS_ENABLED(DM_MMC) + int devnum = mmc->block_dev.devnum; +#else + int devnum = mmc_get_blk_desc(mmc)->devnum; +#endif + debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx); + + /* Check bus busy */ + timeout = MXSMMC_MAX_TIMEOUT; + while (--timeout) { + udelay(1000); + reg = readl(&ssp_regs->hw_ssp_status); + if (!(reg & + (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | + SSP_STATUS_CMD_BUSY))) { + break; + } + } + + if (!timeout) { + printf("MMC%d: Bus busy timeout!\n", devnum); + return -ETIMEDOUT; + } +#if !CONFIG_IS_ENABLED(DM_MMC) + /* See if card is present */ + if (!mxsmmc_cd(priv)) { + printf("MMC%d: No card detected!\n", devnum); + return -ENOMEDIUM; + } +#endif + /* Start building CTRL0 contents */ + ctrl0 = priv->buswidth; + + /* Set up command */ + if (!(cmd->resp_type & MMC_RSP_CRC)) + ctrl0 |= SSP_CTRL0_IGNORE_CRC; + if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ + ctrl0 |= SSP_CTRL0_GET_RESP; + if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ + ctrl0 |= SSP_CTRL0_LONG_RESP; + + if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) + writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); + else + writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); + + /* Command index */ + reg = readl(&ssp_regs->hw_ssp_cmd0); + reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); + reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + reg |= SSP_CMD0_APPEND_8CYC; + writel(reg, &ssp_regs->hw_ssp_cmd0); + + /* Command argument */ + writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); + + /* Set up data */ + if (data) { + /* READ or WRITE */ + if (data->flags & MMC_DATA_READ) { + ctrl0 |= SSP_CTRL0_READ; +#if !CONFIG_IS_ENABLED(DM_MMC) + } else if (priv->mmc_is_wp && + priv->mmc_is_wp(devnum)) { + printf("MMC%d: Can not write a locked card!\n", devnum); + return -EOPNOTSUPP; +#endif + } + ctrl0 |= SSP_CTRL0_DATA_XFER; + + reg = data->blocksize * data->blocks; +#if defined(CONFIG_MX23) + ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK; + + clrsetbits_le32(&ssp_regs->hw_ssp_cmd0, + SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK, + ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) | + ((ffs(data->blocksize) - 1) << + SSP_CMD0_BLOCK_SIZE_OFFSET)); +#elif defined(CONFIG_MX28) + writel(reg, &ssp_regs->hw_ssp_xfer_size); + + reg = ((data->blocks - 1) << + SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | + ((ffs(data->blocksize) - 1) << + SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); + writel(reg, &ssp_regs->hw_ssp_block_size); +#endif + } + + /* Kick off the command */ + ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; + writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); + + /* Wait for the command to complete */ + timeout = MXSMMC_MAX_TIMEOUT; + while (--timeout) { + udelay(1000); + reg = readl(&ssp_regs->hw_ssp_status); + if (!(reg & SSP_STATUS_CMD_BUSY)) + break; + } + + if (!timeout) { + printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx); + return -ETIMEDOUT; + } + + /* Check command timeout */ + if (reg & SSP_STATUS_RESP_TIMEOUT) { + printf("MMC%d: Command %d timeout (status 0x%08x)\n", + devnum, cmd->cmdidx, reg); + return -ETIMEDOUT; + } + + /* Check command errors */ + if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { + printf("MMC%d: Command %d error (status 0x%08x)!\n", + devnum, cmd->cmdidx, reg); + return -ECOMM; + } + + /* Copy response to response buffer */ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); + cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); + cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); + cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); + } else + cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); + + /* Return if no data to process */ + if (!data) + return 0; + + if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { + ret = mxsmmc_send_cmd_pio(priv, data); + if (ret) { + printf("MMC%d: Data timeout with command %d " + "(status 0x%08x)!\n", devnum, cmd->cmdidx, reg); + return ret; + } + } else { + ret = mxsmmc_send_cmd_dma(priv, data); + if (ret) { + printf("MMC%d: DMA transfer failed\n", devnum); + return ret; + } + } + + /* Check data errors */ + reg = readl(&ssp_regs->hw_ssp_status); + if (reg & + (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | + SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { + printf("MMC%d: Data error with command %d (status 0x%08x)!\n", + devnum, cmd->cmdidx, reg); + return -ECOMM; + } + + return 0; +} + +#if CONFIG_IS_ENABLED(DM_MMC) +/* Base numbers of i.MX2[38] clk for ssp0 IP block */ +#define MXS_SSP_IMX23_CLKID_SSP0 33 +#define MXS_SSP_IMX28_CLKID_SSP0 46 + +static int mxsmmc_get_cd(struct udevice *dev) +{ + struct mxsmmc_platdata *plat = dev_get_platdata(dev); + struct mxsmmc_priv *priv = dev_get_priv(dev); + struct mxs_ssp_regs *ssp_regs = priv->regs; + + if (plat->non_removable) + return 1; + + return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT); +} + +static int mxsmmc_set_ios(struct udevice *dev) +{ + struct mxsmmc_platdata *plat = dev_get_platdata(dev); + struct mxsmmc_priv *priv = dev_get_priv(dev); + struct mxs_ssp_regs *ssp_regs = priv->regs; + struct mmc *mmc = &plat->mmc; + + /* Set the clock speed */ + if (mmc->clock) + mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000); + + switch (mmc->bus_width) { + case 1: + priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; + break; + case 4: + priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; + break; + case 8: + priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; + break; + } + + /* Set the bus width */ + clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, + SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); + + debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum, + mmc->bus_width); + + return 0; +} + +static int mxsmmc_init(struct udevice *dev) +{ + struct mxsmmc_priv *priv = dev_get_priv(dev); + struct mxs_ssp_regs *ssp_regs = priv->regs; + + /* Reset SSP */ + mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); + + /* Reconfigure the SSP block for MMC operation */ + writel(SSP_CTRL1_SSP_MODE_SD_MMC | + SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | + SSP_CTRL1_DMA_ENABLE | + SSP_CTRL1_POLARITY | + SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | + SSP_CTRL1_DATA_CRC_IRQ_EN | + SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | + SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | + SSP_CTRL1_RESP_ERR_IRQ_EN, + &ssp_regs->hw_ssp_ctrl1_set); + + /* Set initial bit clock 400 KHz */ + mxs_set_ssp_busclock(priv->clkid, 400); + + /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ + writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); + udelay(200); + writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); + + return 0; +} + +static int mxsmmc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mxsmmc_platdata *plat = dev_get_platdata(dev); + struct mxsmmc_priv *priv = dev_get_priv(dev); + struct blk_desc *bdesc; + struct mmc *mmc; + int ret, clkid; + + debug("%s: probe\n", __func__); + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_fsl_imx_mmc *dtplat = &plat->dtplat; + struct phandle_1_arg *p1a = &dtplat->clocks[0]; + + priv->buswidth = dtplat->bus_width; + priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0]; + priv->dma_channel = dtplat->dmas[1]; + clkid = p1a->arg[0]; + plat->non_removable = dtplat->non_removable; + + debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n", + priv->regs, priv->buswidth, clkid, plat->non_removable); +#else + priv->regs = (struct mxs_ssp_regs *)plat->base; + priv->dma_channel = plat->dma_id; + clkid = plat->clk_id; +#endif + +#ifdef CONFIG_MX28 + priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0; +#else /* CONFIG_MX23 */ + priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0; +#endif + mmc = &plat->mmc; + mmc->cfg = &plat->cfg; + mmc->dev = dev; + + priv->desc = mxs_dma_desc_alloc(); + if (!priv->desc) { + printf("%s: Cannot allocate DMA descriptor\n", __func__); + return -ENOMEM; + } + + ret = mxs_dma_init_channel(priv->dma_channel); + if (ret) + return ret; + + plat->cfg.name = "MXS MMC"; + plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + + plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | + MMC_MODE_HS_52MHz | MMC_MODE_HS; + + /* + * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz + * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), + * CLOCK_DIVIDE has to be an even value from 2 to 254, and + * CLOCK_RATE could be any integer from 0 to 255. + */ + plat->cfg.f_min = 400000; + plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2; + plat->cfg.b_max = 0x20; + + bdesc = mmc_get_blk_desc(mmc); + if (!bdesc) { + printf("%s: No block device descriptor!\n", __func__); + return -ENODEV; + } + + if (plat->non_removable) + bdesc->removable = 0; + + ret = mxsmmc_init(dev); + if (ret) + printf("%s: MMC%d init error %d\n", __func__, + bdesc->devnum, ret); + + /* Set the initial clock speed */ + mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); + + upriv->mmc = mmc; + + return 0; +}; + +#if CONFIG_IS_ENABLED(BLK) +static int mxsmmc_bind(struct udevice *dev) +{ + struct mxsmmc_platdata *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} +#endif + +static const struct dm_mmc_ops mxsmmc_ops = { + .get_cd = mxsmmc_get_cd, + .send_cmd = mxsmmc_send_cmd, + .set_ios = mxsmmc_set_ios, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int mxsmmc_ofdata_to_platdata(struct udevice *bus) +{ + struct mxsmmc_platdata *plat = bus->platdata; + u32 prop[2]; + int ret; + + plat->base = dev_read_addr(bus); + plat->buswidth = + dev_read_u32_default(bus, "bus-width", 1); + plat->non_removable = dev_read_bool(bus, "non-removable"); + + ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop)); + if (ret) { + printf("%s: Reading 'dmas' property failed!\n", __func__); + return ret; + } + plat->dma_id = prop[1]; + + ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop)); + if (ret) { + printf("%s: Reading 'clocks' property failed!\n", __func__); + return ret; + } + plat->clk_id = prop[1]; + + debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n", + __func__, (uint)plat->base, plat->buswidth, + plat->non_removable ? "non-removable" : NULL, + plat->dma_id, plat->clk_id); + + return 0; +} + +static const struct udevice_id mxsmmc_ids[] = { + { .compatible = "fsl,imx23-mmc", }, + { .compatible = "fsl,imx28-mmc", }, + { /* sentinel */ } +}; +#endif + +U_BOOT_DRIVER(mxsmmc) = { +#ifdef CONFIG_MX28 + .name = "fsl_imx28_mmc", +#else /* CONFIG_MX23 */ + .name = "fsl_imx23_mmc", +#endif + .id = UCLASS_MMC, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = mxsmmc_ids, + .ofdata_to_platdata = mxsmmc_ofdata_to_platdata, +#endif + .ops = &mxsmmc_ops, +#if CONFIG_IS_ENABLED(BLK) + .bind = mxsmmc_bind, +#endif + .probe = mxsmmc_probe, + .priv_auto_alloc_size = sizeof(struct mxsmmc_priv), + .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata), +}; + +#endif /* CONFIG_DM_MMC */ From cf31914cf2cd681b3e3681523afbfffb8d8a119b Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Sep 2019 09:55:00 +0200 Subject: [PATCH 112/190] mmc: Replace printf with debug call for timeouts in the i.MX28 mxs driver This change replaces printf() with debug() for the notification about commands timeouts. This is done on purpose (also other drivers use such approach - dw_mmc.c, mvebu_mmc.c), as the mmc core code (mmc.c) uses timeouts to assess if one is using sd card or eMMC device. In such situation timeout is a some kind of a "normal" behavior and there shall not be any output to the console. There is no impact on boot time for boards using this driver (even in SPL) when two extra timeouts are returned (no SD card present, only eMMC available). Boot time tested with grabserial: sudo grabserial -b 115200 -d /dev/ttyUSB1 -e 30 -t -m "^U-Boot SPL*" Signed-off-by: Lukasz Majewski --- drivers/mmc/mxsmmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 7ea47f98017..9414eff42ba 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -432,8 +432,8 @@ mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) /* Check command timeout */ if (reg & SSP_STATUS_RESP_TIMEOUT) { - printf("MMC%d: Command %d timeout (status 0x%08x)\n", - devnum, cmd->cmdidx, reg); + debug("MMC%d: Command %d timeout (status 0x%08x)\n", + devnum, cmd->cmdidx, reg); return -ETIMEDOUT; } From c883d6a0f408b0f319637a7e9b2d6099ada75a9f Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Sep 2019 09:55:01 +0200 Subject: [PATCH 113/190] spi: Add support for SPL_OF_PLATDATA to mxs_gpio.c driver After this patch the mxs_gpio.c DM/DTS driver can be used at early SPL to read states of gpio pins (and for example alter the boot flow). It was necessary to adjust its name to 'fsl_imx_2{38}_gpio' to match requirements for SPL_OF_PLATDATA usage. Signed-off-by: Lukasz Majewski --- drivers/gpio/mxs_gpio.c | 72 +++++++++++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index b2451fdda8a..5795155e3ed 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -131,9 +131,16 @@ int name_to_gpio(const char *name) #else /* CONFIG_DM_GPIO */ #include #include +#include #include #define MXS_MAX_GPIO_PER_BANK 32 +#ifdef CONFIG_MX28 +#define dtd_fsl_imx_gpio dtd_fsl_imx28_gpio +#else /* CONFIG_MX23 */ +#define dtd_fsl_imx_gpio dtd_fsl_imx23_gpio +#endif + DECLARE_GLOBAL_DATA_PTR; /* * According to i.MX28 Reference Manual: @@ -146,6 +153,14 @@ DECLARE_GLOBAL_DATA_PTR; * Bank 4: 0-20 -> 21 PINS */ +struct mxs_gpio_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_fsl_imx_gpio dtplat; +#endif + unsigned int bank; + int gpio_ranges; +}; + struct mxs_gpio_priv { unsigned int bank; }; @@ -223,22 +238,19 @@ static const struct dm_gpio_ops gpio_mxs_ops = { static int mxs_gpio_probe(struct udevice *dev) { + struct mxs_gpio_platdata *plat = dev_get_platdata(dev); struct mxs_gpio_priv *priv = dev_get_priv(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct fdtdec_phandle_args args; - int node = dev_of_offset(dev); char name[16], *str; - fdt_addr_t addr; - int ret; - - addr = devfdt_get_addr(dev); - if (addr == FDT_ADDR_T_NONE) { - printf("%s: No 'reg' property defined!\n", __func__); - return -EINVAL; - } - - priv->bank = (unsigned int)addr; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_fsl_imx_gpio *dtplat = &plat->dtplat; + priv->bank = (unsigned int)dtplat->reg[0]; + uc_priv->gpio_count = dtplat->gpio_ranges[3]; +#else + priv->bank = (unsigned int)plat->bank; + uc_priv->gpio_count = plat->gpio_ranges; +#endif snprintf(name, sizeof(name), "GPIO%d_", priv->bank); str = strdup(name); if (!str) @@ -246,16 +258,33 @@ static int mxs_gpio_probe(struct udevice *dev) uc_priv->bank_name = str; + debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name, + uc_priv->gpio_count, priv->bank); + + return 0; +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int mxs_ofdata_to_platdata(struct udevice *dev) +{ + struct mxs_gpio_platdata *plat = dev->platdata; + struct fdtdec_phandle_args args; + int node = dev_of_offset(dev); + int ret; + + plat->bank = devfdt_get_addr(dev); + if (plat->bank == FDT_ADDR_T_NONE) { + printf("%s: No 'reg' property defined!\n", __func__); + return -EINVAL; + } + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", NULL, 3, 0, &args); if (ret) printf("%s: 'gpio-ranges' not defined - using default!\n", __func__); - uc_priv->gpio_count = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK; - - debug("%s: %s: %d pins\n", __func__, uc_priv->bank_name, - uc_priv->gpio_count); + plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK; return 0; } @@ -265,13 +294,22 @@ static const struct udevice_id mxs_gpio_ids[] = { { .compatible = "fsl,imx28-gpio" }, { } }; +#endif U_BOOT_DRIVER(gpio_mxs) = { - .name = "gpio_mxs", +#ifdef CONFIG_MX28 + .name = "fsl_imx28_gpio", +#else /* CONFIG_MX23 */ + .name = "fsl_imx23_gpio", +#endif .id = UCLASS_GPIO, .ops = &gpio_mxs_ops, .probe = mxs_gpio_probe, .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv), + .platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata), +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = mxs_gpio_ids, + .ofdata_to_platdata = mxs_ofdata_to_platdata, +#endif }; #endif /* CONFIG_DM_GPIO */ From e4b91f085d4259f187052ff724c80af38fc11b18 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Fri, 20 Sep 2019 22:49:06 +0200 Subject: [PATCH 114/190] imx: wandboard: convert FEC support to DM_ETH Remove CONFIG_DM_ETH conversion warning to avoid board removal. Signed-off-by: Anatolij Gustschin --- arch/arm/dts/imx6qdl-wandboard.dtsi | 10 ++++++++++ board/wandboard/wandboard.c | 23 +---------------------- configs/wandboard_defconfig | 3 +++ include/configs/wandboard.h | 8 -------- 4 files changed, 14 insertions(+), 30 deletions(-) diff --git a/arch/arm/dts/imx6qdl-wandboard.dtsi b/arch/arm/dts/imx6qdl-wandboard.dtsi index 90aa43d21bb..35a88bf5a76 100644 --- a/arch/arm/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/dts/imx6qdl-wandboard.dtsi @@ -229,11 +229,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-handle = <ðphy>; phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + }; + }; }; &spdif { diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 69cdf3e9c96..11acbad78b7 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -71,21 +71,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { }; static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), /* AR8031 PHY Reset */ IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; @@ -358,13 +343,6 @@ static void setup_display(void) } #endif /* CONFIG_VIDEO_IPUV3 */ -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - int board_early_init_f(void) { setup_iomux_uart(); @@ -464,6 +442,7 @@ int board_late_init(void) else env_set("board_name", "B1"); #endif + setup_iomux_enet(); return 0; } diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index a8b6b413234..d7eb8fd4b37 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -57,6 +57,9 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 8faf5f0f789..a0a78eab27b 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -40,14 +40,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_PHY_ATHEROS - /* Framebuffer */ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN From 210e443d5ea8aee24a54048fc9a6d55cfebde9b2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Oct 2019 08:05:57 -0300 Subject: [PATCH 115/190] mx28evk: README: Fix location for the generic mxs README doc/README.mxs no longer exists. It has been renamed doc/imx/common/mxs.txt, so fix the mx28evk README accordingly. Signed-off-by: Fabio Estevam --- board/freescale/mx28evk/README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index b8bee8931c5..d32f0efb332 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -58,5 +58,5 @@ It is possible to solder a SOIC memory on U49 or use a DIP8 on J89. To get SPI communication to work R320, R321,R322 and C178 need to be populated. Look in the schematics for the proper component values. -Follow the instructions from doc/README.mxs to generate a bootable SD card or -to generate a binary to be flashed into SPI NOR. +Follow the instructions from doc/imx/common/mxs.txt to generate a bootable +SD card or to generate a binary to be flashed into SPI NOR. From 904c31fe9f08be73ec17a7b21f9832366af7da18 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Oct 2019 08:05:58 -0300 Subject: [PATCH 116/190] imx: mxs: Fix location for the elftosb tool The Denx FTP location is no longer reachable. Switch to the Timesys repository instead. Signed-off-by: Fabio Estevam --- doc/imx/common/mxs.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/imx/common/mxs.txt b/doc/imx/common/mxs.txt index e23ab9cc6d9..372062c0eaf 100644 --- a/doc/imx/common/mxs.txt +++ b/doc/imx/common/mxs.txt @@ -57,7 +57,7 @@ writing of this document, that is "10.12.01". To obtain the file from command line, use: $ VER="10.12.01" - $ wget ftp://ftp.denx.de/pub/tools/elftosb-${VER}.tar.gz + $ wget http://repository.timesys.com/buildsources/e/elftosb/elftosb-10.12.01/elftosb-${VER}.tar.gz Extract the file: From 6745dac4946656771d320ba6887e863ae64c8b3e Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Thu, 26 Sep 2019 15:47:08 +0200 Subject: [PATCH 117/190] ARM: dts: pcl063: add usdhc reset pin of eMMC pcl063 phycore SoM with eMMC also got usdhc reset pin, add reset pin to pinmux. Signed-off-by: Parthiban Nallathambi --- arch/arm/dts/pcl063-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/pcl063-common.dtsi b/arch/arm/dts/pcl063-common.dtsi index 2b14b2dc5fa..b88dde2fb02 100644 --- a/arch/arm/dts/pcl063-common.dtsi +++ b/arch/arm/dts/pcl063-common.dtsi @@ -113,7 +113,7 @@ pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 @@ -191,6 +191,7 @@ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170f9 >; }; }; From d08a194871fdf91b2ccdbaf02e35ed9443e0e170 Mon Sep 17 00:00:00 2001 From: Patrick Wildt Date: Thu, 3 Oct 2019 15:51:50 +0200 Subject: [PATCH 118/190] imx: add support for i.MX8MQ power domain controller Add support for the power domain controller that's used on the i.MX8MQ. This will be needed to be able to power on the PCIe controller. Bindings taken from Linux, driver implementation taken from the i.MX8 power domain controller and adjusted for the i.MX8M SoC. Signed-off-by: Patrick Wildt --- arch/arm/dts/fsl-imx8mq.dtsi | 38 ++++- .../arm/include/asm/arch-imx8m/power-domain.h | 15 ++ configs/imx8mq_evk_defconfig | 2 + drivers/power/domain/Kconfig | 7 + drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8m-power-domain.c | 137 ++++++++++++++++++ include/dt-bindings/power/imx8mq-power.h | 21 +++ include/imx_sip.h | 3 + 8 files changed, 218 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8m/power-domain.h create mode 100644 drivers/power/domain/imx8m-power-domain.c create mode 100755 include/dt-bindings/power/imx8mq-power.h diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi index 814a1b7df4c..fbf50098865 100644 --- a/arch/arm/dts/fsl-imx8mq.dtsi +++ b/arch/arm/dts/fsl-imx8mq.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include #include / { @@ -71,12 +72,6 @@ interrupt-parent = <&gic>; }; - power: power-controller { - compatible = "fsl,imx8mq-pm-domain"; - num-domains = <11>; - #power-domain-cells = <1>; - }; - pwm2: pwm@30670000 { compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; reg = <0x0 0x30670000 0x0 0x10000>; @@ -276,6 +271,37 @@ interrupts = ; #interrupt-cells = <3>; interrupt-parent = <&gic>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_pcie2>; + }; + + pgc_pcie2: power-domain@a { + #power-domain-cells = <0>; + reg = ; + }; + }; }; usdhc1: usdhc@30b40000 { diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h new file mode 100644 index 00000000000..0f94945894e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/power-domain.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 NXP + */ + +#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H +#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H + +struct imx8m_power_domain_platdata { + int resource_id; + int has_pd; + struct power_domain pd; +}; + +#endif diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 8d3cdec22bb..8fd07f689b2 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -37,6 +37,8 @@ CONFIG_FSL_USDHC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 06bba6220b2..7e2d6a90bff 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -23,6 +23,13 @@ config IMX8_POWER_DOMAIN Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC requests to the SCU. +config IMX8M_POWER_DOMAIN + bool "Enable i.MX8M power domain driver" + depends on POWER_DOMAIN && ARCH_IMX8M + help + Enable support for manipulating NXP i.MX8M on-SoC power domains via + requests to the ATF. + config MTK_POWER_DOMAIN bool "Enable the MediaTek power domain driver" depends on POWER_DOMAIN && ARCH_MEDIATEK diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 695aafe17d2..4d87d7c7f9e 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o +obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c new file mode 100644 index 00000000000..164fb3d31dd --- /dev/null +++ b/drivers/power/domain/imx8m-power-domain.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int imx8m_power_domain_request(struct power_domain *power_domain) +{ + return 0; +} + +static int imx8m_power_domain_free(struct power_domain *power_domain) +{ + return 0; +} + +static int imx8m_power_domain_on(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8m_power_domain_platdata *pdata; + pdata = dev_get_platdata(dev); + + if (pdata->resource_id < 0) + return -EINVAL; + + if (pdata->has_pd) + power_domain_on(&pdata->pd); + + call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 1); + + return 0; +} + +static int imx8m_power_domain_off(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8m_power_domain_platdata *pdata; + pdata = dev_get_platdata(dev); + + if (pdata->resource_id < 0) + return -EINVAL; + + call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 0); + + if (pdata->has_pd) + power_domain_off(&pdata->pd); + + return 0; +} + +static int imx8m_power_domain_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + return 0; +} + +static int imx8m_power_domain_bind(struct udevice *dev) +{ + int offset; + const char *name; + int ret = 0; + + offset = dev_of_offset(dev); + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + /* Bind the subnode to this driver */ + name = fdt_get_name(gd->fdt_blob, offset, NULL); + + ret = device_bind_with_driver_data(dev, dev->driver, name, + dev->driver_data, + offset_to_ofnode(offset), + NULL); + + if (ret == -ENODEV) + printf("Driver '%s' refuses to bind\n", + dev->driver->name); + + if (ret) + printf("Error binding driver '%s': %d\n", + dev->driver->name, ret); + } + + return 0; +} + +static int imx8m_power_domain_probe(struct udevice *dev) +{ + return 0; +} + +static int imx8m_power_domain_ofdata_to_platdata(struct udevice *dev) +{ + struct imx8m_power_domain_platdata *pdata = dev_get_platdata(dev); + + pdata->resource_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "reg", -1); + + if (!power_domain_get(dev, &pdata->pd)) + pdata->has_pd = 1; + + return 0; +} + +static const struct udevice_id imx8m_power_domain_ids[] = { + { .compatible = "fsl,imx8mq-gpc" }, + { } +}; + +struct power_domain_ops imx8m_power_domain_ops = { + .request = imx8m_power_domain_request, + .free = imx8m_power_domain_free, + .on = imx8m_power_domain_on, + .off = imx8m_power_domain_off, + .of_xlate = imx8m_power_domain_of_xlate, +}; + +U_BOOT_DRIVER(imx8m_power_domain) = { + .name = "imx8m_power_domain", + .id = UCLASS_POWER_DOMAIN, + .of_match = imx8m_power_domain_ids, + .bind = imx8m_power_domain_bind, + .probe = imx8m_power_domain_probe, + .ofdata_to_platdata = imx8m_power_domain_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct imx8m_power_domain_platdata), + .ops = &imx8m_power_domain_ops, +}; diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h new file mode 100755 index 00000000000..8a513bd9166 --- /dev/null +++ b/include/dt-bindings/power/imx8mq-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2018 Pengutronix, Lucas Stach + */ + +#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ +#define __DT_BINDINGS_IMX8MQ_POWER_H__ + +#define IMX8M_POWER_DOMAIN_MIPI 0 +#define IMX8M_POWER_DOMAIN_PCIE1 1 +#define IMX8M_POWER_DOMAIN_USB_OTG1 2 +#define IMX8M_POWER_DOMAIN_USB_OTG2 3 +#define IMX8M_POWER_DOMAIN_DDR1 4 +#define IMX8M_POWER_DOMAIN_GPU 5 +#define IMX8M_POWER_DOMAIN_VPU 6 +#define IMX8M_POWER_DOMAIN_DISP 7 +#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 +#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 +#define IMX8M_POWER_DOMAIN_PCIE2 10 + +#endif diff --git a/include/imx_sip.h b/include/imx_sip.h index fbb6c5ecdc8..139ff61b8ac 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -6,6 +6,9 @@ #ifndef _IMX_SIP_H__ #define _IMX_SIP_H_ +#define IMX_SIP_GPC 0xC2000000 +#define IMX_SIP_GPC_PM_DOMAIN 0x03 + #define IMX_SIP_SRC 0xC2000005 #define IMX_SIP_SRC_M4_START 0x00 #define IMX_SIP_SRC_M4_STARTED 0x01 From 6300dc4c61c9eccc9960bd9cd9b163032992fb4a Mon Sep 17 00:00:00 2001 From: Patrick Wildt Date: Thu, 3 Oct 2019 16:08:35 +0200 Subject: [PATCH 119/190] imx: add support for i.MX7/i.MX8MQ reset controller Add support for the reset controller that's used on the i.MX7D and i.MX8MQ. This will be needed to be able to assert the PCIe reset pins. Bindings taken from Linux, driver implementation mostly taken from Linux and adjusted to U-Boot infrastructure. Signed-off-by: Patrick Wildt Reviewed-by: Fabio Estevam --- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-imx7.c | 312 +++++++++++++++++++++++ include/dt-bindings/reset/imx7-reset.h | 52 ++++ include/dt-bindings/reset/imx8mq-reset.h | 64 +++++ 5 files changed, 436 insertions(+) create mode 100644 drivers/reset/reset-imx7.c create mode 100644 include/dt-bindings/reset/imx7-reset.h create mode 100755 include/dt-bindings/reset/imx8mq-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6ec6f39c85f..976f3a701c5 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -127,4 +127,11 @@ config RESET_HISILICON help Support for reset controller on HiSilicon SoCs. +config RESET_IMX7 + bool "i.MX7/8 Reset Driver" + depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M) + default y + help + Support for reset controller on i.MX7/8 SoCs. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 7fec75bb492..f5875fce099 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o +obj-$(CONFIG_RESET_IMX7) += reset-imx7.o diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c new file mode 100644 index 00000000000..f2ca5cf8015 --- /dev/null +++ b/drivers/reset/reset-imx7.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, Impinj, Inc. + */ + +#include +#include +#include +#include +#include +#include + +struct imx7_reset_priv { + void __iomem *base; + struct reset_ops ops; +}; + +struct imx7_src_signal { + unsigned int offset, bit; +}; + +enum imx7_src_registers { + SRC_A7RCR0 = 0x0004, + SRC_M4RCR = 0x000c, + SRC_ERCR = 0x0014, + SRC_HSICPHY_RCR = 0x001c, + SRC_USBOPHY1_RCR = 0x0020, + SRC_USBOPHY2_RCR = 0x0024, + SRC_MIPIPHY_RCR = 0x0028, + SRC_PCIEPHY_RCR = 0x002c, + SRC_DDRC_RCR = 0x1000, +}; + +static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { + [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, + [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) }, + [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) }, + [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) }, + [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) }, + [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) }, + [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) }, + [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) }, + [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) }, + [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) }, + [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, + [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, + [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) }, + [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) }, + [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) }, + [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) }, + [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) }, + [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) }, + [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) }, + [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) }, + [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, + [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, + [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, + [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, + [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) }, + [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, +}; + +static int imx7_reset_deassert_imx7(struct reset_ctl *rst) +{ + struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + const struct imx7_src_signal *sig = imx7_src_signals; + u32 val; + + if (rst->id >= IMX7_RESET_NUM) + return -EINVAL; + + if (rst->id == IMX7_RESET_PCIEPHY) { + /* + * wait for more than 10us to release phy g_rst and + * btnrst + */ + udelay(10); + } + + val = readl(priv->base + sig[rst->id].offset); + switch (rst->id) { + case IMX7_RESET_PCIE_CTRL_APPS_EN: + val |= sig[rst->id].bit; + break; + default: + val &= ~sig[rst->id].bit; + break; + } + writel(val, priv->base + sig[rst->id].offset); + + return 0; +} + +static int imx7_reset_assert_imx7(struct reset_ctl *rst) +{ + struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + const struct imx7_src_signal *sig = imx7_src_signals; + u32 val; + + if (rst->id >= IMX7_RESET_NUM) + return -EINVAL; + + val = readl(priv->base + sig[rst->id].offset); + switch (rst->id) { + case IMX7_RESET_PCIE_CTRL_APPS_EN: + val &= ~sig[rst->id].bit; + break; + default: + val |= sig[rst->id].bit; + break; + } + writel(val, priv->base + sig[rst->id].offset); + + return 0; +} + +enum imx8mq_src_registers { + SRC_A53RCR0 = 0x0004, + SRC_HDMI_RCR = 0x0030, + SRC_DISP_RCR = 0x0034, + SRC_GPU_RCR = 0x0040, + SRC_VPU_RCR = 0x0044, + SRC_PCIE2_RCR = 0x0048, + SRC_MIPIPHY1_RCR = 0x004c, + SRC_MIPIPHY2_RCR = 0x0050, + SRC_DDRC2_RCR = 0x1004, +}; + +static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { + [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, + [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, + [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, + [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, + [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, + [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, + [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, + [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, + [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, + [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, + [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, + [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, + [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, + [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, + [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, + [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, + [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, + [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, + [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) }, + [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, + [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, + [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, + [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, + [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, + [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, + [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, + [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, + BIT(2) | BIT(1) }, + [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, + [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, + [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, + [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, + [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) }, + [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, + [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, + [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR, + BIT(2) | BIT(1) }, + [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) }, + [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) }, + [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) }, + [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) }, + [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) }, + [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) }, + [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) }, + [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) }, + [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) }, + [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) }, + [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) }, + [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) }, + [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) }, + [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) }, + [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, +}; + +static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst) +{ + struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + const struct imx7_src_signal *sig = imx8mq_src_signals; + u32 val; + + if (rst->id >= IMX8MQ_RESET_NUM) + return -EINVAL; + + if (rst->id == IMX8MQ_RESET_PCIEPHY || + rst->id == IMX8MQ_RESET_PCIEPHY2) { + /* + * wait for more than 10us to release phy g_rst and + * btnrst + */ + udelay(10); + } + + val = readl(priv->base + sig[rst->id].offset); + switch (rst->id) { + case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: + case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ + val |= sig[rst->id].bit; + break; + default: + val &= ~sig[rst->id].bit; + break; + } + writel(val, priv->base + sig[rst->id].offset); + + return 0; +} + +static int imx7_reset_assert_imx8mq(struct reset_ctl *rst) +{ + struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + const struct imx7_src_signal *sig = imx8mq_src_signals; + u32 val; + + if (rst->id >= IMX8MQ_RESET_NUM) + return -EINVAL; + + val = readl(priv->base + sig[rst->id].offset); + switch (rst->id) { + case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: + case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ + val &= ~sig[rst->id].bit; + break; + default: + val |= sig[rst->id].bit; + break; + } + writel(val, priv->base + sig[rst->id].offset); + + return 0; +} + +static int imx7_reset_assert(struct reset_ctl *rst) +{ + struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + return priv->ops.rst_assert(rst); +} + +static int imx7_reset_deassert(struct reset_ctl *rst) +{ + struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + return priv->ops.rst_deassert(rst); +} + +static int imx7_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int imx7_reset_request(struct reset_ctl *rst) +{ + return 0; +} + +static const struct reset_ops imx7_reset_reset_ops = { + .request = imx7_reset_request, + .free = imx7_reset_free, + .rst_assert = imx7_reset_assert, + .rst_deassert = imx7_reset_deassert, +}; + +static const struct udevice_id imx7_reset_ids[] = { + { .compatible = "fsl,imx7d-src" }, + { .compatible = "fsl,imx8mq-src" }, + { } +}; + +static int imx7_reset_probe(struct udevice *dev) +{ + struct imx7_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -ENOMEM; + + if (device_is_compatible(dev, "fsl,imx8mq-src")) { + priv->ops.rst_assert = imx7_reset_assert_imx8mq; + priv->ops.rst_deassert = imx7_reset_deassert_imx8mq; + } else if (device_is_compatible(dev, "fsl,imx7d-src")) { + priv->ops.rst_assert = imx7_reset_assert_imx7; + priv->ops.rst_deassert = imx7_reset_deassert_imx7; + } + + return 0; +} + +U_BOOT_DRIVER(imx7_reset) = { + .name = "imx7_reset", + .id = UCLASS_RESET, + .of_match = imx7_reset_ids, + .ops = &imx7_reset_reset_ops, + .probe = imx7_reset_probe, + .priv_auto_alloc_size = sizeof(struct imx7_reset_priv), +}; diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h new file mode 100644 index 00000000000..bb92452ffb8 --- /dev/null +++ b/include/dt-bindings/reset/imx7-reset.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Impinj, Inc. + * + * Author: Andrey Smirnov + */ + +#ifndef DT_BINDING_RESET_IMX7_H +#define DT_BINDING_RESET_IMX7_H + +#define IMX7_RESET_A7_CORE_POR_RESET0 0 +#define IMX7_RESET_A7_CORE_POR_RESET1 1 +#define IMX7_RESET_A7_CORE_RESET0 2 +#define IMX7_RESET_A7_CORE_RESET1 3 +#define IMX7_RESET_A7_DBG_RESET0 4 +#define IMX7_RESET_A7_DBG_RESET1 5 +#define IMX7_RESET_A7_ETM_RESET0 6 +#define IMX7_RESET_A7_ETM_RESET1 7 +#define IMX7_RESET_A7_SOC_DBG_RESET 8 +#define IMX7_RESET_A7_L2RESET 9 +#define IMX7_RESET_SW_M4C_RST 10 +#define IMX7_RESET_SW_M4P_RST 11 +#define IMX7_RESET_EIM_RST 12 +#define IMX7_RESET_HSICPHY_PORT_RST 13 +#define IMX7_RESET_USBPHY1_POR 14 +#define IMX7_RESET_USBPHY1_PORT_RST 15 +#define IMX7_RESET_USBPHY2_POR 16 +#define IMX7_RESET_USBPHY2_PORT_RST 17 +#define IMX7_RESET_MIPI_PHY_MRST 18 +#define IMX7_RESET_MIPI_PHY_SRST 19 + +/* + * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN + * and PCIEPHY_G_RST + */ +#define IMX7_RESET_PCIEPHY 20 +#define IMX7_RESET_PCIEPHY_PERST 21 + +/* + * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it + * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht + * of as one + */ +#define IMX7_RESET_PCIE_CTRL_APPS_EN 22 +#define IMX7_RESET_DDRC_PRST 23 +#define IMX7_RESET_DDRC_CORE_RST 24 + +#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 + +#define IMX7_RESET_NUM 26 + +#endif diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h new file mode 100755 index 00000000000..9a301082d36 --- /dev/null +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + * + * Author: Andrey Smirnov + */ + +#ifndef DT_BINDING_RESET_IMX8MQ_H +#define DT_BINDING_RESET_IMX8MQ_H + +#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MQ_RESET_A53_CORE_RESET0 4 +#define IMX8MQ_RESET_A53_CORE_RESET1 5 +#define IMX8MQ_RESET_A53_CORE_RESET2 6 +#define IMX8MQ_RESET_A53_CORE_RESET3 7 +#define IMX8MQ_RESET_A53_DBG_RESET0 8 +#define IMX8MQ_RESET_A53_DBG_RESET1 9 +#define IMX8MQ_RESET_A53_DBG_RESET2 10 +#define IMX8MQ_RESET_A53_DBG_RESET3 11 +#define IMX8MQ_RESET_A53_ETM_RESET0 12 +#define IMX8MQ_RESET_A53_ETM_RESET1 13 +#define IMX8MQ_RESET_A53_ETM_RESET2 14 +#define IMX8MQ_RESET_A53_ETM_RESET3 15 +#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MQ_RESET_A53_L2RESET 17 +#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 +#define IMX8MQ_RESET_OTG1_PHY_RESET 19 +#define IMX8MQ_RESET_OTG2_PHY_RESET 20 +#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 +#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 +#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 +#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 +#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 +#define IMX8MQ_RESET_PCIEPHY 26 +#define IMX8MQ_RESET_PCIEPHY_PERST 27 +#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 +#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 +#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DISP_RESET 31 +#define IMX8MQ_RESET_GPU_RESET 32 +#define IMX8MQ_RESET_VPU_RESET 33 +#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DDRC1_PRST 44 +#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 +#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 +#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ + +#define IMX8MQ_RESET_NUM 50 + +#endif From 63927b8fc7de6c0f75a8329b7f28f1e247b853bd Mon Sep 17 00:00:00 2001 From: Patrick Wildt Date: Thu, 3 Oct 2019 16:12:57 +0200 Subject: [PATCH 120/190] imx: add the i.MX8M reset controller node This patch adds the reset controller node to the i.MX8MQ SoC device tree. Signed-off-by: Patrick Wildt --- arch/arm/dts/fsl-imx8mq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi index fbf50098865..d0206c9dbe5 100644 --- a/arch/arm/dts/fsl-imx8mq.dtsi +++ b/arch/arm/dts/fsl-imx8mq.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -264,6 +265,12 @@ #clock-cells = <1>; }; + src: reset-controller@30390000 { + compatible = "fsl,imx8mq-src", "syscon"; + reg = <0x0 0x30390000 0x0 0x10000>; + #reset-cells = <1>; + }; + gpc: gpc@303a0000 { compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon"; reg = <0x0 0x303a0000 0x0 0x10000>; From 2845f86d951b1ffa3916e2ed7a6b5eed8d8d735a Mon Sep 17 00:00:00 2001 From: Patrick Wildt Date: Thu, 3 Oct 2019 16:13:24 +0200 Subject: [PATCH 121/190] imx: enable the reset controller on the i.MX8MQ EVK This patch makes sure that the reset controller driver is compiled for the i.MX8MQ EVK. Signed-off-by: Patrick Wildt --- configs/imx8mq_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 8fd07f689b2..f352f47ed58 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -42,4 +42,5 @@ CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y CONFIG_DM_THERMAL=y From 5b20d141f209a62596f38ee42b0622280636a7ae Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Mon, 23 Sep 2019 18:39:47 +0000 Subject: [PATCH 122/190] imx: Kconfig: Reduce default CONFIG_CSF_SIZE The default CSF_SIZE defined in Kconfig is too high and SPL cannot fit into the OCRAM in certain cases. The CSF cannot achieve 0x2000 length when using RSA 4K key which is the largest key size supported by HABv4. According to AN12056 "Encrypted Boot on HABv4 and CAAM Enabled Devices" it's recommended to pad CSF binary to 0x2000 and append DEK blob to deploy encrypted boot images. As the maximum DEK blob size is 0x58 we can reduce CSF_SIZE to 0x2060 which should cover both CSF and DEK blob length. Update default_image.c and image.c to align with this change and avoid a U-Boot proper authentication failure in HAB closed devices: Authenticate image from DDR location 0x877fffc0... bad magic magic=0x32 length=0x6131 version=0x38 bad length magic=0x32 length=0x6131 version=0x38 bad version magic=0x32 length=0x6131 version=0x38 spl: ERROR: image authentication fail Fixes: 96d27fb218 (Revert "habv4: tools: Avoid hardcoded CSF size for SPL targets") Reported-by: Jagan Teki Signed-off-by: Breno Lima --- arch/arm/mach-imx/Kconfig | 2 +- common/image.c | 7 ++++--- tools/default_image.c | 5 ++++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index d44f74e4745..f721eaf937c 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -45,7 +45,7 @@ config SECURE_BOOT config CSF_SIZE hex "Maximum size for Command Sequence File (CSF) binary" - default 0x4000 + default 0x2060 help Define the maximum size for Command Sequence File (CSF) binary this information is used to define the image boot data. diff --git a/common/image.c b/common/image.c index 179eef0bd2d..62ba6b3bfe9 100644 --- a/common/image.c +++ b/common/image.c @@ -61,6 +61,7 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, #endif /* !USE_HOSTCC*/ #include +#include #ifndef CONFIG_SYS_BARGSIZE #define CONFIG_SYS_BARGSIZE 512 @@ -378,9 +379,9 @@ void image_print_contents(const void *ptr) } } else if (image_check_type(hdr, IH_TYPE_FIRMWARE_IVT)) { printf("HAB Blocks: 0x%08x 0x0000 0x%08x\n", - image_get_load(hdr) - image_get_header_size(), - image_get_size(hdr) + image_get_header_size() - - 0x1FE0); + image_get_load(hdr) - image_get_header_size(), + (int)(image_get_size(hdr) + image_get_header_size() + + sizeof(flash_header_v2_t) - 0x2060)); } } diff --git a/tools/default_image.c b/tools/default_image.c index 4b7d1ed4a1a..f7990e28c06 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -19,6 +19,7 @@ #include #include #include +#include static image_header_t header; @@ -106,7 +107,9 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, if (params->type == IH_TYPE_FIRMWARE_IVT) /* Add size of CSF minus IVT */ - imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0; + imagesize = sbuf->st_size - sizeof(image_header_t) + + 0x2060 - sizeof(flash_header_v2_t); + else imagesize = sbuf->st_size - sizeof(image_header_t); From 0a1a45b7d67b548d504f4e42359338a0bd4dfcee Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 23 Sep 2019 18:05:05 +0200 Subject: [PATCH 123/190] imx: mx6ul_14x14_evk: fix link issue Since recent splash changes common code for splashscreen logo should be used instead of adding duplicated code under board directories. mx6ul_9x9_evk and mx6ul_14x14_evk configurations used old board specific logo code and do not link, fix them. Signed-off-by: Anatolij Gustschin Acked-by: Peng Fan --- .../mx6ul_14x14_evk/mx6ul_14x14_evk.c | 19 ++----------------- configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + include/configs/mx6ul_14x14_evk.h | 1 + 4 files changed, 5 insertions(+), 17 deletions(-) diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 8e5f365d35e..c98e98b4859 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -28,10 +28,6 @@ #include "../common/pfuze.h" #include #include -#ifdef CONFIG_DM_VIDEO -#include -#include -#endif DECLARE_GLOBAL_DATA_PTR; @@ -449,6 +445,8 @@ static int setup_lcd(void) return 0; } +#else +static inline int setup_lcd(void) { return 0; } #endif int board_early_init_f(void) @@ -505,21 +503,8 @@ int board_late_init(void) env_set("board_rev", "14X14"); #endif -#if defined(CONFIG_DM_VIDEO) - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); - if (ret) - return ret; - setup_lcd(); - ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, 0, 0, true); - if (ret) - return ret; -#endif - return 0; } diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index a458d90a34b..9177794ae98 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -68,3 +68,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 81f9b5b7145..0b3b2b1fb22 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -71,3 +71,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index f8a5fd30f32..87f88693c5a 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -60,6 +60,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ From d10d1386a0fae143ee96dee69bde2e63309913fb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Sep 2019 18:09:08 +0200 Subject: [PATCH 124/190] ARM: imx: Add QSPI boot mode for i.MX6UL/ULL This patch adds the missing boot mode detection for QSPI boot on i.MX6UL/ULL. Without it, booting with SPL from QSPI NOR does not work. Signed-off-by: Stefan Roese Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/mach-imx/spl.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index cda719226aa..f33b9f09622 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -94,6 +94,11 @@ u32 spl_boot_device(void) /* NAND Flash: 8.5.2, Table 8-10 */ case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX: return BOOT_DEVICE_NAND; +#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) + /* QSPI boot */ + case IMX6_BMODE_QSPI: + return BOOT_DEVICE_SPI; +#endif } return BOOT_DEVICE_NONE; } From 2a9f86b27724a56293c152a8b21ee473672cef90 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Sep 2019 18:09:09 +0200 Subject: [PATCH 125/190] ARM: imx: arch/arm/mach-imx/spl_qspi.cfg Similar to "spl_sd.cfg", this patch introduces "spl_qspi.cfg" so that all i.MX6 based boards can use it, when they use SPL and QSPI boot mode. Signed-off-by: Stefan Roese Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/mach-imx/spl_qspi.cfg | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 arch/arm/mach-imx/spl_qspi.cfg diff --git a/arch/arm/mach-imx/spl_qspi.cfg b/arch/arm/mach-imx/spl_qspi.cfg new file mode 100644 index 00000000000..88956e626ff --- /dev/null +++ b/arch/arm/mach-imx/spl_qspi.cfg @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + */ + +#define __ASSEMBLY__ +#include + +IMAGE_VERSION 2 +BOOT_FROM qspi + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif From 4f761dd237a446a89b1deaaf975e9af2c54241b1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Sep 2019 18:09:10 +0200 Subject: [PATCH 126/190] Kconfig: Set default BUILD_TARGET for ARCH_MX6 with SPL Use BUILD_TARGET to automatically build "u-boot-with-spl.imx" on MX6 targets with SPL. Signed-off-by: Stefan Roese Cc: Fabio Estevam Cc: Stefano Babic --- Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig index 1f0904f7045..66b059f749a 100644 --- a/Kconfig +++ b/Kconfig @@ -256,6 +256,7 @@ config BUILD_TARGET ARCH_SUNXI || RISCV) default "u-boot.kwb" if KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT + default "u-boot-with-spl.imx" if ARCH_MX6 && SPL help Some SoCs need special image types (e.g. U-Boot binary with a special header) as build targets. By defining From fa99af41e0da803d42ea90e688aa8d8fc371feea Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Tue, 27 Aug 2019 06:24:40 +0000 Subject: [PATCH 127/190] imx: mkimage_fit_atf: Fix FIT image for correct boot order Fix the FIT image metadata for i.MX8 to result in the intended boot order (SPL -> ATF -> U-Boot). Signed-off-by: Frieder Schrempf Signed-off-by: Peng Fan --- arch/arm/mach-imx/mkimage_fit_atf.sh | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh index 38c9858e849..ad81d5ecab2 100755 --- a/arch/arm/mach-imx/mkimage_fit_atf.sh +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh @@ -55,6 +55,7 @@ cat << __HEADER_EOF images { uboot@1 { description = "U-Boot (64-bit)"; + os = "u-boot"; data = /incbin/("$BL33"); type = "standalone"; arch = "arm64"; @@ -63,6 +64,7 @@ cat << __HEADER_EOF }; atf@1 { description = "ARM Trusted Firmware"; + os = "arm-trusted-firmware"; data = /incbin/("$BL31"); type = "firmware"; arch = "arm64"; @@ -114,8 +116,8 @@ if [ -f $BL32 ]; then cat << __CONF_SECTION_EOF config@$cnt { description = "$(basename $dtname .dtb)"; - firmware = "uboot@1"; - loadables = "atf@1", "tee@1"; + firmware = "atf@1"; + loadables = "uboot@1", "tee@1"; fdt = "fdt@$cnt"; }; __CONF_SECTION_EOF @@ -123,8 +125,8 @@ else cat << __CONF_SECTION1_EOF config@$cnt { description = "$(basename $dtname .dtb)"; - firmware = "uboot@1"; - loadables = "atf@1"; + firmware = "atf@1"; + loadables = "uboot@1"; fdt = "fdt@$cnt"; }; __CONF_SECTION1_EOF From 4b78bb504142ebc97efae6908e666cb0608ebf86 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:24:43 +0000 Subject: [PATCH 128/190] tools: imx8m_image: align spl bin image size The loader for the DDR firmware in drivers/ddr/imx/imx8m/helper.c uses a 4-byte-aligned address to load the firmware. In cases where OF is enabled in SPL the dtb will be appended to the SPL binary and can result in a binary that is not aligned correctly. If OF is not enabled in SPL, `_end` is already aligned correctly, but this patch does not hurt. To ensure the correct alignment we use dd to create a temporary file u-boot-spl-pad.bin with the correct padding. Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf Signed-off-by: Peng Fan --- tools/imx8m_image.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh index ec0881a1281..08a6a481800 100755 --- a/tools/imx8m_image.sh +++ b/tools/imx8m_image.sh @@ -35,8 +35,9 @@ if [ $post_process = 1 ]; then objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_imem_pad.bin cat lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin cat lpddr4_pmu_train_2d_imem_pad.bin $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin - cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin - rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin + dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync + cat spl/u-boot-spl-pad.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin + rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin spl/u-boot-spl-pad.bin fi fi From 28cb058ff748aa592014fcc8049b6bac1e2e4a2e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:24:47 +0000 Subject: [PATCH 129/190] ddr: imx8m: fix ddr firmware location when enable SPL OF With CONFIG_SPL_OF_CONTROL, the device tree will be padded to end of the u-boot-spl-nodtb.bin, however we also put the ddr firmware file to this location, so need to adapt the code with SPL OF and align to 4 bytes to ease copy firmware. Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/helper.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c index 61cd4f6db12..3e605353ea1 100644 --- a/drivers/ddr/imx/imx8m/helper.c +++ b/drivers/ddr/imx/imx8m/helper.c @@ -31,7 +31,17 @@ void ddr_load_train_firmware(enum fw_type type) unsigned long pr_to32, pr_from32; unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; unsigned long imem_start = (unsigned long)&_end + fw_offset; - unsigned long dmem_start = imem_start + IMEM_LEN; + unsigned long dmem_start; + +#ifdef CONFIG_SPL_OF_CONTROL + if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { + imem_start = roundup((unsigned long)&_end + + fdt_totalsize(gd->fdt_blob), 4) + + fw_offset; + } +#endif + + dmem_start = imem_start + IMEM_LEN; pr_from32 = imem_start; pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; From 478f944a96439085e4d5f3fb11a7e8f4fd39eef1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:24:50 +0000 Subject: [PATCH 130/190] imx8m: add image cfg for i.MX8MM lpddr4 There is no HDMI on i.MX8MM, so we need to remove HDMI entry, then we could not reuse imximage.cfg, so create a new one. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg new file mode 100644 index 00000000000..1a2e43e6718 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin From d968ae7ed67cfc85750a6e6964ea930a48036956 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:24:54 +0000 Subject: [PATCH 131/190] imx: add IMX8MQ kconfig entry Add IMX8MQ kconfig entry, preparing support IMX8MM Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 317dee9bc19..9c487870a65 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -4,6 +4,10 @@ config IMX8M bool select ROM_UNIFIED_SECTIONS +config IMX8MQ + bool + select IMX8M + config SYS_SOC default "imx8m" @@ -13,7 +17,7 @@ choice config TARGET_IMX8MQ_EVK bool "imx8mq_evk" - select IMX8M + select IMX8MQ select IMX8M_LPDDR4 endchoice From 1b1eaa0e127206e2061728dbe5ed34abb04c0951 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:24:57 +0000 Subject: [PATCH 132/190] imx: add IMX8MM kconfig entry Add IMX8MM kconfig entry Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 9c487870a65..35c978e8630 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -8,6 +8,10 @@ config IMX8MQ bool select IMX8M +config IMX8MM + bool + select IMX8M + config SYS_SOC default "imx8m" From 8619c393d890a18148408e687c248c45fae203cd Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:01 +0000 Subject: [PATCH 133/190] imx: imx8mm: add clock bindings header Import clock bindings header file from Linux 5.3.0-rc2 Signed-off-by: Peng Fan --- include/dt-bindings/clock/imx8mm-clock.h | 253 +++++++++++++++++++++++ 1 file changed, 253 insertions(+) create mode 100644 include/dt-bindings/clock/imx8mm-clock.h diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h new file mode 100644 index 00000000000..07e6c686f3e --- /dev/null +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H +#define __DT_BINDINGS_CLOCK_IMX8MM_H + +#define IMX8MM_CLK_DUMMY 0 +#define IMX8MM_CLK_32K 1 +#define IMX8MM_CLK_24M 2 +#define IMX8MM_OSC_HDMI_CLK 3 +#define IMX8MM_CLK_EXT1 4 +#define IMX8MM_CLK_EXT2 5 +#define IMX8MM_CLK_EXT3 6 +#define IMX8MM_CLK_EXT4 7 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_DRAM_PLL_REF_SEL 11 +#define IMX8MM_GPU_PLL_REF_SEL 12 +#define IMX8MM_VPU_PLL_REF_SEL 13 +#define IMX8MM_ARM_PLL_REF_SEL 14 +#define IMX8MM_SYS_PLL1_REF_SEL 15 +#define IMX8MM_SYS_PLL2_REF_SEL 16 +#define IMX8MM_SYS_PLL3_REF_SEL 17 +#define IMX8MM_AUDIO_PLL1 18 +#define IMX8MM_AUDIO_PLL2 19 +#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_DRAM_PLL 21 +#define IMX8MM_GPU_PLL 22 +#define IMX8MM_VPU_PLL 23 +#define IMX8MM_ARM_PLL 24 +#define IMX8MM_SYS_PLL1 25 +#define IMX8MM_SYS_PLL2 26 +#define IMX8MM_SYS_PLL3 27 +#define IMX8MM_AUDIO_PLL1_BYPASS 28 +#define IMX8MM_AUDIO_PLL2_BYPASS 29 +#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_DRAM_PLL_BYPASS 31 +#define IMX8MM_GPU_PLL_BYPASS 32 +#define IMX8MM_VPU_PLL_BYPASS 33 +#define IMX8MM_ARM_PLL_BYPASS 34 +#define IMX8MM_SYS_PLL1_BYPASS 35 +#define IMX8MM_SYS_PLL2_BYPASS 36 +#define IMX8MM_SYS_PLL3_BYPASS 37 +#define IMX8MM_AUDIO_PLL1_OUT 38 +#define IMX8MM_AUDIO_PLL2_OUT 39 +#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_DRAM_PLL_OUT 41 +#define IMX8MM_GPU_PLL_OUT 42 +#define IMX8MM_VPU_PLL_OUT 43 +#define IMX8MM_ARM_PLL_OUT 44 +#define IMX8MM_SYS_PLL1_OUT 45 +#define IMX8MM_SYS_PLL2_OUT 46 +#define IMX8MM_SYS_PLL3_OUT 47 +#define IMX8MM_SYS_PLL1_40M 48 +#define IMX8MM_SYS_PLL1_80M 49 +#define IMX8MM_SYS_PLL1_100M 50 +#define IMX8MM_SYS_PLL1_133M 51 +#define IMX8MM_SYS_PLL1_160M 52 +#define IMX8MM_SYS_PLL1_200M 53 +#define IMX8MM_SYS_PLL1_266M 54 +#define IMX8MM_SYS_PLL1_400M 55 +#define IMX8MM_SYS_PLL1_800M 56 +#define IMX8MM_SYS_PLL2_50M 57 +#define IMX8MM_SYS_PLL2_100M 58 +#define IMX8MM_SYS_PLL2_125M 59 +#define IMX8MM_SYS_PLL2_166M 60 +#define IMX8MM_SYS_PLL2_200M 61 +#define IMX8MM_SYS_PLL2_250M 62 +#define IMX8MM_SYS_PLL2_333M 63 +#define IMX8MM_SYS_PLL2_500M 64 +#define IMX8MM_SYS_PLL2_1000M 65 + +/* core */ +#define IMX8MM_CLK_A53_SRC 66 +#define IMX8MM_CLK_M4_SRC 67 +#define IMX8MM_CLK_VPU_SRC 68 +#define IMX8MM_CLK_GPU3D_SRC 69 +#define IMX8MM_CLK_GPU2D_SRC 70 +#define IMX8MM_CLK_A53_CG 71 +#define IMX8MM_CLK_M4_CG 72 +#define IMX8MM_CLK_VPU_CG 73 +#define IMX8MM_CLK_GPU3D_CG 74 +#define IMX8MM_CLK_GPU2D_CG 75 +#define IMX8MM_CLK_A53_DIV 76 +#define IMX8MM_CLK_M4_DIV 77 +#define IMX8MM_CLK_VPU_DIV 78 +#define IMX8MM_CLK_GPU3D_DIV 79 +#define IMX8MM_CLK_GPU2D_DIV 80 + +/* bus */ +#define IMX8MM_CLK_MAIN_AXI 81 +#define IMX8MM_CLK_ENET_AXI 82 +#define IMX8MM_CLK_NAND_USDHC_BUS 83 +#define IMX8MM_CLK_VPU_BUS 84 +#define IMX8MM_CLK_DISP_AXI 85 +#define IMX8MM_CLK_DISP_APB 86 +#define IMX8MM_CLK_DISP_RTRM 87 +#define IMX8MM_CLK_USB_BUS 88 +#define IMX8MM_CLK_GPU_AXI 89 +#define IMX8MM_CLK_GPU_AHB 90 +#define IMX8MM_CLK_NOC 91 +#define IMX8MM_CLK_NOC_APB 92 + +#define IMX8MM_CLK_AHB 93 +#define IMX8MM_CLK_AUDIO_AHB 94 +#define IMX8MM_CLK_IPG_ROOT 95 +#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 + +#define IMX8MM_CLK_DRAM_ALT 97 +#define IMX8MM_CLK_DRAM_APB 98 +#define IMX8MM_CLK_VPU_G1 99 +#define IMX8MM_CLK_VPU_G2 100 +#define IMX8MM_CLK_DISP_DTRC 101 +#define IMX8MM_CLK_DISP_DC8000 102 +#define IMX8MM_CLK_PCIE1_CTRL 103 +#define IMX8MM_CLK_PCIE1_PHY 104 +#define IMX8MM_CLK_PCIE1_AUX 105 +#define IMX8MM_CLK_DC_PIXEL 106 +#define IMX8MM_CLK_LCDIF_PIXEL 107 +#define IMX8MM_CLK_SAI1 108 +#define IMX8MM_CLK_SAI2 109 +#define IMX8MM_CLK_SAI3 110 +#define IMX8MM_CLK_SAI4 111 +#define IMX8MM_CLK_SAI5 112 +#define IMX8MM_CLK_SAI6 113 +#define IMX8MM_CLK_SPDIF1 114 +#define IMX8MM_CLK_SPDIF2 115 +#define IMX8MM_CLK_ENET_REF 116 +#define IMX8MM_CLK_ENET_TIMER 117 +#define IMX8MM_CLK_ENET_PHY_REF 118 +#define IMX8MM_CLK_NAND 119 +#define IMX8MM_CLK_QSPI 120 +#define IMX8MM_CLK_USDHC1 121 +#define IMX8MM_CLK_USDHC2 122 +#define IMX8MM_CLK_I2C1 123 +#define IMX8MM_CLK_I2C2 124 +#define IMX8MM_CLK_I2C3 125 +#define IMX8MM_CLK_I2C4 126 +#define IMX8MM_CLK_UART1 127 +#define IMX8MM_CLK_UART2 128 +#define IMX8MM_CLK_UART3 129 +#define IMX8MM_CLK_UART4 130 +#define IMX8MM_CLK_USB_CORE_REF 131 +#define IMX8MM_CLK_USB_PHY_REF 132 +#define IMX8MM_CLK_ECSPI1 133 +#define IMX8MM_CLK_ECSPI2 134 +#define IMX8MM_CLK_PWM1 135 +#define IMX8MM_CLK_PWM2 136 +#define IMX8MM_CLK_PWM3 137 +#define IMX8MM_CLK_PWM4 138 +#define IMX8MM_CLK_GPT1 139 +#define IMX8MM_CLK_WDOG 140 +#define IMX8MM_CLK_WRCLK 141 +#define IMX8MM_CLK_DSI_CORE 142 +#define IMX8MM_CLK_DSI_PHY_REF 143 +#define IMX8MM_CLK_DSI_DBI 144 +#define IMX8MM_CLK_USDHC3 145 +#define IMX8MM_CLK_CSI1_CORE 146 +#define IMX8MM_CLK_CSI1_PHY_REF 147 +#define IMX8MM_CLK_CSI1_ESC 148 +#define IMX8MM_CLK_CSI2_CORE 149 +#define IMX8MM_CLK_CSI2_PHY_REF 150 +#define IMX8MM_CLK_CSI2_ESC 151 +#define IMX8MM_CLK_PCIE2_CTRL 152 +#define IMX8MM_CLK_PCIE2_PHY 153 +#define IMX8MM_CLK_PCIE2_AUX 154 +#define IMX8MM_CLK_ECSPI3 155 +#define IMX8MM_CLK_PDM 156 +#define IMX8MM_CLK_VPU_H1 157 +#define IMX8MM_CLK_CLKO1 158 + +#define IMX8MM_CLK_ECSPI1_ROOT 159 +#define IMX8MM_CLK_ECSPI2_ROOT 160 +#define IMX8MM_CLK_ECSPI3_ROOT 161 +#define IMX8MM_CLK_ENET1_ROOT 162 +#define IMX8MM_CLK_GPT1_ROOT 163 +#define IMX8MM_CLK_I2C1_ROOT 164 +#define IMX8MM_CLK_I2C2_ROOT 165 +#define IMX8MM_CLK_I2C3_ROOT 166 +#define IMX8MM_CLK_I2C4_ROOT 167 +#define IMX8MM_CLK_OCOTP_ROOT 168 +#define IMX8MM_CLK_PCIE1_ROOT 169 +#define IMX8MM_CLK_PWM1_ROOT 170 +#define IMX8MM_CLK_PWM2_ROOT 171 +#define IMX8MM_CLK_PWM3_ROOT 172 +#define IMX8MM_CLK_PWM4_ROOT 173 +#define IMX8MM_CLK_QSPI_ROOT 174 +#define IMX8MM_CLK_NAND_ROOT 175 +#define IMX8MM_CLK_SAI1_ROOT 176 +#define IMX8MM_CLK_SAI1_IPG 177 +#define IMX8MM_CLK_SAI2_ROOT 178 +#define IMX8MM_CLK_SAI2_IPG 179 +#define IMX8MM_CLK_SAI3_ROOT 180 +#define IMX8MM_CLK_SAI3_IPG 181 +#define IMX8MM_CLK_SAI4_ROOT 182 +#define IMX8MM_CLK_SAI4_IPG 183 +#define IMX8MM_CLK_SAI5_ROOT 184 +#define IMX8MM_CLK_SAI5_IPG 185 +#define IMX8MM_CLK_SAI6_ROOT 186 +#define IMX8MM_CLK_SAI6_IPG 187 +#define IMX8MM_CLK_UART1_ROOT 188 +#define IMX8MM_CLK_UART2_ROOT 189 +#define IMX8MM_CLK_UART3_ROOT 190 +#define IMX8MM_CLK_UART4_ROOT 191 +#define IMX8MM_CLK_USB1_CTRL_ROOT 192 +#define IMX8MM_CLK_GPU3D_ROOT 193 +#define IMX8MM_CLK_USDHC1_ROOT 194 +#define IMX8MM_CLK_USDHC2_ROOT 195 +#define IMX8MM_CLK_WDOG1_ROOT 196 +#define IMX8MM_CLK_WDOG2_ROOT 197 +#define IMX8MM_CLK_WDOG3_ROOT 198 +#define IMX8MM_CLK_VPU_G1_ROOT 199 +#define IMX8MM_CLK_GPU_BUS_ROOT 200 +#define IMX8MM_CLK_VPU_H1_ROOT 201 +#define IMX8MM_CLK_VPU_G2_ROOT 202 +#define IMX8MM_CLK_PDM_ROOT 203 +#define IMX8MM_CLK_DISP_ROOT 204 +#define IMX8MM_CLK_DISP_AXI_ROOT 205 +#define IMX8MM_CLK_DISP_APB_ROOT 206 +#define IMX8MM_CLK_DISP_RTRM_ROOT 207 +#define IMX8MM_CLK_USDHC3_ROOT 208 +#define IMX8MM_CLK_TMU_ROOT 209 +#define IMX8MM_CLK_VPU_DEC_ROOT 210 +#define IMX8MM_CLK_SDMA1_ROOT 211 +#define IMX8MM_CLK_SDMA2_ROOT 212 +#define IMX8MM_CLK_SDMA3_ROOT 213 +#define IMX8MM_CLK_GPT_3M 214 +#define IMX8MM_CLK_ARM 215 +#define IMX8MM_CLK_PDM_IPG 216 +#define IMX8MM_CLK_GPU2D_ROOT 217 +#define IMX8MM_CLK_MU_ROOT 218 +#define IMX8MM_CLK_CSI1_ROOT 219 + +#define IMX8MM_CLK_DRAM_CORE 220 +#define IMX8MM_CLK_DRAM_ALT_ROOT 221 + +#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 + +#define IMX8MM_CLK_GPIO1_ROOT 223 +#define IMX8MM_CLK_GPIO2_ROOT 224 +#define IMX8MM_CLK_GPIO3_ROOT 225 +#define IMX8MM_CLK_GPIO4_ROOT 226 +#define IMX8MM_CLK_GPIO5_ROOT 227 + +#define IMX8MM_CLK_SNVS_ROOT 228 +#define IMX8MM_CLK_GIC 229 + +#define IMX8MM_CLK_END 230 + +#endif From 65a6c50095c4d9ab5c11d8c2d901457a98012044 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:04 +0000 Subject: [PATCH 134/190] imx: add i.MX8MM cpu type Add i.MX8MM cpu type and related helper functions Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 6 ++++++ arch/arm/include/asm/mach-imx/sys_proto.h | 8 ++++++++ arch/arm/mach-imx/cpu.c | 12 ++++++++++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 073efcd1b42..3a85492f5bf 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -26,6 +26,12 @@ #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 #define MXC_CPU_IMX8MQ 0x82 +#define MXC_CPU_IMX8MM 0x85 /* dummy ID */ +#define MXC_CPU_IMX8MML 0x86 /* dummy ID */ +#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ +#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */ +#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ +#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 449366fa8d4..aa66fdc88f1 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -45,6 +45,14 @@ #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) +#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ + is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ + is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) +#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) +#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) +#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) +#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) +#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #ifdef CONFIG_MX6 diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 73ce7f8d7d5..efd8fc614a6 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -145,6 +145,18 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_IMX8MM: + return "8MMQ"; /* Quad-core version of the imx8mm */ + case MXC_CPU_IMX8MML: + return "8MMQL"; /* Quad-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMD: + return "8MMD"; /* Dual-core version of the imx8mm */ + case MXC_CPU_IMX8MMDL: + return "8MMDL"; /* Dual-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMS: + return "8MMS"; /* Single-core version of the imx8mm */ + case MXC_CPU_IMX8MMSL: + return "8MMSL"; /* Single-core Lite version of the imx8mm */ case MXC_CPU_IMX8MQ: return "8MQ"; /* Quad-core version of the imx8m */ case MXC_CPU_MX7S: From 6c646b3de466b222b9a43d240cec1a8b582b1baf Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:07 +0000 Subject: [PATCH 135/190] imx: spl: add spl_board_boot_device for i.MX8MM Differnet board has different controller used, it is hard to use one layout for them all. Signed-off-by: Peng Fan --- arch/arm/mach-imx/spl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index f33b9f09622..30fa6aeb25f 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -18,6 +18,11 @@ DECLARE_GLOBAL_DATA_PTR; +__weak int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return 0; +} + #if defined(CONFIG_MX6) /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */ u32 spl_boot_device(void) @@ -132,6 +137,9 @@ u32 spl_boot_device(void) enum boot_device boot_device_spl = get_boot_device(); + if (IS_ENABLED(CONFIG_IMX8MM)) + return spl_board_boot_device(boot_device_spl); + switch (boot_device_spl) { #if defined(CONFIG_MX7) case SD1_BOOT: From 4800df0cb04c35d38a259bf8ef35a844f130531d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:10 +0000 Subject: [PATCH 136/190] imx8m: imx-regs: drop unused register definitions Drop unused register definitions and structures for i.MX8MQ Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 222 +-------------------- 1 file changed, 1 insertion(+), 221 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 68666a535b9..4ce6c1b0775 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -13,112 +13,41 @@ #define ROM_VERSION_A0 0x800 #define ROM_VERSION_B0 0x83C -#define M4_BOOTROM_BASE_ADDR 0x007E0000 +#define M4_BOOTROM_BASE_ADDR 0x007E0000 -#define SAI1_BASE_ADDR 0x30010000 -#define SAI6_BASE_ADDR 0x30030000 -#define SAI5_BASE_ADDR 0x30040000 -#define SAI4_BASE_ADDR 0x30050000 -#define SPBA2_BASE_ADDR 0x300F0000 -#define AIPS1_BASE_ADDR 0x301F0000 #define GPIO1_BASE_ADDR 0X30200000 #define GPIO2_BASE_ADDR 0x30210000 #define GPIO3_BASE_ADDR 0x30220000 #define GPIO4_BASE_ADDR 0x30230000 #define GPIO5_BASE_ADDR 0x30240000 -#define ANA_TSENSOR_BASE_ADDR 0x30260000 -#define ANA_OSC_BASE_ADDR 0x30270000 #define WDOG1_BASE_ADDR 0x30280000 #define WDOG2_BASE_ADDR 0x30290000 #define WDOG3_BASE_ADDR 0x302A0000 -#define SDMA2_BASE_ADDR 0x302C0000 -#define GPT1_BASE_ADDR 0x302D0000 -#define GPT2_BASE_ADDR 0x302E0000 -#define GPT3_BASE_ADDR 0x302F0000 -#define ROMCP_BASE_ADDR 0x30310000 #define LCDIF_BASE_ADDR 0x30320000 #define IOMUXC_BASE_ADDR 0x30330000 #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 #define ANATOP_BASE_ADDR 0x30360000 -#define SNVS_HP_BASE_ADDR 0x30370000 #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 -#define SEMAPHORE1_BASE_ADDR 0x303B0000 -#define SEMAPHORE2_BASE_ADDR 0x303C0000 -#define RDC_BASE_ADDR 0x303D0000 -#define CSU_BASE_ADDR 0x303E0000 -#define AIPS2_BASE_ADDR 0x305F0000 -#define PWM1_BASE_ADDR 0x30660000 -#define PWM2_BASE_ADDR 0x30670000 -#define PWM3_BASE_ADDR 0x30680000 -#define PWM4_BASE_ADDR 0x30690000 #define SYSCNT_RD_BASE_ADDR 0x306A0000 #define SYSCNT_CMP_BASE_ADDR 0x306B0000 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000 -#define GPT6_BASE_ADDR 0x306E0000 -#define GPT5_BASE_ADDR 0x306F0000 -#define GPT4_BASE_ADDR 0x30700000 -#define PERFMON1_BASE_ADDR 0x307C0000 -#define PERFMON2_BASE_ADDR 0x307D0000 -#define QOSC_BASE_ADDR 0x307F0000 -#define SPDIF1_BASE_ADDR 0x30810000 -#define ECSPI1_BASE_ADDR 0x30820000 -#define ECSPI2_BASE_ADDR 0x30830000 -#define ECSPI3_BASE_ADDR 0x30840000 #define UART1_BASE_ADDR 0x30860000 #define UART3_BASE_ADDR 0x30880000 #define UART2_BASE_ADDR 0x30890000 -#define SPDIF2_BASE_ADDR 0x308A0000 -#define SAI2_BASE_ADDR 0x308B0000 -#define SAI3_BASE_ADDR 0x308C0000 -#define SPBA1_BASE_ADDR 0x308F0000 -#define CAAM_BASE_ADDR 0x30900000 -#define AIPS3_BASE_ADDR 0x309F0000 -#define MIPI_PHY_BASE_ADDR 0x30A00000 -#define MIPI_DSI_BASE_ADDR 0x30A10000 #define I2C1_BASE_ADDR 0x30A20000 #define I2C2_BASE_ADDR 0x30A30000 #define I2C3_BASE_ADDR 0x30A40000 #define I2C4_BASE_ADDR 0x30A50000 #define UART4_BASE_ADDR 0x30A60000 -#define MIPI_CSI_BASE_ADDR 0x30A70000 -#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 -#define CSI1_BASE_ADDR 0x30A90000 -#define MU_A_BASE_ADDR 0x30AA0000 -#define MU_B_BASE_ADDR 0x30AB0000 -#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000 #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 -#define MIPI_CS2_BASE_ADDR 0x30B60000 -#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 -#define CSI2_BASE_ADDR 0x30B80000 -#define QSPI0_BASE_ADDR 0x30BB0000 -#define QSPI0_AMBA_BASE 0x08000000 -#define SDMA1_BASE_ADDR 0x30BD0000 -#define ENET1_BASE_ADDR 0x30BE0000 -#define HDMI_CTRL_BASE_ADDR 0x32C00000 -#define AIPS4_BASE_ADDR 0x32DF0000 -#define DC1_BASE_ADDR 0x32E00000 -#define DC2_BASE_ADDR 0x32E10000 -#define DC3_BASE_ADDR 0x32E20000 -#define HDMI_SEC_BASE_ADDR 0x32E40000 #define TZASC_BASE_ADDR 0x32F80000 -#define MTR_BASE_ADDR 0x32FB0000 -#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000 - -#define MXS_APBH_BASE 0x33000000 -#define MXS_GPMI_BASE 0x33002000 -#define MXS_BCH_BASE 0x33004000 - -#define USB1_BASE_ADDR 0x38100000 -#define USB2_BASE_ADDR 0x38200000 -#define USB1_PHY_BASE_ADDR 0x381F0000 -#define USB2_PHY_BASE_ADDR 0x382F0000 #define MXS_LCDIF_BASE LCDIF_BASE_ADDR @@ -288,155 +217,6 @@ struct src { u32 ddr2_rcr; }; -struct gpc_reg { - u32 lpcr_bsc; - u32 lpcr_ad; - u32 lpcr_cpu1; - u32 lpcr_cpu2; - u32 lpcr_cpu3; - u32 slpcr; - u32 mst_cpu_mapping; - u32 mmdc_cpu_mapping; - u32 mlpcr; - u32 pgc_ack_sel; - u32 pgc_ack_sel_m4; - u32 gpc_misc; - u32 imr1_core0; - u32 imr2_core0; - u32 imr3_core0; - u32 imr4_core0; - u32 imr1_core1; - u32 imr2_core1; - u32 imr3_core1; - u32 imr4_core1; - u32 imr1_cpu1; - u32 imr2_cpu1; - u32 imr3_cpu1; - u32 imr4_cpu1; - u32 imr1_cpu3; - u32 imr2_cpu3; - u32 imr3_cpu3; - u32 imr4_cpu3; - u32 isr1_cpu0; - u32 isr2_cpu0; - u32 isr3_cpu0; - u32 isr4_cpu0; - u32 isr1_cpu1; - u32 isr2_cpu1; - u32 isr3_cpu1; - u32 isr4_cpu1; - u32 isr1_cpu2; - u32 isr2_cpu2; - u32 isr3_cpu2; - u32 isr4_cpu2; - u32 isr1_cpu3; - u32 isr2_cpu3; - u32 isr3_cpu3; - u32 isr4_cpu3; - u32 slt0_cfg; - u32 slt1_cfg; - u32 slt2_cfg; - u32 slt3_cfg; - u32 slt4_cfg; - u32 slt5_cfg; - u32 slt6_cfg; - u32 slt7_cfg; - u32 slt8_cfg; - u32 slt9_cfg; - u32 slt10_cfg; - u32 slt11_cfg; - u32 slt12_cfg; - u32 slt13_cfg; - u32 slt14_cfg; - u32 pgc_cpu_0_1_mapping; - u32 cpu_pgc_up_trg; - u32 mix_pgc_up_trg; - u32 pu_pgc_up_trg; - u32 cpu_pgc_dn_trg; - u32 mix_pgc_dn_trg; - u32 pu_pgc_dn_trg; - u32 lpcr_bsc2; - u32 pgc_cpu_2_3_mapping; - u32 lps_cpu0; - u32 lps_cpu1; - u32 lps_cpu2; - u32 lps_cpu3; - u32 gpc_gpr; - u32 gtor; - u32 debug_addr1; - u32 debug_addr2; - u32 cpu_pgc_up_status1; - u32 mix_pgc_up_status0; - u32 mix_pgc_up_status1; - u32 mix_pgc_up_status2; - u32 m4_mix_pgc_up_status0; - u32 m4_mix_pgc_up_status1; - u32 m4_mix_pgc_up_status2; - u32 pu_pgc_up_status0; - u32 pu_pgc_up_status1; - u32 pu_pgc_up_status2; - u32 m4_pu_pgc_up_status0; - u32 m4_pu_pgc_up_status1; - u32 m4_pu_pgc_up_status2; - u32 a53_lp_io_0; - u32 a53_lp_io_1; - u32 a53_lp_io_2; - u32 cpu_pgc_dn_status1; - u32 mix_pgc_dn_status0; - u32 mix_pgc_dn_status1; - u32 mix_pgc_dn_status2; - u32 m4_mix_pgc_dn_status0; - u32 m4_mix_pgc_dn_status1; - u32 m4_mix_pgc_dn_status2; - u32 pu_pgc_dn_status0; - u32 pu_pgc_dn_status1; - u32 pu_pgc_dn_status2; - u32 m4_pu_pgc_dn_status0; - u32 m4_pu_pgc_dn_status1; - u32 m4_pu_pgc_dn_status2; - u32 res[3]; - u32 mix_pdn_flg; - u32 pu_pdn_flg; - u32 m4_mix_pdn_flg; - u32 m4_pu_pdn_flg; - u32 imr1_core2; - u32 imr2_core2; - u32 imr3_core2; - u32 imr4_core2; - u32 imr1_core3; - u32 imr2_core3; - u32 imr3_core3; - u32 imr4_core3; - u32 pgc_ack_sel_pu; - u32 pgc_ack_sel_m4_pu; - u32 slt15_cfg; - u32 slt16_cfg; - u32 slt17_cfg; - u32 slt18_cfg; - u32 slt19_cfg; - u32 gpc_pu_pwrhsk; - u32 slt0_cfg_pu; - u32 slt1_cfg_pu; - u32 slt2_cfg_pu; - u32 slt3_cfg_pu; - u32 slt4_cfg_pu; - u32 slt5_cfg_pu; - u32 slt6_cfg_pu; - u32 slt7_cfg_pu; - u32 slt8_cfg_pu; - u32 slt9_cfg_pu; - u32 slt10_cfg_pu; - u32 slt11_cfg_pu; - u32 slt12_cfg_pu; - u32 slt13_cfg_pu; - u32 slt14_cfg_pu; - u32 slt15_cfg_pu; - u32 slt16_cfg_pu; - u32 slt17_cfg_pu; - u32 slt18_cfg_pu; - u32 slt19_cfg_pu; -}; - #define WDOG_WDT_MASK BIT(3) #define WDOG_WDZST_MASK BIT(0) struct wdog_regs { From 20ebb4fa758f56bf9c29d83922287c2796ceaf21 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:14 +0000 Subject: [PATCH 137/190] imx8m: update imx-regs for i.MX8MM i.MX8MM has similar architecture with i.MX8MQ, but it has totally different PLL design and register layout change. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 69 ++++++++++++++++++++-- 1 file changed, 64 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 4ce6c1b0775..62640d996e4 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -10,8 +10,8 @@ #include -#define ROM_VERSION_A0 0x800 -#define ROM_VERSION_B0 0x83C +#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 +#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 #define M4_BOOTROM_BASE_ADDR 0x007E0000 @@ -23,7 +23,6 @@ #define WDOG1_BASE_ADDR 0x30280000 #define WDOG2_BASE_ADDR 0x30290000 #define WDOG3_BASE_ADDR 0x302A0000 -#define LCDIF_BASE_ADDR 0x30320000 #define IOMUXC_BASE_ADDR 0x30330000 #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 @@ -46,10 +45,14 @@ #define UART4_BASE_ADDR 0x30A60000 #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 +#ifdef CONFIG_IMX8MM +#define USDHC3_BASE_ADDR 0x30B60000 +#endif #define TZASC_BASE_ADDR 0x32F80000 -#define MXS_LCDIF_BASE LCDIF_BASE_ADDR +#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ + 0x30320000 : 0x32e00000 #define SRC_IPS_BASE_ADDR 0x30390000 #define SRC_DDRC_RCR_ADDR 0x30391000 @@ -134,6 +137,7 @@ struct fuse_bank1_regs { u32 rsvd3[3]; }; +#ifdef CONFIG_IMX8MQ struct anamix_pll { u32 audio_pll1_cfg0; u32 audio_pll1_cfg1; @@ -168,6 +172,60 @@ struct anamix_pll { u32 frac_pllout_div_cfg; u32 sscg_pllout_div_cfg; }; +#else +struct anamix_pll { + u32 audio_pll1_gnrl_ctl; + u32 audio_pll1_fdiv_ctl0; + u32 audio_pll1_fdiv_ctl1; + u32 audio_pll1_sscg_ctl; + u32 audio_pll1_mnit_ctl; + u32 audio_pll2_gnrl_ctl; + u32 audio_pll2_fdiv_ctl0; + u32 audio_pll2_fdiv_ctl1; + u32 audio_pll2_sscg_ctl; + u32 audio_pll2_mnit_ctl; + u32 video_pll1_gnrl_ctl; + u32 video_pll1_fdiv_ctl0; + u32 video_pll1_fdiv_ctl1; + u32 video_pll1_sscg_ctl; + u32 video_pll1_mnit_ctl; + u32 reserved[5]; + u32 dram_pll_gnrl_ctl; + u32 dram_pll_fdiv_ctl0; + u32 dram_pll_fdiv_ctl1; + u32 dram_pll_sscg_ctl; + u32 dram_pll_mnit_ctl; + u32 gpu_pll_gnrl_ctl; + u32 gpu_pll_div_ctl; + u32 gpu_pll_locked_ctl1; + u32 gpu_pll_mnit_ctl; + u32 vpu_pll_gnrl_ctl; + u32 vpu_pll_div_ctl; + u32 vpu_pll_locked_ctl1; + u32 vpu_pll_mnit_ctl; + u32 arm_pll_gnrl_ctl; + u32 arm_pll_div_ctl; + u32 arm_pll_locked_ctl1; + u32 arm_pll_mnit_ctl; + u32 sys_pll1_gnrl_ctl; + u32 sys_pll1_div_ctl; + u32 sys_pll1_locked_ctl1; + u32 reserved2[24]; + u32 sys_pll1_mnit_ctl; + u32 sys_pll2_gnrl_ctl; + u32 sys_pll2_div_ctl; + u32 sys_pll2_locked_ctl1; + u32 sys_pll2_mnit_ctl; + u32 sys_pll3_gnrl_ctl; + u32 sys_pll3_div_ctl; + u32 sys_pll3_locked_ctl1; + u32 sys_pll3_mnit_ctl; + u32 anamix_misc_ctl; + u32 anamix_clk_mnit_ctl; + u32 reserved3[437]; + u32 digprog; +}; +#endif struct fuse_bank9_regs { u32 mac_addr0; @@ -239,7 +297,8 @@ struct bootrom_sw_info { u32 reserved_3[3]; }; -#define ROM_SW_INFO_ADDR_B0 0x00000968 +#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\ + 0x000009e8) #define ROM_SW_INFO_ADDR_A0 0x000009e8 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ From 78db9a54636d3c43df0d5a9629c6293b2877c0a5 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:17 +0000 Subject: [PATCH 138/190] imx: add get_cpu_rev support for i.MX8MM There are several variants based on i.MX8MM, add the support in get_cpu_rev Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 57 +++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 7ec39b3e474..5115471eff8 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -130,25 +130,62 @@ static struct mm_region imx8m_mem_map[] = { struct mm_region *mem_map = imx8m_mem_map; +static u32 get_cpu_variant_type(u32 type) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->tester4); + + if (type == MXC_CPU_IMX8MM) { + switch (value & 0x3) { + case 2: + if (value & 0x1c0000) + return MXC_CPU_IMX8MMDL; + else + return MXC_CPU_IMX8MMD; + case 3: + if (value & 0x1c0000) + return MXC_CPU_IMX8MMSL; + else + return MXC_CPU_IMX8MMS; + default: + if (value & 0x1c0000) + return MXC_CPU_IMX8MML; + break; + } + } + + return type; +} + u32 get_cpu_rev(void) { struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; u32 reg = readl(&ana_pll->digprog); u32 type = (reg >> 16) & 0xff; + u32 major_low = (reg >> 8) & 0xff; u32 rom_version; reg &= 0xff; - if (reg == CHIP_REV_1_0) { - /* - * For B0 chip, the DIGPROG is not updated, still TO1.0. - * we have to check ROM version further - */ - rom_version = readl((void __iomem *)ROM_VERSION_A0); - if (rom_version != CHIP_REV_1_0) { - rom_version = readl((void __iomem *)ROM_VERSION_B0); - if (rom_version >= CHIP_REV_2_0) - reg = CHIP_REV_2_0; + /* i.MX8MM */ + if (major_low == 0x41) { + type = get_cpu_variant_type(MXC_CPU_IMX8MM); + } else { + if (reg == CHIP_REV_1_0) { + /* + * For B0 chip, the DIGPROG is not updated, still TO1.0. + * we have to check ROM version further + */ + rom_version = readl((void __iomem *)ROM_VERSION_A0); + if (rom_version != CHIP_REV_1_0) { + rom_version = readl((void __iomem *)ROM_VERSION_B0); + if (rom_version >= CHIP_REV_2_0) + reg = CHIP_REV_2_0; + } } } From e246b7ad74c80b79c17eeb8fc7e9079b5b25a97f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:20 +0000 Subject: [PATCH 139/190] imx8m: add pin header for i.MX8MM Add pin header file for i.MX8MM To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be selected. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 ++++++++++++++++++ 1 file changed, 691 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h new file mode 100644 index 00000000000..210e96e1dbe --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h @@ -0,0 +1,691 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8MM_PINS_H__ +#define __ASM_ARCH_IMX8MM_PINS_H__ + +#include + +enum { + IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0), + IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0), + IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0), + IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0), + IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), + IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), + IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), + IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), + IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0), + IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0), + IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0), + IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0), + IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0), + IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), + IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), + IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), + IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), + IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), + IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), + IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), + IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), + IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), + IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), + IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), + IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), + IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; +#endif From 1c7cba9fa70c7ce5113afdf78f132d49c99e9ed2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:23 +0000 Subject: [PATCH 140/190] imx: add i.MX8MM PE property i.MX8MM does not have LVTTL, it has a PE property Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/iomux-v3.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index b899a4ff6f0..720e8f70433 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -104,7 +104,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_ODE (0x1 << 5) #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) +#ifdef CONFIG_IMX8MM +#define PAD_CTL_PE (0x1 << 8) +#else #define PAD_CTL_LVTTL (0x1 << 8) +#endif #elif defined CONFIG_MX7 From 59efa6b52bb25f66bb0b0f6f633e6c403a37be3d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:27 +0000 Subject: [PATCH 141/190] imx8m: Fix MMU table issue for OPTEE memory When running with OPTEE, the MMU table in u-boot does not remove the OPTEE memory from its settings. So ARM speculative prefetch in u-boot may access that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory is set to secure access, then the speculative prefetch will fail and cause various memory issue in u-boot. The fail address register and int_status register in trustzone has logged that speculative access from u-boot. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5115471eff8..dd393b581be 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -112,16 +112,18 @@ static struct mm_region imx8m_mem_map[] = { /* DRAM1 */ .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0xC0000000UL, + .size = PHYS_SDRAM_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE +#ifdef PHYS_SDRAM_2_SIZE }, { /* DRAM2 */ .virt = 0x100000000UL, .phys = 0x100000000UL, - .size = 0x040000000UL, + .size = PHYS_SDRAM_2_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE +#endif }, { /* List terminator */ 0, @@ -130,6 +132,20 @@ static struct mm_region imx8m_mem_map[] = { struct mm_region *mem_map = imx8m_mem_map; +void enable_caches(void) +{ + /* + * If OPTEE runs, remove OPTEE memory from MMU table to + * avoid speculative prefetch. OPTEE runs at the top of + * the first memory bank + */ + if (rom_pointer[1]) + imx8m_mem_map[5].size -= rom_pointer[1]; + + icache_enable(); + dcache_enable(); +} + static u32 get_cpu_variant_type(u32 type) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; From dbb2b7e50899ea6651bdc4c931427e6152493ba2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:30 +0000 Subject: [PATCH 142/190] imx8m: set BYPASS ID SWAP to avoid AXI bus errors set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index dd393b581be..261f586fc02 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -55,6 +55,8 @@ void enable_tzc380(void) /* Enable TZASC and lock setting */ setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); + if (IS_ENABLED(CONFIG_IMX8MM)) + setbits_le32(&gpr->gpr[10], BIT(1)); } void set_wdog_reset(struct wdog_regs *wdog) From b3cf0a8f03d162e030cde1131751d060853e16fc Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 27 Aug 2019 06:25:34 +0000 Subject: [PATCH 143/190] imx8m: Configure trustzone region 0 for non-secure access Set trustzone region 0 to allow both non-secure and secure access when trust zone is enabled. We found USB controller fails to access DDR if the default region 0 is secure access only. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 261f586fc02..a33ca356532 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -57,6 +57,12 @@ void enable_tzc380(void) setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); if (IS_ENABLED(CONFIG_IMX8MM)) setbits_le32(&gpr->gpr[10], BIT(1)); + /* + * set Region 0 attribute to allow secure and non-secure + * read/write permission. Found some masters like usb dwc3 + * controllers can't work with secure memory. + */ + writel(0xf0000000, TZASC_BASE_ADDR + 0x108); } void set_wdog_reset(struct wdog_regs *wdog) From 0528ba0e1c4f879278d597b1aeaf1bf31a943f75 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:37 +0000 Subject: [PATCH 144/190] imx8m: soc: enable SCTR clock before timer init To i.MX8MM SCTR clock is disabled by ROM, so before timer init need to enable it. To i.MX8MQ, it does not hurt the clock is enabled again. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index a33ca356532..ac80266010d 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -231,6 +231,12 @@ static void imx_set_wdog_powerdown(bool enable) int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + /* + * ROM might disable clock for SCTR, + * enable the clock before timer_init. + */ + if (IS_ENABLED(CONFIG_SPL_BUILD)) + clock_enable(CCGR_SCTR, 1); /* * Init timer at very early state, because sscg pll setting * will use it From d2041725e84b6796d12a0ea587e6ed84dee8a59f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:41 +0000 Subject: [PATCH 145/190] imx8m: restrict reset_cpu Make reset_cpu only visible when CONFIG_SYSRESET not defined or CONFIG_SPL_BUILD. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index ac80266010d..3a54db48980 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -301,16 +301,21 @@ int ft_system_setup(void *blob, bd_t *bd) } #endif +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET) void reset_cpu(ulong addr) { - struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + struct watchdog_regs *wdog = (struct watchdog_regs *)addr; - /* Clear WDA to trigger WDOG_B immediately */ - writew((WCR_WDE | WCR_SRS), &wdog->wcr); + if (!addr) + wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - while (1) { - /* - * spin for .5 seconds before reset - */ - } + /* Clear WDA to trigger WDOG_B immediately */ + writew((WCR_WDE | WCR_SRS), &wdog->wcr); + + while (1) { + /* + * spin for .5 seconds before reset + */ + } } +#endif From 2005916f54cfef5413010a16c243d3c01189fe68 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:44 +0000 Subject: [PATCH 146/190] imx8m: rename clock to clock_imx8mq i.MX8MQ and i.MX8MM has totally different pll design, so rename clock to clock_imx8mq. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/Makefile | 3 ++- arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 0 2 files changed, 2 insertions(+), 1 deletion(-) rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (100%) diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile index feff4941c1a..42a1544c6b7 100644 --- a/arch/arm/mach-imx/imx8m/Makefile +++ b/arch/arm/mach-imx/imx8m/Makefile @@ -3,4 +3,5 @@ # Copyright 2017 NXP obj-y += lowlevel_init.o -obj-y += clock.o clock_slice.o soc.o +obj-y += clock_slice.o soc.o +obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o diff --git a/arch/arm/mach-imx/imx8m/clock.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c similarity index 100% rename from arch/arm/mach-imx/imx8m/clock.c rename to arch/arm/mach-imx/imx8m/clock_imx8mq.c From 8838cdf10d28ad4e651785c8de9446585dd39363 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:48 +0000 Subject: [PATCH 147/190] imx8m: restructure clock.h i.MX8MQ and i.MX8MM use different analog pll design, but they share same ccm design. Add clock_imx8mq.h for i.MX8MQ keep common part in clock.h Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/clock.h | 489 ++---------------- .../arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +++++++++++++++ arch/arm/mach-imx/imx8m/clock_imx8mq.c | 5 +- 3 files changed, 467 insertions(+), 451 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index e7c1670f6b9..80245a2f2d4 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -2,27 +2,30 @@ /* * Copyright 2017 NXP * - * Peng Fan + * Peng Fan */ -#ifndef _ASM_ARCH_IMX8M_CLOCK_H -#define _ASM_ARCH_IMX8M_CLOCK_H - #include +#ifdef CONFIG_IMX8MQ +#include +#else +#error "Error no clock.h" +#endif + #define MHZ(X) ((X) * 1000000UL) -enum pll_clocks { - ANATOP_ARM_PLL, - ANATOP_GPU_PLL, - ANATOP_SYSTEM_PLL1, - ANATOP_SYSTEM_PLL2, - ANATOP_SYSTEM_PLL3, - ANATOP_AUDIO_PLL1, - ANATOP_AUDIO_PLL2, - ANATOP_VIDEO_PLL1, - ANATOP_VIDEO_PLL2, - ANATOP_DRAM_PLL, +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_IPG_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, + MXC_UART_CLK, + MXC_QSPI_CLK, }; enum clk_slice_type { @@ -35,297 +38,6 @@ enum clk_slice_type { DRAM_SEL_CLOCK_SLICE, }; -enum clk_root_index { - MXC_ARM_CLK = 0, - ARM_A53_CLK_ROOT = 0, - ARM_M4_CLK_ROOT = 1, - VPU_A53_CLK_ROOT = 2, - GPU_CORE_CLK_ROOT = 3, - GPU_SHADER_CLK_ROOT = 4, - MAIN_AXI_CLK_ROOT = 16, - ENET_AXI_CLK_ROOT = 17, - NAND_USDHC_BUS_CLK_ROOT = 18, - VPU_BUS_CLK_ROOT = 19, - DISPLAY_AXI_CLK_ROOT = 20, - DISPLAY_APB_CLK_ROOT = 21, - DISPLAY_RTRM_CLK_ROOT = 22, - USB_BUS_CLK_ROOT = 23, - GPU_AXI_CLK_ROOT = 24, - GPU_AHB_CLK_ROOT = 25, - NOC_CLK_ROOT = 26, - NOC_APB_CLK_ROOT = 27, - AHB_CLK_ROOT = 32, - IPG_CLK_ROOT = 33, - MXC_IPG_CLK = 33, - AUDIO_AHB_CLK_ROOT = 34, - MIPI_DSI_ESC_RX_CLK_ROOT = 36, - DRAM_SEL_CFG = 48, - CORE_SEL_CFG = 49, - DRAM_ALT_CLK_ROOT = 64, - DRAM_APB_CLK_ROOT = 65, - VPU_G1_CLK_ROOT = 66, - VPU_G2_CLK_ROOT = 67, - DISPLAY_DTRC_CLK_ROOT = 68, - DISPLAY_DC8000_CLK_ROOT = 69, - PCIE1_CTRL_CLK_ROOT = 70, - PCIE1_PHY_CLK_ROOT = 71, - PCIE1_AUX_CLK_ROOT = 72, - DC_PIXEL_CLK_ROOT = 73, - LCDIF_PIXEL_CLK_ROOT = 74, - SAI1_CLK_ROOT = 75, - SAI2_CLK_ROOT = 76, - SAI3_CLK_ROOT = 77, - SAI4_CLK_ROOT = 78, - SAI5_CLK_ROOT = 79, - SAI6_CLK_ROOT = 80, - SPDIF1_CLK_ROOT = 81, - SPDIF2_CLK_ROOT = 82, - ENET_REF_CLK_ROOT = 83, - ENET_TIMER_CLK_ROOT = 84, - ENET_PHY_REF_CLK_ROOT = 85, - NAND_CLK_ROOT = 86, - QSPI_CLK_ROOT = 87, - MXC_ESDHC_CLK = 88, - USDHC1_CLK_ROOT = 88, - MXC_ESDHC2_CLK = 89, - USDHC2_CLK_ROOT = 89, - I2C1_CLK_ROOT = 90, - MXC_I2C_CLK = 90, - I2C2_CLK_ROOT = 91, - I2C3_CLK_ROOT = 92, - I2C4_CLK_ROOT = 93, - UART1_CLK_ROOT = 94, - UART2_CLK_ROOT = 95, - UART3_CLK_ROOT = 96, - UART4_CLK_ROOT = 97, - USB_CORE_REF_CLK_ROOT = 98, - USB_PHY_REF_CLK_ROOT = 99, - GIC_CLK_ROOT = 100, - ECSPI1_CLK_ROOT = 101, - ECSPI2_CLK_ROOT = 102, - PWM1_CLK_ROOT = 103, - PWM2_CLK_ROOT = 104, - PWM3_CLK_ROOT = 105, - PWM4_CLK_ROOT = 106, - GPT1_CLK_ROOT = 107, - GPT2_CLK_ROOT = 108, - GPT3_CLK_ROOT = 109, - GPT4_CLK_ROOT = 110, - GPT5_CLK_ROOT = 111, - GPT6_CLK_ROOT = 112, - TRACE_CLK_ROOT = 113, - WDOG_CLK_ROOT = 114, - WRCLK_CLK_ROOT = 115, - IPP_DO_CLKO1 = 116, - IPP_DO_CLKO2 = 117, - MIPI_DSI_CORE_CLK_ROOT = 118, - MIPI_DSI_PHY_REF_CLK_ROOT = 119, - MIPI_DSI_DBI_CLK_ROOT = 120, - OLD_MIPI_DSI_ESC_CLK_ROOT = 121, - MIPI_CSI1_CORE_CLK_ROOT = 122, - MIPI_CSI1_PHY_REF_CLK_ROOT = 123, - MIPI_CSI1_ESC_CLK_ROOT = 124, - MIPI_CSI2_CORE_CLK_ROOT = 125, - MIPI_CSI2_PHY_REF_CLK_ROOT = 126, - MIPI_CSI2_ESC_CLK_ROOT = 127, - PCIE2_CTRL_CLK_ROOT = 128, - PCIE2_PHY_CLK_ROOT = 129, - PCIE2_AUX_CLK_ROOT = 130, - ECSPI3_CLK_ROOT = 131, - OLD_MIPI_DSI_ESC_RX_ROOT = 132, - DISPLAY_HDMI_CLK_ROOT = 133, - CLK_ROOT_MAX, -}; - -enum clk_root_src { - OSC_25M_CLK, - ARM_PLL_CLK, - DRAM_PLL1_CLK, - VIDEO_PLL2_CLK, - VPU_PLL_CLK, - GPU_PLL_CLK, - SYSTEM_PLL1_800M_CLK, - SYSTEM_PLL1_400M_CLK, - SYSTEM_PLL1_266M_CLK, - SYSTEM_PLL1_200M_CLK, - SYSTEM_PLL1_160M_CLK, - SYSTEM_PLL1_133M_CLK, - SYSTEM_PLL1_100M_CLK, - SYSTEM_PLL1_80M_CLK, - SYSTEM_PLL1_40M_CLK, - SYSTEM_PLL2_1000M_CLK, - SYSTEM_PLL2_500M_CLK, - SYSTEM_PLL2_333M_CLK, - SYSTEM_PLL2_250M_CLK, - SYSTEM_PLL2_200M_CLK, - SYSTEM_PLL2_166M_CLK, - SYSTEM_PLL2_125M_CLK, - SYSTEM_PLL2_100M_CLK, - SYSTEM_PLL2_50M_CLK, - SYSTEM_PLL3_CLK, - AUDIO_PLL1_CLK, - AUDIO_PLL2_CLK, - VIDEO_PLL_CLK, - OSC_32K_CLK, - EXT_CLK_1, - EXT_CLK_2, - EXT_CLK_3, - EXT_CLK_4, - OSC_27M_CLK, -}; - -/* CCGR index */ -enum clk_ccgr_index { - CCGR_DVFS = 0, - CCGR_ANAMIX = 1, - CCGR_CPU = 2, - CCGR_CSU = 4, - CCGR_DRAM1 = 5, - CCGR_DRAM2_OBSOLETE = 6, - CCGR_ECSPI1 = 7, - CCGR_ECSPI2 = 8, - CCGR_ECSPI3 = 9, - CCGR_ENET1 = 10, - CCGR_GPIO1 = 11, - CCGR_GPIO2 = 12, - CCGR_GPIO3 = 13, - CCGR_GPIO4 = 14, - CCGR_GPIO5 = 15, - CCGR_GPT1 = 16, - CCGR_GPT2 = 17, - CCGR_GPT3 = 18, - CCGR_GPT4 = 19, - CCGR_GPT5 = 20, - CCGR_GPT6 = 21, - CCGR_HS = 22, - CCGR_I2C1 = 23, - CCGR_I2C2 = 24, - CCGR_I2C3 = 25, - CCGR_I2C4 = 26, - CCGR_IOMUX = 27, - CCGR_IOMUX1 = 28, - CCGR_IOMUX2 = 29, - CCGR_IOMUX3 = 30, - CCGR_IOMUX4 = 31, - CCGR_M4 = 32, - CCGR_MU = 33, - CCGR_OCOTP = 34, - CCGR_OCRAM = 35, - CCGR_OCRAM_S = 36, - CCGR_PCIE = 37, - CCGR_PERFMON1 = 38, - CCGR_PERFMON2 = 39, - CCGR_PWM1 = 40, - CCGR_PWM2 = 41, - CCGR_PWM3 = 42, - CCGR_PWM4 = 43, - CCGR_QOS = 44, - CCGR_DISMIX = 45, - CCGR_MEGAMIX = 46, - CCGR_QSPI = 47, - CCGR_RAWNAND = 48, - CCGR_RDC = 49, - CCGR_ROM = 50, - CCGR_SAI1 = 51, - CCGR_SAI2 = 52, - CCGR_SAI3 = 53, - CCGR_SAI4 = 54, - CCGR_SAI5 = 55, - CCGR_SAI6 = 56, - CCGR_SCTR = 57, - CCGR_SDMA1 = 58, - CCGR_SDMA2 = 59, - CCGR_SEC_DEBUG = 60, - CCGR_SEMA1 = 61, - CCGR_SEMA2 = 62, - CCGR_SIM_DISPLAY = 63, - CCGR_SIM_ENET = 64, - CCGR_SIM_M = 65, - CCGR_SIM_MAIN = 66, - CCGR_SIM_S = 67, - CCGR_SIM_WAKEUP = 68, - CCGR_SIM_USB = 69, - CCGR_SIM_VPU = 70, - CCGR_SNVS = 71, - CCGR_TRACE = 72, - CCGR_UART1 = 73, - CCGR_UART2 = 74, - CCGR_UART3 = 75, - CCGR_UART4 = 76, - CCGR_USB_CTRL1 = 77, - CCGR_USB_CTRL2 = 78, - CCGR_USB_PHY1 = 79, - CCGR_USB_PHY2 = 80, - CCGR_USDHC1 = 81, - CCGR_USDHC2 = 82, - CCGR_WDOG1 = 83, - CCGR_WDOG2 = 84, - CCGR_WDOG3 = 85, - CCGR_VA53 = 86, - CCGR_GPU = 87, - CCGR_HEVC = 88, - CCGR_AVC = 89, - CCGR_VP9 = 90, - CCGR_HEVC_INTER = 91, - CCGR_GIC = 92, - CCGR_DISPLAY = 93, - CCGR_HDMI = 94, - CCGR_HDMI_PHY = 95, - CCGR_XTAL = 96, - CCGR_PLL = 97, - CCGR_TSENSOR = 98, - CCGR_VPU_DEC = 99, - CCGR_PCIE2 = 100, - CCGR_MIPI_CSI1 = 101, - CCGR_MIPI_CSI2 = 102, - CCGR_MAX, -}; - -/* src index */ -enum clk_src_index { - CLK_SRC_CKIL_SYNC_REQ = 0, - CLK_SRC_ARM_PLL_EN = 1, - CLK_SRC_GPU_PLL_EN = 2, - CLK_SRC_VPU_PLL_EN = 3, - CLK_SRC_DRAM_PLL_EN = 4, - CLK_SRC_SYSTEM_PLL1_EN = 5, - CLK_SRC_SYSTEM_PLL2_EN = 6, - CLK_SRC_SYSTEM_PLL3_EN = 7, - CLK_SRC_AUDIO_PLL1_EN = 8, - CLK_SRC_AUDIO_PLL2_EN = 9, - CLK_SRC_VIDEO_PLL1_EN = 10, - CLK_SRC_VIDEO_PLL2_EN = 11, - CLK_SRC_ARM_PLL = 12, - CLK_SRC_GPU_PLL = 13, - CLK_SRC_VPU_PLL = 14, - CLK_SRC_DRAM_PLL = 15, - CLK_SRC_SYSTEM_PLL1_800M = 16, - CLK_SRC_SYSTEM_PLL1_400M = 17, - CLK_SRC_SYSTEM_PLL1_266M = 18, - CLK_SRC_SYSTEM_PLL1_200M = 19, - CLK_SRC_SYSTEM_PLL1_160M = 20, - CLK_SRC_SYSTEM_PLL1_133M = 21, - CLK_SRC_SYSTEM_PLL1_100M = 22, - CLK_SRC_SYSTEM_PLL1_80M = 23, - CLK_SRC_SYSTEM_PLL1_40M = 24, - CLK_SRC_SYSTEM_PLL2_1000M = 25, - CLK_SRC_SYSTEM_PLL2_500M = 26, - CLK_SRC_SYSTEM_PLL2_333M = 27, - CLK_SRC_SYSTEM_PLL2_250M = 28, - CLK_SRC_SYSTEM_PLL2_200M = 29, - CLK_SRC_SYSTEM_PLL2_166M = 30, - CLK_SRC_SYSTEM_PLL2_125M = 31, - CLK_SRC_SYSTEM_PLL2_100M = 32, - CLK_SRC_SYSTEM_PLL2_50M = 33, - CLK_SRC_SYSTEM_PLL3 = 34, - CLK_SRC_AUDIO_PLL1 = 35, - CLK_SRC_AUDIO_PLL2 = 36, - CLK_SRC_VIDEO_PLL1 = 37, - CLK_SRC_VIDEO_PLL2 = 38, - CLK_SRC_OSC_25M = 39, - CLK_SRC_OSC_27M = 40, -}; - enum root_pre_div { CLK_ROOT_PRE_DIV1 = 0, CLK_ROOT_PRE_DIV2, @@ -466,6 +178,29 @@ struct ccm_reg { struct ccm_root ip_root[78]; }; +enum enet_freq { + ENET_25MHZ = 0, + ENET_50MHZ, + ENET_125MHZ, +}; + +#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { + ulong clk; + int alt_root_sel; + enum root_pre_div alt_pre_div; + int apb_root_sel; + enum root_pre_div apb_pre_div; +}; + #define CCGR_CLK_ON_MASK 0x03 #define CLK_SRC_ON_MASK 0x03 @@ -503,117 +238,6 @@ struct ccm_reg { #define CLK_ROOT_IPG_POST_DIV_MASK 0x3 #define CLK_ROOT_POST_DIV_SHIFT 0 #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) - -/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ -#define FRAC_PLL_LOCK_MASK BIT(31) -#define FRAC_PLL_CLKE_MASK BIT(21) -#define FRAC_PLL_PD_MASK BIT(19) -#define FRAC_PLL_REFCLK_SEL_MASK BIT(16) -#define FRAC_PLL_LOCK_SEL_MASK BIT(15) -#define FRAC_PLL_BYPASS_MASK BIT(14) -#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) -#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) -#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) -#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) -#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) -#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 -#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f -#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f) - -#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16) - -#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) -#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 -#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f -#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) - -/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ -#define SSCG_PLL_LOCK_MASK BIT(31) -#define SSCG_PLL_CLKE_MASK BIT(25) -#define SSCG_PLL_DIV2_CLKE_MASK BIT(23) -#define SSCG_PLL_DIV3_CLKE_MASK BIT(21) -#define SSCG_PLL_DIV4_CLKE_MASK BIT(19) -#define SSCG_PLL_DIV5_CLKE_MASK BIT(17) -#define SSCG_PLL_DIV6_CLKE_MASK BIT(15) -#define SSCG_PLL_DIV8_CLKE_MASK BIT(13) -#define SSCG_PLL_DIV10_CLKE_MASK BIT(11) -#define SSCG_PLL_DIV20_CLKE_MASK BIT(9) -#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) -#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) -#define SSCG_PLL_PLL3_CLKE_MASK BIT(9) -#define SSCG_PLL_PD_MASK BIT(7) -#define SSCG_PLL_BYPASS1_MASK BIT(5) -#define SSCG_PLL_BYPASS2_MASK BIT(4) -#define SSCG_PLL_LOCK_SEL_MASK BIT(3) -#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) -#define SSCG_PLL_REFCLK_SEL_MASK 0x3 -#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) - -#define SSCG_PLL_SSDS_MASK BIT(8) -#define SSCG_PLL_SSMD_MASK (0x7 << 5) -#define SSCG_PLL_SSMF_MASK (0xf << 1) -#define SSCG_PLL_SSE_MASK 0x1 - -#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) -#define SSCG_PLL_REF_DIVR1_SHIFT 25 -#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) -#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) -#define SSCG_PLL_REF_DIVR2_SHIFT 19 -#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) -#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) -#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 -#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ - SSCG_PLL_FEEDBACK_DIV_F1_MASK) -#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) -#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 -#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ - SSCG_PLL_FEEDBACK_DIV_F2_MASK) -#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) -#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 -#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ - SSCG_PLL_OUTPUT_DIV_VAL_MASK) -#define SSCG_PLL_FILTER_RANGE_MASK 0x1 - -#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) -#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) -#define HW_DIGPROG_MINOR_MASK 0xff - -#define HW_OSC_27M_CLKE_MASK BIT(4) -#define HW_OSC_25M_CLKE_MASK BIT(2) -#define HW_OSC_32K_SEL_MASK 0x1 -#define HW_OSC_32K_SEL_RTC 0x1 -#define HW_OSC_32K_SEL_25M_DIV800 0x0 - -#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) -#define HW_FRAC_ARM_PLL_DIV_SHIFT 20 -#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) -#define HW_FRAC_VPU_PLL_DIV_SHIFT 16 -#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) -#define HW_FRAC_GPU_PLL_DIV_SHIFT 12 -#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) -#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 -#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) -#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 -#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 -#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0 - -#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) -#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 -#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) -#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 -#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) -#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 -#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) -#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 -#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 -#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0 - #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 @@ -622,34 +246,6 @@ struct ccm_reg { #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 -enum enet_freq { - ENET_25MHZ = 0, - ENET_50MHZ, - ENET_125MHZ, -}; - -enum frac_pll_out_val { - FRAC_PLL_OUT_1000M, - FRAC_PLL_OUT_1600M, -}; - -#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ - { \ - .clk = (_rate), \ - .alt_root_sel = (_m), \ - .alt_pre_div = (_p), \ - .apb_root_sel = (_s), \ - .apb_pre_div = (_k), \ - } - -struct dram_bypass_clk_setting { - ulong clk; - int alt_root_sel; - enum root_pre_div alt_pre_div; - int apb_root_sel; - enum root_pre_div apb_pre_div; -}; - void dram_pll_init(ulong pll_val); void dram_enable_bypass(ulong clk_val); void dram_disable_bypass(void); @@ -659,7 +255,7 @@ int clock_init(void); void init_clk_usdhc(u32 index); void init_uart_clk(u32 index); void init_wdog_clk(void); -unsigned int mxc_get_clock(enum clk_root_index clk); +unsigned int mxc_get_clock(enum mxc_clock clk); int clock_enable(enum clk_ccgr_index index, bool enable); int clock_root_enabled(enum clk_root_index clock_id); int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, @@ -675,4 +271,3 @@ int set_clk_qspi(void); void enable_ocotp_clk(unsigned char enable); int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); int set_clk_enet(enum enet_freq type); -#endif diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h new file mode 100644 index 00000000000..9fa9eb26877 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -0,0 +1,424 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + * + * Peng Fan + */ + +#ifndef _ASM_ARCH_IMX8M_CLOCK_H +#define _ASM_ARCH_IMX8M_CLOCK_H + +enum pll_clocks { + ANATOP_ARM_PLL, + ANATOP_GPU_PLL, + ANATOP_SYSTEM_PLL1, + ANATOP_SYSTEM_PLL2, + ANATOP_SYSTEM_PLL3, + ANATOP_AUDIO_PLL1, + ANATOP_AUDIO_PLL2, + ANATOP_VIDEO_PLL1, + ANATOP_VIDEO_PLL2, + ANATOP_DRAM_PLL, +}; + +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + VPU_A53_CLK_ROOT = 2, + GPU_CORE_CLK_ROOT = 3, + GPU_SHADER_CLK_ROOT = 4, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + DISPLAY_AXI_CLK_ROOT = 20, + DISPLAY_APB_CLK_ROOT = 21, + DISPLAY_RTRM_CLK_ROOT = 22, + USB_BUS_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_APB_CLK_ROOT = 27, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + DISPLAY_DTRC_CLK_ROOT = 68, + DISPLAY_DC8000_CLK_ROOT = 69, + PCIE1_CTRL_CLK_ROOT = 70, + PCIE1_PHY_CLK_ROOT = 71, + PCIE1_AUX_CLK_ROOT = 72, + DC_PIXEL_CLK_ROOT = 73, + LCDIF_PIXEL_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + SPDIF1_CLK_ROOT = 81, + SPDIF2_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + MIPI_DSI_CORE_CLK_ROOT = 118, + MIPI_DSI_PHY_REF_CLK_ROOT = 119, + MIPI_DSI_DBI_CLK_ROOT = 120, + OLD_MIPI_DSI_ESC_CLK_ROOT = 121, + MIPI_CSI1_CORE_CLK_ROOT = 122, + MIPI_CSI1_PHY_REF_CLK_ROOT = 123, + MIPI_CSI1_ESC_CLK_ROOT = 124, + MIPI_CSI2_CORE_CLK_ROOT = 125, + MIPI_CSI2_PHY_REF_CLK_ROOT = 126, + MIPI_CSI2_ESC_CLK_ROOT = 127, + PCIE2_CTRL_CLK_ROOT = 128, + PCIE2_PHY_CLK_ROOT = 129, + PCIE2_AUX_CLK_ROOT = 130, + ECSPI3_CLK_ROOT = 131, + OLD_MIPI_DSI_ESC_RX_ROOT = 132, + DISPLAY_HDMI_CLK_ROOT = 133, + CLK_ROOT_MAX, +}; + +enum clk_root_src { + OSC_25M_CLK, + ARM_PLL_CLK, + DRAM_PLL1_CLK, + VIDEO_PLL2_CLK, + VPU_PLL_CLK, + GPU_PLL_CLK, + SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_266M_CLK, + SYSTEM_PLL1_200M_CLK, + SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, + AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, + OSC_32K_CLK, + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + OSC_27M_CLK, +}; + +/* CCGR index */ +enum clk_ccgr_index { + CCGR_DVFS = 0, + CCGR_ANAMIX = 1, + CCGR_CPU = 2, + CCGR_CSU = 4, + CCGR_DRAM1 = 5, + CCGR_DRAM2_OBSOLETE = 6, + CCGR_ECSPI1 = 7, + CCGR_ECSPI2 = 8, + CCGR_ECSPI3 = 9, + CCGR_ENET1 = 10, + CCGR_GPIO1 = 11, + CCGR_GPIO2 = 12, + CCGR_GPIO3 = 13, + CCGR_GPIO4 = 14, + CCGR_GPIO5 = 15, + CCGR_GPT1 = 16, + CCGR_GPT2 = 17, + CCGR_GPT3 = 18, + CCGR_GPT4 = 19, + CCGR_GPT5 = 20, + CCGR_GPT6 = 21, + CCGR_HS = 22, + CCGR_I2C1 = 23, + CCGR_I2C2 = 24, + CCGR_I2C3 = 25, + CCGR_I2C4 = 26, + CCGR_IOMUX = 27, + CCGR_IOMUX1 = 28, + CCGR_IOMUX2 = 29, + CCGR_IOMUX3 = 30, + CCGR_IOMUX4 = 31, + CCGR_M4 = 32, + CCGR_MU = 33, + CCGR_OCOTP = 34, + CCGR_OCRAM = 35, + CCGR_OCRAM_S = 36, + CCGR_PCIE = 37, + CCGR_PERFMON1 = 38, + CCGR_PERFMON2 = 39, + CCGR_PWM1 = 40, + CCGR_PWM2 = 41, + CCGR_PWM3 = 42, + CCGR_PWM4 = 43, + CCGR_QOS = 44, + CCGR_DISMIX = 45, + CCGR_MEGAMIX = 46, + CCGR_QSPI = 47, + CCGR_RAWNAND = 48, + CCGR_RDC = 49, + CCGR_ROM = 50, + CCGR_SAI1 = 51, + CCGR_SAI2 = 52, + CCGR_SAI3 = 53, + CCGR_SAI4 = 54, + CCGR_SAI5 = 55, + CCGR_SAI6 = 56, + CCGR_SCTR = 57, + CCGR_SDMA1 = 58, + CCGR_SDMA2 = 59, + CCGR_SEC_DEBUG = 60, + CCGR_SEMA1 = 61, + CCGR_SEMA2 = 62, + CCGR_SIM_DISPLAY = 63, + CCGR_SIM_ENET = 64, + CCGR_SIM_M = 65, + CCGR_SIM_MAIN = 66, + CCGR_SIM_S = 67, + CCGR_SIM_WAKEUP = 68, + CCGR_SIM_USB = 69, + CCGR_SIM_VPU = 70, + CCGR_SNVS = 71, + CCGR_TRACE = 72, + CCGR_UART1 = 73, + CCGR_UART2 = 74, + CCGR_UART3 = 75, + CCGR_UART4 = 76, + CCGR_USB_CTRL1 = 77, + CCGR_USB_CTRL2 = 78, + CCGR_USB_PHY1 = 79, + CCGR_USB_PHY2 = 80, + CCGR_USDHC1 = 81, + CCGR_USDHC2 = 82, + CCGR_WDOG1 = 83, + CCGR_WDOG2 = 84, + CCGR_WDOG3 = 85, + CCGR_VA53 = 86, + CCGR_GPU = 87, + CCGR_HEVC = 88, + CCGR_AVC = 89, + CCGR_VP9 = 90, + CCGR_HEVC_INTER = 91, + CCGR_GIC = 92, + CCGR_DISPLAY = 93, + CCGR_HDMI = 94, + CCGR_HDMI_PHY = 95, + CCGR_XTAL = 96, + CCGR_PLL = 97, + CCGR_TSENSOR = 98, + CCGR_VPU_DEC = 99, + CCGR_PCIE2 = 100, + CCGR_MIPI_CSI1 = 101, + CCGR_MIPI_CSI2 = 102, + CCGR_MAX, +}; + +/* src index */ +enum clk_src_index { + CLK_SRC_CKIL_SYNC_REQ = 0, + CLK_SRC_ARM_PLL_EN = 1, + CLK_SRC_GPU_PLL_EN = 2, + CLK_SRC_VPU_PLL_EN = 3, + CLK_SRC_DRAM_PLL_EN = 4, + CLK_SRC_SYSTEM_PLL1_EN = 5, + CLK_SRC_SYSTEM_PLL2_EN = 6, + CLK_SRC_SYSTEM_PLL3_EN = 7, + CLK_SRC_AUDIO_PLL1_EN = 8, + CLK_SRC_AUDIO_PLL2_EN = 9, + CLK_SRC_VIDEO_PLL1_EN = 10, + CLK_SRC_VIDEO_PLL2_EN = 11, + CLK_SRC_ARM_PLL = 12, + CLK_SRC_GPU_PLL = 13, + CLK_SRC_VPU_PLL = 14, + CLK_SRC_DRAM_PLL = 15, + CLK_SRC_SYSTEM_PLL1_800M = 16, + CLK_SRC_SYSTEM_PLL1_400M = 17, + CLK_SRC_SYSTEM_PLL1_266M = 18, + CLK_SRC_SYSTEM_PLL1_200M = 19, + CLK_SRC_SYSTEM_PLL1_160M = 20, + CLK_SRC_SYSTEM_PLL1_133M = 21, + CLK_SRC_SYSTEM_PLL1_100M = 22, + CLK_SRC_SYSTEM_PLL1_80M = 23, + CLK_SRC_SYSTEM_PLL1_40M = 24, + CLK_SRC_SYSTEM_PLL2_1000M = 25, + CLK_SRC_SYSTEM_PLL2_500M = 26, + CLK_SRC_SYSTEM_PLL2_333M = 27, + CLK_SRC_SYSTEM_PLL2_250M = 28, + CLK_SRC_SYSTEM_PLL2_200M = 29, + CLK_SRC_SYSTEM_PLL2_166M = 30, + CLK_SRC_SYSTEM_PLL2_125M = 31, + CLK_SRC_SYSTEM_PLL2_100M = 32, + CLK_SRC_SYSTEM_PLL2_50M = 33, + CLK_SRC_SYSTEM_PLL3 = 34, + CLK_SRC_AUDIO_PLL1 = 35, + CLK_SRC_AUDIO_PLL2 = 36, + CLK_SRC_VIDEO_PLL1 = 37, + CLK_SRC_VIDEO_PLL2 = 38, + CLK_SRC_OSC_25M = 39, + CLK_SRC_OSC_27M = 40, +}; + +/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ +#define FRAC_PLL_LOCK_MASK BIT(31) +#define FRAC_PLL_CLKE_MASK BIT(21) +#define FRAC_PLL_PD_MASK BIT(19) +#define FRAC_PLL_REFCLK_SEL_MASK BIT(16) +#define FRAC_PLL_LOCK_SEL_MASK BIT(15) +#define FRAC_PLL_BYPASS_MASK BIT(14) +#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) +#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) +#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) +#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) +#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) +#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 +#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f +#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f) + +#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) +#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) +#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) +#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16) + +#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) +#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 +#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f +#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) + +/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ +#define SSCG_PLL_LOCK_MASK BIT(31) +#define SSCG_PLL_CLKE_MASK BIT(25) +#define SSCG_PLL_DIV2_CLKE_MASK BIT(23) +#define SSCG_PLL_DIV3_CLKE_MASK BIT(21) +#define SSCG_PLL_DIV4_CLKE_MASK BIT(19) +#define SSCG_PLL_DIV5_CLKE_MASK BIT(17) +#define SSCG_PLL_DIV6_CLKE_MASK BIT(15) +#define SSCG_PLL_DIV8_CLKE_MASK BIT(13) +#define SSCG_PLL_DIV10_CLKE_MASK BIT(11) +#define SSCG_PLL_DIV20_CLKE_MASK BIT(9) +#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) +#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) +#define SSCG_PLL_PLL3_CLKE_MASK BIT(9) +#define SSCG_PLL_PD_MASK BIT(7) +#define SSCG_PLL_BYPASS1_MASK BIT(5) +#define SSCG_PLL_BYPASS2_MASK BIT(4) +#define SSCG_PLL_LOCK_SEL_MASK BIT(3) +#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) +#define SSCG_PLL_REFCLK_SEL_MASK 0x3 +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) + +#define SSCG_PLL_SSDS_MASK BIT(8) +#define SSCG_PLL_SSMD_MASK (0x7 << 5) +#define SSCG_PLL_SSMF_MASK (0xf << 1) +#define SSCG_PLL_SSE_MASK 0x1 + +#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) +#define SSCG_PLL_REF_DIVR1_SHIFT 25 +#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) +#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) +#define SSCG_PLL_REF_DIVR2_SHIFT 19 +#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) +#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 +#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ + SSCG_PLL_FEEDBACK_DIV_F1_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) +#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 +#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ + SSCG_PLL_FEEDBACK_DIV_F2_MASK) +#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) +#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 +#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ + SSCG_PLL_OUTPUT_DIV_VAL_MASK) +#define SSCG_PLL_FILTER_RANGE_MASK 0x1 + +#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) +#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) +#define HW_DIGPROG_MINOR_MASK 0xff + +#define HW_OSC_27M_CLKE_MASK BIT(4) +#define HW_OSC_25M_CLKE_MASK BIT(2) +#define HW_OSC_32K_SEL_MASK 0x1 +#define HW_OSC_32K_SEL_RTC 0x1 +#define HW_OSC_32K_SEL_25M_DIV800 0x0 + +#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) +#define HW_FRAC_ARM_PLL_DIV_SHIFT 20 +#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) +#define HW_FRAC_VPU_PLL_DIV_SHIFT 16 +#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) +#define HW_FRAC_GPU_PLL_DIV_SHIFT 12 +#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) +#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 +#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) +#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 +#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 +#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0 + +#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) +#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 +#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) +#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 +#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) +#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 +#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) +#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 +#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 +#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0 + +enum frac_pll_out_val { + FRAC_PLL_OUT_1000M, + FRAC_PLL_OUT_1600M, +}; +#endif diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 289b9417aaf..feecdb50f6c 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -322,13 +322,10 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) return 0; } -unsigned int mxc_get_clock(enum clk_root_index clk) +unsigned int mxc_get_clock(enum mxc_clock clk) { u32 val; - if (clk >= CLK_ROOT_MAX) - return 0; - if (clk == MXC_ARM_CLK) return get_root_clk(ARM_A53_CLK_ROOT); From 5f24d0cb9c690b32068c9903cd1bc4e78e044865 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:51 +0000 Subject: [PATCH 148/190] imx8m: add clk support for i.MX8MM Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/clock.h | 2 + .../arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Makefile | 1 + arch/arm/mach-imx/imx8m/clock_imx8mm.c | 306 ++++++++++++++ arch/arm/mach-imx/imx8m/clock_slice.c | 63 +++ 5 files changed, 759 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index 80245a2f2d4..dded6e07977 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -9,6 +9,8 @@ #ifdef CONFIG_IMX8MQ #include +#elif defined(CONFIG_IMX8MM) +#include #else #error "Error no clock.h" #endif diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file mode 100644 index 00000000000..305514a4ecc --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + * + * Peng Fan + */ + +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H +#define _ASM_ARCH_IMX8MM_CLOCK_H + +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +#define LOCK_STATUS BIT(31) +#define LOCK_SEL_MASK BIT(29) +#define CLKE_MASK BIT(11) +#define RST_MASK BIT(9) +#define BYPASS_MASK BIT(4) +#define MDIV_SHIFT 12 +#define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 +#define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 +#define SDIV_MASK GENMASK(2, 0) +#define KDIV_SHIFT 0 +#define KDIV_MASK GENMASK(15, 0) + +struct imx_int_pll_rate_table { + u32 rate; + int mdiv; + int pdiv; + int sdiv; + int kdiv; +}; + +enum pll_clocks { + ANATOP_ARM_PLL, + ANATOP_VPU_PLL, + ANATOP_GPU_PLL, + ANATOP_SYSTEM_PLL1, + ANATOP_SYSTEM_PLL2, + ANATOP_SYSTEM_PLL3, + ANATOP_AUDIO_PLL1, + ANATOP_AUDIO_PLL2, + ANATOP_VIDEO_PLL, + ANATOP_DRAM_PLL, +}; + +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + VPU_A53_CLK_ROOT = 2, + GPU3D_CLK_ROOT = 3, + GPU2D_CLK_ROOT = 4, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + DISPLAY_AXI_CLK_ROOT = 20, + DISPLAY_APB_CLK_ROOT = 21, + DISPLAY_RTRM_CLK_ROOT = 22, + USB_BUS_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_APB_CLK_ROOT = 27, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + DISPLAY_DTRC_CLK_ROOT = 68, + DISPLAY_DC8000_CLK_ROOT = 69, + PCIE_CTRL_CLK_ROOT = 70, + PCIE_PHY_CLK_ROOT = 71, + PCIE_AUX_CLK_ROOT = 72, + DC_PIXEL_CLK_ROOT = 73, + LCDIF_PIXEL_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + SPDIF1_CLK_ROOT = 81, + SPDIF2_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + MIPI_DSI_CORE_CLK_ROOT = 118, + MIPI_DSI_PHY_REF_CLK_ROOT = 119, + MIPI_DSI_DBI_CLK_ROOT = 120, + USDHC3_CLK_ROOT = 121, + MIPI_CSI1_CORE_CLK_ROOT = 122, + MIPI_CSI1_PHY_REF_CLK_ROOT = 123, + MIPI_CSI1_ESC_CLK_ROOT = 124, + MIPI_CSI2_CORE_CLK_ROOT = 125, + MIPI_CSI2_PHY_REF_CLK_ROOT = 126, + MIPI_CSI2_ESC_CLK_ROOT = 127, + PCIE2_CTRL_CLK_ROOT = 128, + PCIE2_PHY_CLK_ROOT = 129, + PCIE2_AUX_CLK_ROOT = 130, + ECSPI3_CLK_ROOT = 131, + PDM_CLK_ROOT = 132, + VPU_H1_CLK_ROOT = 133, + CLK_ROOT_MAX, +}; + +enum clk_root_src { + OSC_24M_CLK, + ARM_PLL_CLK, + DRAM_PLL1_CLK, + VIDEO_PLL2_CLK, + VPU_PLL_CLK, + GPU_PLL_CLK, + SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_266M_CLK, + SYSTEM_PLL1_200M_CLK, + SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, + AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, + OSC_32K_CLK, + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + OSC_HDMI_CLK +}; + +enum clk_ccgr_index { + CCGR_DVFS = 0, + CCGR_ANAMIX = 1, + CCGR_CPU = 2, + CCGR_CSU = 3, + CCGR_DEBUG = 4, + CCGR_DDR1 = 5, + CCGR_ECSPI1 = 7, + CCGR_ECSPI2 = 8, + CCGR_ECSPI3 = 9, + CCGR_ENET1 = 10, + CCGR_GPIO1 = 11, + CCGR_GPIO2 = 12, + CCGR_GPIO3 = 13, + CCGR_GPIO4 = 14, + CCGR_GPIO5 = 15, + CCGR_GPT1 = 16, + CCGR_GPT2 = 17, + CCGR_GPT3 = 18, + CCGR_GPT4 = 19, + CCGR_GPT5 = 20, + CCGR_GPT6 = 21, + CCGR_HS = 22, + CCGR_I2C1 = 23, + CCGR_I2C2 = 24, + CCGR_I2C3 = 25, + CCGR_I2C4 = 26, + CCGR_IOMUX = 27, + CCGR_IOMUX1 = 28, + CCGR_IOMUX2 = 29, + CCGR_IOMUX3 = 30, + CCGR_IOMUX4 = 31, + CCGR_SNVSMIX_IPG_CLK = 32, + CCGR_MU = 33, + CCGR_OCOTP = 34, + CCGR_OCRAM = 35, + CCGR_OCRAM_S = 36, + CCGR_PCIE = 37, + CCGR_PERFMON1 = 38, + CCGR_PERFMON2 = 39, + CCGR_PWM1 = 40, + CCGR_PWM2 = 41, + CCGR_PWM3 = 42, + CCGR_PWM4 = 43, + CCGR_QOS = 44, + CCGR_QOS_DISPMIX = 45, + CCGR_QOS_ETHENET = 46, + CCGR_QSPI = 47, + CCGR_RAWNAND = 48, + CCGR_RDC = 49, + CCGR_ROM = 50, + CCGR_SAI1 = 51, + CCGR_SAI2 = 52, + CCGR_SAI3 = 53, + CCGR_SAI4 = 54, + CCGR_SAI5 = 55, + CCGR_SAI6 = 56, + CCGR_SCTR = 57, + CCGR_SDMA1 = 58, + CCGR_SDMA2 = 59, + CCGR_SEC_DEBUG = 60, + CCGR_SEMA1 = 61, + CCGR_SEMA2 = 62, + CCGR_SIM_DISPLAY = 63, + CCGR_SIM_ENET = 64, + CCGR_SIM_M = 65, + CCGR_SIM_MAIN = 66, + CCGR_SIM_S = 67, + CCGR_SIM_WAKEUP = 68, + CCGR_SIM_HSIO = 69, + CCGR_SIM_VPU = 70, + CCGR_SNVS = 71, + CCGR_TRACE = 72, + CCGR_UART1 = 73, + CCGR_UART2 = 74, + CCGR_UART3 = 75, + CCGR_UART4 = 76, + CCGR_USB_MSCALE_PL301 = 77, + CCGR_GPU3D = 79, + CCGR_USDHC1 = 81, + CCGR_USDHC2 = 82, + CCGR_WDOG1 = 83, + CCGR_WDOG2 = 84, + CCGR_WDOG3 = 85, + CCGR_VPUG1 = 86, + CCGR_GPU_BUS = 87, + CCGR_VPUH1 = 89, + CCGR_VPUG2 = 90, + CCGR_PDM = 91, + CCGR_GIC = 92, + CCGR_DISPMIX = 93, + CCGR_USDHC3 = 94, + CCGR_SDMA3 = 95, + CCGR_XTAL = 96, + CCGR_PLL = 97, + CCGR_TEMP_SENSOR = 98, + CCGR_VPUMIX_BUS = 99, + CCGR_GPU2D = 102, + CCGR_MAX +}; + +enum clk_src_index { + CLK_SRC_CKIL_SYNC_REQ = 0, + CLK_SRC_ARM_PLL_EN = 1, + CLK_SRC_GPU_PLL_EN = 2, + CLK_SRC_VPU_PLL_EN = 3, + CLK_SRC_DRAM_PLL_EN = 4, + CLK_SRC_SYSTEM_PLL1_EN = 5, + CLK_SRC_SYSTEM_PLL2_EN = 6, + CLK_SRC_SYSTEM_PLL3_EN = 7, + CLK_SRC_AUDIO_PLL1_EN = 8, + CLK_SRC_AUDIO_PLL2_EN = 9, + CLK_SRC_VIDEO_PLL1_EN = 10, + CLK_SRC_RESERVED = 11, + CLK_SRC_ARM_PLL = 12, + CLK_SRC_GPU_PLL = 13, + CLK_SRC_VPU_PLL = 14, + CLK_SRC_DRAM_PLL = 15, + CLK_SRC_SYSTEM_PLL1_800M = 16, + CLK_SRC_SYSTEM_PLL1_400M = 17, + CLK_SRC_SYSTEM_PLL1_266M = 18, + CLK_SRC_SYSTEM_PLL1_200M = 19, + CLK_SRC_SYSTEM_PLL1_160M = 20, + CLK_SRC_SYSTEM_PLL1_133M = 21, + CLK_SRC_SYSTEM_PLL1_100M = 22, + CLK_SRC_SYSTEM_PLL1_80M = 23, + CLK_SRC_SYSTEM_PLL1_40M = 24, + CLK_SRC_SYSTEM_PLL2_1000M = 25, + CLK_SRC_SYSTEM_PLL2_500M = 26, + CLK_SRC_SYSTEM_PLL2_333M = 27, + CLK_SRC_SYSTEM_PLL2_250M = 28, + CLK_SRC_SYSTEM_PLL2_200M = 29, + CLK_SRC_SYSTEM_PLL2_166M = 30, + CLK_SRC_SYSTEM_PLL2_125M = 31, + CLK_SRC_SYSTEM_PLL2_100M = 32, + CLK_SRC_SYSTEM_PLL2_50M = 33, + CLK_SRC_SYSTEM_PLL3 = 34, + CLK_SRC_AUDIO_PLL1 = 35, + CLK_SRC_AUDIO_PLL2 = 36, + CLK_SRC_VIDEO_PLL1 = 37, +}; + +#define INTPLL_LOCK_MASK BIT(31) +#define INTPLL_LOCK_SEL_MASK BIT(29) +#define INTPLL_EXT_BYPASS_MASK BIT(28) +#define INTPLL_DIV20_CLKE_MASK BIT(27) +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26) +#define INTPLL_DIV10_CLKE_MASK BIT(25) +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24) +#define INTPLL_DIV8_CLKE_MASK BIT(23) +#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22) +#define INTPLL_DIV6_CLKE_MASK BIT(21) +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20) +#define INTPLL_DIV5_CLKE_MASK BIT(19) +#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18) +#define INTPLL_DIV4_CLKE_MASK BIT(17) +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16) +#define INTPLL_DIV3_CLKE_MASK BIT(15) +#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14) +#define INTPLL_DIV2_CLKE_MASK BIT(13) +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12) +#define INTPLL_CLKE_MASK BIT(11) +#define INTPLL_CLKE_OVERRIDE_MASK BIT(10) +#define INTPLL_RST_MASK BIT(9) +#define INTPLL_RST_OVERRIDE_MASK BIT(8) +#define INTPLL_BYPASS_MASK BIT(4) +#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2) +#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0) + +#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12) +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12)) +#define INTPLL_MAIN_DIV_SHIFT 12 +#define INTPLL_PRE_DIV_MASK GENMASK(9, 4) +#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4)) +#define INTPLL_PRE_DIV_SHIFT 4 +#define INTPLL_POST_DIV_MASK GENMASK(2, 0) +#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0)) +#define INTPLL_POST_DIV_SHIFT 0 + +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4) +#define INTPLL_LOCK_CON_DLY_SHIFT 4 +#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2) +#define INTPLL_LOCK_CON_OUT_SHIFT 2 +#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0) +#define INTPLL_LOCK_CON_IN_SHIFT 0 + +#define INTPLL_LRD_EN_MASK BIT(21) +#define INTPLL_FOUT_MASK BIT(20) +#define INTPLL_AFC_SEL_MASK BIT(19) +#define INTPLL_PBIAS_CTRL_MASK BIT(18) +#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17) +#define INTPLL_AFCINIT_SEL_MASK BIT(16) +#define INTPLL_FSEL_MASK BIT(14) +#define INTPLL_FEED_EN_MASK BIT(13) +#define INTPLL_EXTAFC_MASK GENMASK(7, 3) +#define INTPLL_AFC_EN_MASK BIT(2) +#define INTPLL_ICP_MASK GENMASK(1, 0) + +#endif diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile index 42a1544c6b7..92184f31351 100644 --- a/arch/arm/mach-imx/imx8m/Makefile +++ b/arch/arm/mach-imx/imx8m/Makefile @@ -5,3 +5,4 @@ obj-y += lowlevel_init.o obj-y += clock_slice.o soc.o obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o +obj-$(CONFIG_IMX8MM) += clock_imx8mm.o diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c new file mode 100644 index 00000000000..ee44ba75feb --- /dev/null +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * + * Peng Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; + +void enable_ocotp_clk(unsigned char enable) +{ + struct clk *clkp; + int ret; + + ret = clk_get_by_id(IMX8MM_CLK_OCOTP_ROOT, &clkp); + if (ret) { + printf("%s: err: %d\n", __func__, ret); + return; + } + + enable ? clk_enable(clkp) : clk_disable(clkp); +} + +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + struct clk *clkp; + int ret; + + ret = clk_get_by_id(IMX8MM_CLK_I2C1_ROOT + i2c_num, &clkp); + if (ret) { + printf("%s: err: %d\n", __func__, ret); + return ret; + } + + return enable ? clk_enable(clkp) : clk_disable(clkp); +} + +#ifdef CONFIG_SPL_BUILD +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { + PLL_1443X_RATE(800000000U, 300, 9, 0, 0), + PLL_1443X_RATE(750000000U, 250, 8, 0, 0), + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), + PLL_1443X_RATE(600000000U, 300, 3, 2, 0), + PLL_1443X_RATE(594000000U, 99, 1, 2, 0), + PLL_1443X_RATE(400000000U, 300, 9, 1, 0), + PLL_1443X_RATE(266666667U, 400, 9, 2, 0), + PLL_1443X_RATE(167000000U, 334, 3, 4, 0), + PLL_1443X_RATE(100000000U, 300, 9, 3, 0), +}; + +int fracpll_configure(enum pll_clocks pll, u32 freq) +{ + int i; + u32 tmp, div_val; + void *pll_base; + struct imx_int_pll_rate_table *rate; + + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) { + if (freq == imx8mm_fracpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) { + printf("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx8mm_fracpll_tbl[i]; + + switch (pll) { + case ANATOP_DRAM_PLL: + setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); + setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); + writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); + + pll_base = &ana_pll->dram_pll_gnrl_ctl; + break; + case ANATOP_VIDEO_PLL: + pll_base = &ana_pll->video_pll1_gnrl_ctl; + break; + default: + return 0; + } + /* Bypass clock and set lock to pll output lock */ + tmp = readl(pll_base); + tmp |= BYPASS_MASK; + writel(tmp, pll_base); + + /* Enable RST */ + tmp &= ~RST_MASK; + writel(tmp, pll_base); + + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | + (rate->sdiv << SDIV_SHIFT); + writel(div_val, pll_base + 4); + writel(rate->kdiv << KDIV_SHIFT, pll_base + 8); + + __udelay(100); + + /* Disable RST */ + tmp |= RST_MASK; + writel(tmp, pll_base); + + /* Wait Lock*/ + while (!(readl(pll_base) & LOCK_STATUS)) + ; + + /* Bypass */ + tmp &= ~BYPASS_MASK; + writel(tmp, pll_base); + + return 0; +} + +void dram_pll_init(ulong pll_val) +{ + fracpll_configure(ANATOP_DRAM_PLL, pll_val); +} + +static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = { + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, + CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, + CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, + CLK_ROOT_PRE_DIV2), +}; + +void dram_enable_bypass(ulong clk_val) +{ + int i; + struct dram_bypass_clk_setting *config; + + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) { + if (clk_val == imx8mm_dram_bypass_tbl[i].clk) + break; + } + + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) { + printf("No matched freq table %lu\n", clk_val); + return; + } + + config = &imx8mm_dram_bypass_tbl[i]; + + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | + CLK_ROOT_PRE_DIV(config->alt_pre_div)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | + CLK_ROOT_PRE_DIV(config->apb_pre_div)); + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); +} + +void dram_disable_bypass(void) +{ + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +} +#endif + +void init_uart_clk(u32 index) +{ + /* + * set uart clock root + * 24M OSC + */ + switch (index) { + case 0: + clock_enable(CCGR_UART1, 0); + clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART1, 1); + return; + case 1: + clock_enable(CCGR_UART2, 0); + clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART2, 1); + return; + case 2: + clock_enable(CCGR_UART3, 0); + clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART3, 1); + return; + case 3: + clock_enable(CCGR_UART4, 0); + clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART4, 1); + return; + default: + printf("Invalid uart index\n"); + return; + } +} + +void init_wdog_clk(void) +{ + clock_enable(CCGR_WDOG1, 0); + clock_enable(CCGR_WDOG2, 0); + clock_enable(CCGR_WDOG3, 0); + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_WDOG1, 1); + clock_enable(CCGR_WDOG2, 1); + clock_enable(CCGR_WDOG3, 1); +} + +int clock_init(void) +{ + u32 val_cfg0; + + /* + * The gate is not exported to clk tree, so configure them here. + * According to ANAMIX SPEC + * sys pll1 fixed at 800MHz + * sys pll2 fixed at 1GHz + * Here we only enable the outputs. + */ + val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | + INTPLL_DIV20_CLKE_MASK; + writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); + + val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | + INTPLL_DIV20_CLKE_MASK; + writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); + + /* config GIC to sys_pll2_100m */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(3)); + clock_enable(CCGR_GIC, 1); + + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + + clock_enable(CCGR_DDR1, 0); + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_DDR1, 1); + + init_wdog_clk(); + + clock_enable(CCGR_TEMP_SENSOR, 1); + + clock_enable(CCGR_SEC_DEBUG, 1); + + return 0; +}; + +u32 imx_get_uartclk(void) +{ + return 24000000U; +} + +u32 mxc_get_clock(enum mxc_clock clk) +{ + struct clk *clkp; + int ret; + + switch (clk) { + case MXC_IPG_CLK: + ret = clk_get_by_id(IMX8MM_CLK_IPG_ROOT, &clkp); + if (ret) + return 0; + return clk_get_rate(clkp); + case MXC_ARM_CLK: + ret = clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp); + if (ret) + return 0; + return clk_get_rate(clkp); + default: + printf("%s: %d not supported\n", __func__, clk); + } + + return 0; +} diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index 1a67c626f1a..780f64314d0 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -13,6 +13,7 @@ static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; +#ifdef CONFIG_IMX8MQ static struct clk_root_map root_array[] = { {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, @@ -474,6 +475,68 @@ static struct clk_root_map root_array[] = { {DRAM_PLL1_CLK} }, }; +#elif defined(CONFIG_IMX8MM) +static struct clk_root_map root_array[] = { + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK} + }, + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK} + }, + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK} + }, + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, +}; +#endif static int select(enum clk_root_index clock_id) { From e89d211f30277e8d1600ed00b5c9244d8f891aaf Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:54 +0000 Subject: [PATCH 149/190] imx: mmc_env: update runtime SD/MMC boot env device When DM_MMC enabled, the USDHC index in U-Boot is the USDHC port. To directly return devno, we could avoid add board specific code. Signed-off-by: Peng Fan --- arch/arm/mach-imx/mmc_env.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 9c822f721c6..addb50f5382 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -11,6 +11,9 @@ __weak int board_mmc_get_env_dev(int devno) { + if (CONFIG_IS_ENABLED(DM_MMC)) + return devno; + return CONFIG_SYS_MMC_ENV_DEV; } From e663c703b16b515ce0038f971c5d10d33884869b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:25:58 +0000 Subject: [PATCH 150/190] imx8m: soc: probe clock device in arch_cpu_init_dm Because we need to get cpu freq in print_cpuinfo at very early stage, so we need to make sure the ccm be probed. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 3a54db48980..f9040491200 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -228,6 +229,22 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog3->wmcr); } +int arch_cpu_init_dm(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + return ret; + } + + return 0; +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; From 2f1723132e3c0d6e5a9ea832a274a1ac48f345e1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:26:01 +0000 Subject: [PATCH 151/190] arm: dts: import i.MX8MM dtsi Import i.MX8MM dtsi from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan --- arch/arm/dts/imx8mm.dtsi | 733 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 733 insertions(+) create mode 100644 arch/arm/dts/imx8mm.dtsi diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi new file mode 100644 index 00000000000..6b407a94c06 --- /dev/null +++ b/arch/arm/dts/imx8mm.dtsi @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include + +#include "imx8mm-pinfunc.h" + +/ { + compatible = "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MM_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MM_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MM_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MM_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + clock-latency-ns = <150000>; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + arm,no-tick-in-suspend; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips1: bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: watchdog@30290000 { + compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: watchdog@302a0000 { + compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + + sdma2: dma-controller@302c0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; + reg = <0x302c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, + <&clk IMX8MM_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + sdma3: dma-controller@302b0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; + reg = <0x302b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, + <&clk IMX8MM_CLK_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; + /* For nvmem subnodes */ + #address-cells = <1>; + #size-cells = <1>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; + reg = <0x30360000 0x10000>; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + src: reset-controller@30390000 { + compatible = "fsl,imx8mm-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = ; + #reset-cells = <1>; + }; + }; + + aips2: bus@30400000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, + <&clk IMX8MM_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, + <&clk IMX8MM_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, + <&clk IMX8MM_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, + <&clk IMX8MM_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ecspi1: spi@30820000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, + <&clk IMX8MM_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, + <&clk IMX8MM_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, + <&clk IMX8MM_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_UART1_ROOT>, + <&clk IMX8MM_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_UART3_ROOT>, + <&clk IMX8MM_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_UART2_ROOT>, + <&clk IMX8MM_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30a20000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30a30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30a50000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_UART4_ROOT>, + <&clk IMX8MM_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS>, + <&clk IMX8MM_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS>, + <&clk IMX8MM_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS>, + <&clk IMX8MM_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, + <&clk IMX8MM_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = , + , + ; + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>, + <&clk IMX8MM_CLK_ENET_PHY_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>, + <&clk IMX8MM_CLK_ENET_TIMER>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + + }; + + aips4: bus@32c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbotg1: usb@32e40000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x32e40000 0x200>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc1: usbmisc@32e40200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x32e40200 0x200>; + }; + + usbotg2: usb@32e50000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x32e50000 0x200>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc2: usbmisc@32e50200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x32e50200 0x200>; + }; + + }; + + dma_apbh: dma-controller@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: nand-controller@33002000{ + compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MM_CLK_NAND_ROOT>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + }; +}; From d68d73df177ce948b77296afcf322226f9c2f725 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:26:04 +0000 Subject: [PATCH 152/190] arm: dts: add i.MX8MM pin func Import i.MX8MM pin func from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan --- arch/arm/dts/imx8mm-pinfunc.h | 629 ++++++++++++++++++++++++++++++++++ 1 file changed, 629 insertions(+) create mode 100644 arch/arm/dts/imx8mm-pinfunc.h diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h new file mode 100644 index 00000000000..e25f7fcd799 --- /dev/null +++ b/arch/arm/dts/imx8mm-pinfunc.h @@ -0,0 +1,629 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __DTS_IMX8MM_PINFUNC_H +#define __DTS_IMX8MM_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 + +#endif /* __DTS_IMX8MM_PINFUNC_H */ From 9b15ce91939d6469dda92eb297b44fa87572629a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 27 Aug 2019 06:26:08 +0000 Subject: [PATCH 153/190] imx: Add i.MX8MM EVK board support. Add board and SoC dts Add ddr training code support SD/MMC/GPIO/PINCTRL/UART Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 92 + arch/arm/dts/imx8mm-evk.dts | 235 +++ arch/arm/mach-imx/imx8m/Kconfig | 7 + board/freescale/imx8mm_evk/Kconfig | 12 + board/freescale/imx8mm_evk/MAINTAINERS | 6 + board/freescale/imx8mm_evk/Makefile | 12 + board/freescale/imx8mm_evk/README | 37 + board/freescale/imx8mm_evk/imx8mm_evk.c | 29 + board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 ++++++++++++++++++++ board/freescale/imx8mm_evk/spl.c | 129 ++ configs/imx8mm_evk_defconfig | 74 + include/configs/imx8mm_evk.h | 153 ++ 13 files changed, 2768 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-evk.dts create mode 100644 board/freescale/imx8mm_evk/Kconfig create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS create mode 100644 board/freescale/imx8mm_evk/Makefile create mode 100644 board/freescale/imx8mm_evk/README create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8mm_evk/spl.c create mode 100644 configs/imx8mm_evk_defconfig create mode 100644 include/configs/imx8mm_evk.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7a0b05b8cac..2c86b293a80 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -641,7 +641,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb -dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \ + imx8mm-evk.dtb dtb-$(CONFIG_RCAR_GEN2) += \ r8a7790-lager-u-boot.dtb \ diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi new file mode 100644 index 00000000000..1095d36e312 --- /dev/null +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&{/soc} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts new file mode 100644 index 00000000000..2d5d89475b7 --- /dev/null +++ b/arch/arm/dts/imx8mm-evk.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM EVK board"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 35c978e8630..f5200758755 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK select IMX8MQ select IMX8M_LPDDR4 +config TARGET_IMX8MM_EVK + bool "imx8mm LPDDR4 EVK board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + endchoice source "board/freescale/imx8mq_evk/Kconfig" +source "board/freescale/imx8mm_evk/Kconfig" endif diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig new file mode 100644 index 00000000000..299691a6194 --- /dev/null +++ b/board/freescale/imx8mm_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MM_EVK + +config SYS_BOARD + default "imx8mm_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mm_evk" + +endif diff --git a/board/freescale/imx8mm_evk/MAINTAINERS b/board/freescale/imx8mm_evk/MAINTAINERS new file mode 100644 index 00000000000..b031bb06745 --- /dev/null +++ b/board/freescale/imx8mm_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8MM EVK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/imx8mm_evk/ +F: include/configs/imx8mm_evk.h +F: configs/imx8mm_evk_defconfig diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile new file mode 100644 index 00000000000..1db7b62cafc --- /dev/null +++ b/board/freescale/imx8mm_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/freescale/imx8mm_evk/README b/board/freescale/imx8mm_evk/README new file mode 100644 index 00000000000..a885bc5c97d --- /dev/null +++ b/board/freescale/imx8mm_evk/README @@ -0,0 +1,37 @@ +U-Boot for the NXP i.MX8MM EVK board + +Quick Start +=========== +- Build the ARM Trusted firmware binary +- Get ddr fimware +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +====================================== +Note: srctree is U-Boot source directory +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +branch: imx_4.19.35_1.0.0 +$ make PLAT=imx8mm bl31 +$ cp build/imx8mm/release/bl31.bin $(srctree) + +Get the ddr and hdmi firmware +============================= +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0 +$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Build U-Boot +============ +$ export CROSS_COMPILE=aarch64-poky-linux- +$ make imx8mm_evk_defconfig +$ export ATF_LOAD_ADDR=0x920000 +$ make flash.bin + +Burn the flash.bin to MicroSD card offset 33KB +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +==== +Set Boot switch to SD boot diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644 index 00000000000..3706e1ec550 --- /dev/null +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MM"); +#endif + return 0; +} diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644 index 00000000000..8e48b9d81b7 --- /dev/null +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c @@ -0,0 +1,1980 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa1080020 }, + { DDRC_RFSHTMG(0), 0x005b00d2 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG2(0), 0x0000170A }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + { DDRC_DBICTL(0), 0x00000001 }, + + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x0000001f }, + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP2(0), 0x00000000 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x07070707 }, + { DDRC_ADDRMAP7(0), 0x00000f0f }, + + /* performance setting */ + { DDRC_SCHED(0), 0x29001701 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x04000030 }, + { DDRC_PERFLPR1(0), 0x900093e7 }, + { DDRC_PERFWR1(0), 0x20005574 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCFGQOS0_0(0), 0x02100e07 }, + { DDRC_PCFGQOS1_0(0), 0x00620096 }, + { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, + { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + + /* frequency P1&P2 */ + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310000 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, + + /* boot start point */ + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + + { 0x200b2, 0x1d4 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + + { 0x20025, 0x0 }, + { 0x2002d, LPDDR4_PHY_DMIPinPresent }, + { 0x12002d, LPDDR4_PHY_DMIPinPresent }, + { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), +}; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c new file mode 100644 index 00000000000..043b5f43426 --- /dev/null +++ b/board/freescale/imx8mm_evk/spl.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + puts("Normal Boot\n"); + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) + printf("Failed to find clock node. Check device tree\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + puts ("resetting ...\n"); + + reset_cpu(WDOG1_BASE_ADDR); + + return 0; +} diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig new file mode 100644 index 00000000000..a934363277d --- /dev/null +++ b/configs/imx8mm_evk_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h new file mode 100644 index 00000000000..a9d99ec8b7b --- /dev/null +++ b/include/configs/imx8mm_evk.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8MM_EVK_H +#define __IMX8MM_EVK_H + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE SZ_8K +#endif + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image.itb\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#endif +#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif From 30ecc9c323ec2db72a709da7d3f3f70373aa52ee Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:40 +0800 Subject: [PATCH 154/190] spl: mmc: introduce spl_mmc_get_uboot_raw_sector Introduce a weak function spl_mmc_get_uboot_raw_sector, then platform could have their own implementation. Signed-off-by: Peng Fan Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: Marek Vasut Cc: Andreas Dannenberg Cc: Alex Kiernan Cc: Stefan Roese Cc: Patrick Delaunay Cc: Miquel Raynal Cc: Michal Simek --- common/spl/spl_mmc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 6c6eaf4ec87..ebc566081ad 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -313,6 +313,15 @@ int spl_boot_partition(const u32 boot_device) } #endif +unsigned long __weak spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +#else + return 0; +#endif +} + int spl_mmc_load(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, const char *filename, @@ -340,6 +349,8 @@ int spl_mmc_load(struct spl_image_info *spl_image, } } + raw_sect = spl_mmc_get_uboot_raw_sector(mmc); + boot_mode = spl_boot_mode(bootdev->boot_device); err = -EINVAL; switch (boot_mode) { From ec649330942b7898f0e95c832f16ee189df91609 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:41 +0800 Subject: [PATCH 155/190] spl: spi: introduce spl_spi_get_uboot_offs Introduce a weak function spl_spi_get_uboot_offs, then platform could have their own implementation. Signed-off-by: Peng Fan Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: Marek Vasut Cc: Andreas Dannenberg Cc: Alex Kiernan Cc: Stefan Roese Cc: Patrick Delaunay Cc: Miquel Raynal Cc: Michal Simek --- common/spl/spl_spi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 9b74473377f..84f20ea4ed9 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -62,6 +62,12 @@ static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector, else return 0; } + +unsigned int __weak spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + return CONFIG_SYS_SPI_U_BOOT_OFFS; +} + /* * The main entry for SPI booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -71,7 +77,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int err = 0; - unsigned payload_offs = CONFIG_SYS_SPI_U_BOOT_OFFS; + unsigned int payload_offs; struct spi_flash *flash; struct image_header *header; @@ -90,6 +96,8 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, return -ENODEV; } + payload_offs = spl_spi_get_uboot_offs(flash); + header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) From 07d900af76228e0f88116919272b935d456d112b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:42 +0800 Subject: [PATCH 156/190] spl: nor: introduce spl_nor_get_uboot_base Introduce weak spl_nor_get_uboot_base, then platform have their own implementation. Signed-off-by: Peng Fan Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: Marek Vasut Cc: Andreas Dannenberg Cc: Alex Kiernan Cc: Stefan Roese Cc: Patrick Delaunay Cc: Miquel Raynal Cc: Michal Simek --- common/spl/spl_nor.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 969e319de06..0f8afa6f926 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -18,6 +18,11 @@ static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, } #endif +unsigned long __weak spl_nor_get_uboot_base(void) +{ + return CONFIG_SYS_UBOOT_BASE; +} + static int spl_nor_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { @@ -80,25 +85,25 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, * defined location in SDRAM */ #ifdef CONFIG_SPL_LOAD_FIT - header = (const struct image_header *)CONFIG_SYS_UBOOT_BASE; + header = (const struct image_header *)spl_nor_get_uboot_base(); if (image_get_magic(header) == FDT_MAGIC) { debug("Found FIT format U-Boot\n"); load.bl_len = 1; load.read = spl_nor_load_read; ret = spl_load_simple_fit(spl_image, &load, - CONFIG_SYS_UBOOT_BASE, + spl_nor_get_uboot_base(), (void *)header); return ret; } #endif ret = spl_parse_image_header(spl_image, - (const struct image_header *)CONFIG_SYS_UBOOT_BASE); + (const struct image_header *)spl_nor_get_uboot_base()); if (ret) return ret; memcpy((void *)(unsigned long)spl_image->load_addr, - (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)), + (void *)(spl_nor_get_uboot_base() + sizeof(struct image_header)), spl_image->size); return 0; From 2c79229c02ad9f0eae4faee028a76394d00a699d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:43 +0800 Subject: [PATCH 157/190] spl: nand: Introduce spl_nand_get_uboot_raw_page Introduce weak spl_nand_get_uboot_raw_page, then platform could have their own implementation. Signed-off-by: Peng Fan Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: Marek Vasut Cc: Andreas Dannenberg Cc: Alex Kiernan Cc: Stefan Roese Cc: Patrick Delaunay Cc: Miquel Raynal Cc: Michal Simek --- common/spl/spl_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index e2bcefb111e..d3185dc0170 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -11,6 +11,11 @@ #include #include +uint32_t __weak spl_nand_get_uboot_raw_page(void) +{ + return CONFIG_SYS_NAND_U_BOOT_OFFS; +} + #if defined(CONFIG_SPL_NAND_RAW_ONLY) static int spl_nand_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) @@ -21,7 +26,7 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, CONFIG_SYS_NAND_U_BOOT_DST); - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + nand_spl_load_image(spl_nand_get_uboot_raw_page(), CONFIG_SYS_NAND_U_BOOT_SIZE, (void *)CONFIG_SYS_NAND_U_BOOT_DST); spl_set_header_raw_uboot(spl_image); @@ -139,7 +144,7 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, #endif #endif /* Load u-boot */ - err = spl_nand_load_element(spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS, + err = spl_nand_load_element(spl_image, spl_nand_get_uboot_raw_page(), header); #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND #if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND From d1c07785fd68def6aa2251a15eed99f2e9c8071f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:44 +0800 Subject: [PATCH 158/190] imx8: Add support to get container image set size To avoid hardcoded offset when adding u-boot.cnt to flash.bin, we use flexible offset which is calculated based on the size of the container image generated int the first stage. And pad u-boot.cnt at 1KB alignment. So add code to get the offset when SPL loading u-boot.cnt. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/Makefile | 9 +- arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/image.c | 246 ++++++++++++++++++++++++++++++++ 3 files changed, 255 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-imx/imx8/image.c diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 17b241ae996..87fd69706d2 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -169,9 +169,16 @@ u-boot.cnt: MKIMAGEOUTPUT = u-boot.cnt.log ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y) u-boot.cnt: u-boot.bin container.cfg FORCE $(call if_changed,mkimage) -endif flash.bin: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) + @flashbin_size=`wc -c flash.bin | awk '{print $$1}'`; \ + pad_cnt=$$(((flashbin_size + 0x400 - 1) / 0x400)); \ + echo "append u-boot.cnt at $$pad_cnt KB"; \ + dd if=u-boot.cnt of=flash.bin bs=1K seek=$$pad_cnt; +else +flash.bin: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) +endif endif else diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 97f9d229451..39e384d5c75 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -8,5 +8,5 @@ obj-y += cpu.o iomux.o misc.o lowlevel_init.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += parse-container.o +obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o endif diff --git a/arch/arm/mach-imx/imx8/image.c b/arch/arm/mach-imx/imx8/image.c new file mode 100644 index 00000000000..58a29e8a03c --- /dev/null +++ b/arch/arm/mach-imx/imx8/image.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MMC_DEV 0 +#define QSPI_DEV 1 +#define NAND_DEV 2 +#define QSPI_NOR_DEV 3 + +static int __get_container_size(ulong addr) +{ + struct container_hdr *phdr; + struct boot_img_t *img_entry; + struct signature_block_hdr *sign_hdr; + u8 i = 0; + u32 max_offset = 0, img_end; + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 && phdr->version != 0x0) { + debug("Wrong container header\n"); + return -EFAULT; + } + + max_offset = sizeof(struct container_hdr); + + img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr)); + for (i = 0; i < phdr->num_images; i++) { + img_end = img_entry->offset + img_entry->size; + if (img_end > max_offset) + max_offset = img_end; + + debug("img[%u], end = 0x%x\n", i, img_end); + + img_entry++; + } + + if (phdr->sig_blk_offset != 0) { + sign_hdr = (struct signature_block_hdr *)(addr + phdr->sig_blk_offset); + u16 len = sign_hdr->length_lsb + (sign_hdr->length_msb << 8); + + if (phdr->sig_blk_offset + len > max_offset) + max_offset = phdr->sig_blk_offset + len; + + debug("sigblk, end = 0x%x\n", phdr->sig_blk_offset + len); + } + + return max_offset; +} + +static int get_container_size(void *dev, int dev_type, unsigned long offset) +{ + u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT); + int ret = 0; + + if (!buf) { + printf("Malloc buffer failed\n"); + return -ENOMEM; + } + +#ifdef CONFIG_SPL_MMC_SUPPORT + if (dev_type == MMC_DEV) { + unsigned long count = 0; + struct mmc *mmc = (struct mmc *)dev; + + count = blk_dread(mmc_get_blk_desc(mmc), + offset / mmc->read_bl_len, + CONTAINER_HDR_ALIGNMENT / mmc->read_bl_len, + buf); + if (count == 0) { + printf("Read container image from MMC/SD failed\n"); + return -EIO; + } + } +#endif + +#ifdef CONFIG_SPL_SPI_LOAD + if (dev_type == QSPI_DEV) { + struct spi_flash *flash = (struct spi_flash *)dev; + + ret = spi_flash_read(flash, offset, + CONTAINER_HDR_ALIGNMENT, buf); + if (ret != 0) { + printf("Read container image from QSPI failed\n"); + return -EIO; + } + } +#endif + +#ifdef CONFIG_SPL_NAND_SUPPORT + if (dev_type == NAND_DEV) { + ret = nand_spl_load_image(offset, CONTAINER_HDR_ALIGNMENT, + buf); + if (ret != 0) { + printf("Read container image from NAND failed\n"); + return -EIO; + } + } +#endif + +#ifdef CONFIG_SPL_NOR_SUPPORT + if (dev_type == QSPI_NOR_DEV) + memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT); +#endif + + ret = __get_container_size((ulong)buf); + + free(buf); + + return ret; +} + +static unsigned long get_boot_device_offset(void *dev, int dev_type) +{ + unsigned long offset = 0; + + if (dev_type == MMC_DEV) { + struct mmc *mmc = (struct mmc *)dev; + + if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { + offset = CONTAINER_HDR_MMCSD_OFFSET; + } else { + u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == 1 || part == 2) { + if (is_imx8qxp() && is_soc_rev(CHIP_REV_B)) + offset = CONTAINER_HDR_MMCSD_OFFSET; + else + offset = CONTAINER_HDR_EMMC_OFFSET; + } else { + offset = CONTAINER_HDR_MMCSD_OFFSET; + } + } + } else if (dev_type == QSPI_DEV) { + offset = CONTAINER_HDR_QSPI_OFFSET; + } else if (dev_type == NAND_DEV) { + offset = CONTAINER_HDR_NAND_OFFSET; + } else if (dev_type == QSPI_NOR_DEV) { + offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; + } + + return offset; +} + +static int get_imageset_end(void *dev, int dev_type) +{ + unsigned long offset1 = 0, offset2 = 0; + int value_container[2]; + + offset1 = get_boot_device_offset(dev, dev_type); + offset2 = CONTAINER_HDR_ALIGNMENT + offset1; + + value_container[0] = get_container_size(dev, dev_type, offset1); + if (value_container[0] < 0) { + printf("Parse seco container failed %d\n", value_container[0]); + return value_container[0]; + } + + debug("seco container size 0x%x\n", value_container[0]); + + value_container[1] = get_container_size(dev, dev_type, offset2); + if (value_container[1] < 0) { + debug("Parse scu container failed %d, only seco container\n", + value_container[1]); + /* return seco container total size */ + return value_container[0] + offset1; + } + + debug("scu container size 0x%x\n", value_container[1]); + + return value_container[1] + offset2; +} + +#ifdef CONFIG_SPL_SPI_LOAD +unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + int end; + + end = get_imageset_end(flash, QSPI_DEV); + end = ROUND(end, SZ_1K); + + printf("Load image from QSPI 0x%x\n", end); + + return end; +} +#endif + +#ifdef CONFIG_SPL_MMC_SUPPORT +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + int end; + + end = get_imageset_end(mmc, MMC_DEV); + end = ROUND(end, SZ_1K); + + printf("Load image from MMC/SD 0x%x\n", end); + + return end / mmc->read_bl_len; +} +#endif + +#ifdef CONFIG_SPL_NAND_SUPPORT +uint32_t spl_nand_get_uboot_raw_page(void) +{ + int end; + + end = get_imageset_end((void *)NULL, NAND_DEV); + end = ROUND(end, SZ_16K); + + printf("Load image from NAND 0x%x\n", end); + + return end; +} +#endif + +#ifdef CONFIG_SPL_NOR_SUPPORT +unsigned long spl_nor_get_uboot_base(void) +{ + int end; + + /* Calculate the image set end, + * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000), + * we use CONFIG_SYS_UBOOT_BASE + * Otherwise, use the calculated address + */ + end = get_imageset_end((void *)NULL, QSPI_NOR_DEV); + if (end <= CONFIG_SYS_UBOOT_BASE) + end = CONFIG_SYS_UBOOT_BASE; + else + end = ROUND(end, SZ_1K); + + printf("Load image from NOR 0x%x\n", end); + + return end; +} +#endif From 62f0bfc016d25d22425fc24cd34684d8030f919b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:45 +0800 Subject: [PATCH 159/190] imx8: update README After u-boot.cnt is padded to flash.bin automatically by script, no need to burn the image mannually, so drop the step. Signed-off-by: Peng Fan --- board/freescale/imx8qm_mek/README | 1 - board/freescale/imx8qxp_mek/README | 1 - 2 files changed, 2 deletions(-) diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README index ebf630c446a..a187ad8a09c 100644 --- a/board/freescale/imx8qm_mek/README +++ b/board/freescale/imx8qm_mek/README @@ -41,7 +41,6 @@ Build U-Boot ============ $ make imx8qm_mek_defconfig $ make flash.bin -$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984 Flash the binary into the SD card ================================= diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README index 1ee03579614..e676e88664e 100644 --- a/board/freescale/imx8qxp_mek/README +++ b/board/freescale/imx8qxp_mek/README @@ -41,7 +41,6 @@ Build U-Boot ============ $ make imx8qxp_mek_defconfig $ make flash.bin -$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984 Flash the binary into the SD card ================================= From 00e180cc513ee8ea4f2a3c17758772e710deb4df Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:46 +0800 Subject: [PATCH 160/190] spl: nand: support loading i.MX container format file i.MX8 only support AHAB secure boot with Container format image, we could not use FIT to support secure boot, so introduce container support to let SPL could load container images. Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: York Sun Cc: Marek Vasut Cc: Alex Kiernan Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Heiko Schocher Signed-off-by: Peng Fan --- common/spl/spl_nand.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index d3185dc0170..5f8a111a2f0 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -68,6 +68,15 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, load.bl_len = 1; load.read = spl_nand_fit_read; return spl_load_simple_fit(spl_image, &load, offset, header); + } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { + struct spl_load_info load; + + load.dev = NULL; + load.priv = NULL; + load.filename = NULL; + load.bl_len = 1; + load.read = spl_nand_fit_read; + return spl_load_imx_container(spl_image, &load, offset); } else { err = spl_parse_image_header(spl_image, header); if (err) From d9bd2f4a4efa15b129749978ca48675633a13668 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:47 +0800 Subject: [PATCH 161/190] spl: spi: support loading i.MX container format file i.MX8 only support AHAB secure boot with Container format image, we could not use FIT to support secure boot, so introduce container support to let SPL could load container images. Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: York Sun Cc: Marek Vasut Cc: Alex Kiernan Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Heiko Schocher Signed-off-by: Peng Fan --- common/spl/spl_spi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 84f20ea4ed9..288dbb5fa98 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -141,6 +141,17 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, err = spl_load_simple_fit(spl_image, &load, payload_offs, header); + } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { + struct spl_load_info load; + + load.dev = flash; + load.priv = NULL; + load.filename = NULL; + load.bl_len = 1; + load.read = spl_spi_fit_read; + + err = spl_load_imx_container(spl_image, &load, + payload_offs); } else { err = spl_parse_image_header(spl_image, header); if (err) From 3bc4f1df033bdad3c1dbd89c1714886a0b075fac Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:18:48 +0800 Subject: [PATCH 162/190] spl: nor: support loading i.MX container format file i.MX8 only support AHAB secure boot with Container format image, we could not use FIT to support secure boot, so introduce container support to let SPL could load container images. Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: York Sun Cc: Marek Vasut Cc: Alex Kiernan Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Heiko Schocher Signed-off-by: Peng Fan --- common/spl/spl_nor.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 0f8afa6f926..7df708de9b0 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -6,7 +6,6 @@ #include #include -#ifdef CONFIG_SPL_LOAD_FIT static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { @@ -16,7 +15,6 @@ static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, return count; } -#endif unsigned long __weak spl_nor_get_uboot_base(void) { @@ -97,6 +95,13 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, return ret; } #endif + if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { + load.bl_len = 1; + load.read = spl_nor_load_read; + return spl_load_imx_container(spl_image, &load, + spl_nor_get_uboot_base()); + } + ret = spl_parse_image_header(spl_image, (const struct image_header *)spl_nor_get_uboot_base()); if (ret) From 4d81755272c19f0bc47b829deaa752291bcdaba6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 23 Sep 2019 10:12:31 +0000 Subject: [PATCH 163/190] misc: imx8: add more scfw api Add more scfw api for clk/partition/seco usage The api will be used by ccf/partition/secure boot. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8/sci/rpc.h | 24 + arch/arm/include/asm/arch-imx8/sci/sci.h | 42 +- .../include/asm/arch-imx8/sci/svc/seco/api.h | 37 ++ drivers/misc/imx8/scu_api.c | 522 +++++++++++++++++- 4 files changed, 614 insertions(+), 11 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 0dfd89ad11a..8e1e9bbf437 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -142,6 +142,7 @@ struct sc_rpc_msg_s { #define RM_FUNC_SET_MASTER_SID 11U #define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U #define RM_FUNC_IS_RESOURCE_OWNED 13U +#define RM_FUNC_GET_RESOURCE_OWNER 33U #define RM_FUNC_IS_RESOURCE_MASTER 14U #define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U #define RM_FUNC_GET_RESOURCE_INFO 16U @@ -158,4 +159,27 @@ struct sc_rpc_msg_s { #define RM_FUNC_IS_PAD_OWNED 25U #define RM_FUNC_DUMP 27U +/* SECO RPC */ +#define SECO_FUNC_UNKNOWN 0 +#define SECO_FUNC_IMAGE_LOAD 1U +#define SECO_FUNC_AUTHENTICATE 2U +#define SECO_FUNC_FORWARD_LIFECYCLE 3U +#define SECO_FUNC_RETURN_LIFECYCLE 4U +#define SECO_FUNC_COMMIT 5U +#define SECO_FUNC_ATTEST_MODE 6U +#define SECO_FUNC_ATTEST 7U +#define SECO_FUNC_GET_ATTEST_PKEY 8U +#define SECO_FUNC_GET_ATTEST_SIGN 9U +#define SECO_FUNC_ATTEST_VERIFY 10U +#define SECO_FUNC_GEN_KEY_BLOB 11U +#define SECO_FUNC_LOAD_KEY 12U +#define SECO_FUNC_GET_MP_KEY 13U +#define SECO_FUNC_UPDATE_MPMR 14U +#define SECO_FUNC_GET_MP_SIGN 15U +#define SECO_FUNC_BUILD_INFO 16U +#define SECO_FUNC_CHIP_INFO 17U +#define SECO_FUNC_ENABLE_DEBUG 18U +#define SECO_FUNC_GET_EVENT 19U +#define SECO_FUNC_FUSE_WRITE 20U + #endif /* SC_RPC_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index 55b392fde15..14ee6f999ba 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -58,14 +59,23 @@ static inline int sc_err_to_linux(sc_err_t err) /* PM API*/ int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t mode); +int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode); int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); +int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clk_parent_t parent); +int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address); +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); /* MISC API */ +int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, u32 val); int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val); void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); @@ -77,12 +87,40 @@ int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, /* RM API */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); +int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end); +int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end); sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); -int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); -sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); +int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent); +int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); +int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); +int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); +int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); +int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); +int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt); /* PAD API */ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); + +/* SMMU API */ +int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); + +/* SECO API */ +int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, + sc_faddr_t addr); +int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); +int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, + u32 *uid_h); +void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); +int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); +int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, + sc_faddr_t export_addr, u16 max_size); + #endif diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h new file mode 100644 index 00000000000..3ed05842d99 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef SC_SECO_API_H +#define SC_SECO_API_H + +/* Includes */ + +#include + +/* Defines */ +#define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_SECO_VERIFY_IMAGE 1U /* Verify image */ +#define SC_SECO_REL_CONTAINER 2U /* Release container */ +#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ +#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ +#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ + +#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ +#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ +#define SC_SECO_RNG_STAT_READY 2U /* Initialized */ + +/* Types */ + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef u8 sc_seco_auth_cmd_t; + +/*! + * This type is used to return the RNG initialization status. + */ +typedef u32 sc_seco_rng_stat_t; + +#endif /* SC_SECO_API_H */ diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 000a31f1b7b..b2fdeef13ab 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define B2U8(X) (((X) != SC_FALSE) ? (u8)(0x01U) : (u8)(0x00U)) + /* CLK and PM */ int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) @@ -93,6 +95,30 @@ int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, return ret; } +int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent) +{ + struct udevice *dev = gd->arch.scu_dev; + int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (u8)PM_FUNC_SET_CLOCK_PARENT; + RPC_U16(&msg, 0U) = (u16)resource; + RPC_U8(&msg, 2U) = (u8)clk; + RPC_U8(&msg, 3U) = (u8)parent; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: resource:%d clk:%d: parent clk: %d, res:%d\n", + __func__, resource, clk, parent, RPC_R8(&msg)); + + return ret; +} + int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t mode) { @@ -173,6 +199,33 @@ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val) } /* MISC */ +int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, u32 val) +{ + struct udevice *dev = gd->arch.scu_dev; + int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; + int ret; + + if (!dev) + hang(); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (u8)MISC_FUNC_SET_CONTROL; + RPC_U32(&msg, 0U) = (u32)ctrl; + RPC_U32(&msg, 4U) = (u32)val; + RPC_U16(&msg, 8U) = (u16)resource; + RPC_SIZE(&msg) = 4U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: ctrl:%d resource:%d: res:%d\n", + __func__, ctrl, resource, RPC_R8(&msg)); + + return ret; +} + int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val) { @@ -202,6 +255,28 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, return ret; } +int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_SET_MASTER_SID; + RPC_U16(&msg, 0U) = (u16)resource; + RPC_U16(&msg, 2U) = (u16)sid; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: resource:%d sid:%d: res:%d\n", + __func__, resource, sid, RPC_R8(&msg)); + + return ret; +} + void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev) { struct udevice *dev = gd->arch.scu_dev; @@ -359,24 +434,60 @@ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) return (sc_bool_t)result; } -int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) +int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end) { struct udevice *dev = gd->arch.scu_dev; - struct sc_rpc_msg_s msg; int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; int ret; + if (!dev) + hang(); + RPC_VER(&msg) = SC_RPC_VERSION; - RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; - RPC_FUNC(&msg) = (u8)RM_FUNC_SET_MASTER_SID; - RPC_U16(&msg, 0U) = (u16)resource; - RPC_U16(&msg, 2U) = (u16)sid; - RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = (u8)(RM_FUNC_FIND_MEMREG); + RPC_U32(&msg, 0U) = (u32)(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = (u32)(addr_start); + RPC_U32(&msg, 8U) = (u32)(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = (u32)(addr_end); + RPC_SIZE(&msg) = 5U; ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); if (ret) - printf("%s: resource:%d sid:%d: res:%d\n", - __func__, resource, sid, RPC_R8(&msg)); + printf("%s: start:0x%llx, end:0x%llx res:%d\n", __func__, addr_start, addr_end, RPC_R8(&msg)); + + if (mr) + *mr = RPC_U8(&msg, 0U); + + return ret; +} + +int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + struct udevice *dev = gd->arch.scu_dev; + int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; + int ret; + + if (!dev) + hang(); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = (u8)(RM_FUNC_SET_MEMREG_PERMISSIONS); + RPC_U8(&msg, 0U) = (u8)(mr); + RPC_U8(&msg, 1U) = (u8)(pt); + RPC_U8(&msg, 2U) = (u8)(perm); + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: mr:%u, pt:%u, perm:%u, res:%d\n", __func__, + mr, pt, perm, RPC_R8(&msg)); + } return ret; } @@ -442,3 +553,396 @@ sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) return !!result; } + +int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_PARTITION_ALLOC; + RPC_U8(&msg, 0U) = B2U8(secure); + RPC_U8(&msg, 1U) = B2U8(isolated); + RPC_U8(&msg, 2U) = B2U8(restricted); + RPC_U8(&msg, 3U) = B2U8(grant); + RPC_U8(&msg, 4U) = B2U8(coherent); + RPC_SIZE(&msg) = 3U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: secure:%u isolated:%u restricted:%u grant:%u coherent:%u res:%d\n", + __func__, secure, isolated, restricted, grant, coherent, + RPC_R8(&msg)); + } + + if (pt) + *pt = RPC_U8(&msg, 0U); + + return ret; +} + +int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_PARTITION_FREE; + RPC_U8(&msg, 0U) = (u8)pt; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: pt:%u res:%d\n", + __func__, pt, RPC_R8(&msg)); + } + + return ret; +} + +int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_GET_PARTITION; + RPC_SIZE(&msg) = 1U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + if (pt) + *pt = RPC_U8(&msg, 0U); + + return ret; +} + +int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_SET_PARENT; + RPC_U8(&msg, 0U) = (u8)pt; + RPC_U8(&msg, 1U) = (u8)pt_parent; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: pt:%u, pt_parent:%u, res:%d\n", + __func__, pt, pt_parent, RPC_R8(&msg)); + } + + return ret; +} + +int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_ASSIGN_RESOURCE; + RPC_U16(&msg, 0U) = (u16)resource; + RPC_U8(&msg, 2U) = (u8)pt; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: pt:%u, resource:%u, res:%d\n", + __func__, pt, resource, RPC_R8(&msg)); + } + + return ret; +} + +int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_ASSIGN_PAD; + RPC_U16(&msg, 0U) = (u16)pad; + RPC_U8(&msg, 2U) = (u8)pt; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: pt:%u, pad:%u, res:%d\n", + __func__, pt, pad, RPC_R8(&msg)); + } + + return ret; +} + +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + u8 result; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_IS_PAD_OWNED; + RPC_U8(&msg, 0U) = (u8)pad; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + result = RPC_R8(&msg); + if (result != 0 && result != 1) { + printf("%s: pad:%d res:%d\n", __func__, pad, RPC_R8(&msg)); + if (ret) { + printf("%s: pad:%d res:%d\n", __func__, + pad, RPC_R8(&msg)); + } + } + + return !!result; +} + +int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; + RPC_FUNC(&msg) = (u8)RM_FUNC_GET_RESOURCE_OWNER; + RPC_U16(&msg, 0U) = (u16)resource; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (pt) + *pt = RPC_U8(&msg, 0U); + + return ret; +} + +int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (u8)PM_FUNC_CPU_START; + RPC_U32(&msg, 0U) = (u32)(address >> 32ULL); + RPC_U32(&msg, 4U) = (u32)address; + RPC_U16(&msg, 8U) = (u16)resource; + RPC_U8(&msg, 10U) = B2U8(enable); + RPC_SIZE(&msg) = 4U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: resource:%d address:0x%llx: res:%d\n", + __func__, resource, address, RPC_R8(&msg)); + } + + return ret; +} + +int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (u8)PM_FUNC_GET_RESOURCE_POWER_MODE; + RPC_U16(&msg, 0U) = (u16)resource; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: resource:%d: res:%d\n", + __func__, resource, RPC_R8(&msg)); + } + + if (mode) + *mode = RPC_U8(&msg, 0U); + + return ret; +} + +int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, + sc_faddr_t addr) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_SECO; + RPC_FUNC(&msg) = (u8)SECO_FUNC_AUTHENTICATE; + RPC_U32(&msg, 0U) = (u32)(addr >> 32ULL); + RPC_U32(&msg, 4U) = (u32)addr; + RPC_U8(&msg, 8U) = (u8)cmd; + RPC_SIZE(&msg) = 4U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + return ret; +} + +int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_SECO; + RPC_FUNC(&msg) = (u8)SECO_FUNC_FORWARD_LIFECYCLE; + RPC_U32(&msg, 0U) = (u32)change; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: change:%u, res:%d\n", __func__, + change, RPC_R8(&msg)); + } + + return ret; +} + +int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, + u32 *uid_h) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_SECO; + RPC_FUNC(&msg) = (u8)SECO_FUNC_CHIP_INFO; + RPC_SIZE(&msg) = 1U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + if (uid_l) + *uid_l = RPC_U32(&msg, 0U); + + if (uid_h) + *uid_h = RPC_U32(&msg, 4U); + + if (lc) + *lc = RPC_U16(&msg, 8U); + + if (monotonic) + *monotonic = RPC_U16(&msg, 10U); + + return ret; +} + +void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = (u8)(SECO_FUNC_BUILD_INFO); + RPC_SIZE(&msg) = 1U; + + misc_call(dev, SC_FALSE, &msg, size, &msg, size); + + if (version) + *version = RPC_U32(&msg, 0U); + + if (commit) + *commit = RPC_U32(&msg, 4U); +} + +int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_SECO; + RPC_FUNC(&msg) = (u8)SECO_FUNC_GET_EVENT; + RPC_U8(&msg, 0U) = (u8)idx; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: idx: %u, res:%d\n", __func__, idx, RPC_R8(&msg)); + + if (event) + *event = RPC_U32(&msg, 0U); + + return ret; +} + +int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, + sc_faddr_t export_addr, u16 max_size) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_SECO; + RPC_FUNC(&msg) = (u8)SECO_FUNC_GEN_KEY_BLOB; + RPC_U32(&msg, 0U) = (u32)(load_addr >> 32ULL); + RPC_U32(&msg, 4U) = (u32)load_addr; + RPC_U32(&msg, 8U) = (u32)(export_addr >> 32ULL); + RPC_U32(&msg, 12U) = (u32)export_addr; + RPC_U32(&msg, 16U) = (u32)id; + RPC_U16(&msg, 20U) = (u16)max_size; + RPC_SIZE(&msg) = 7U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) { + printf("%s: id: %u, load_addr 0x%llx, export_addr 0x%llx, res:%d\n", + __func__, id, load_addr, export_addr, RPC_R8(&msg)); + } + + return ret; +} From 848ba639dcf7c3c49462a9a7ae26775ec1e19a82 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Fri, 23 Aug 2019 20:00:48 +0300 Subject: [PATCH 164/190] colibri_imx6/imx7/imx8x: use distroboot by default Use distro_bootcmd as defauult bootcmd instead of legacy wrappers. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- include/configs/colibri-imx8x.h | 1 + include/configs/colibri_imx6.h | 4 ++-- include/configs/colibri_imx7.h | 5 +++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 69a876fee35..ab98da6da39 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -79,6 +79,7 @@ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ + "boot_file=Image\0" \ "console=ttyLP3 earlycon\0" \ "fdt_addr=0x83000000\0" \ "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index fa4dc498f58..69bf8225fe5 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -91,6 +91,7 @@ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) @@ -167,8 +168,7 @@ #define FDT_FILE "imx6dl-colibri-eval-v3.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ - "setenv fdtfile ${fdt_file}; run distro_bootcmd ; " \ + "bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd; " \ "usb start ; " \ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ "boot_file=zImage\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 4677e09b475..ade4df5ad8a 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -106,7 +106,8 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x81000000\0" \ - "ramdisk_addr_r=0x82100000\0" + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x82500000\0" #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) #define SD_BOOTDEV 0 @@ -157,7 +158,7 @@ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) -#define CONFIG_BOOTCOMMAND "run emmcboot ; echo ; echo emmcboot failed ; " \ +#define CONFIG_BOOTCOMMAND \ "setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;" #define MODULE_EXTRA_ENV_SETTINGS \ "variant=-emmc\0" \ From d73c520327b2ae337efc0d557fd45a1b7010da17 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Fri, 23 Aug 2019 20:00:49 +0300 Subject: [PATCH 165/190] apalis_imx6: use distroboot by default Use distro_bootcmd as default bootcmd instead of legacy wrappers. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- include/configs/apalis_imx6.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index c3bc3943f40..5139b01ab3a 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -101,6 +101,7 @@ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ @@ -183,8 +184,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ - "setenv fdtfile ${fdt_file}; run distro_bootcmd ; " \ + "bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd ; " \ "usb start ; " \ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ "boot_file=zImage\0" \ From a919b6ba371b5dbc47e761ab965d638b0d624641 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 23 Aug 2019 18:19:48 +0200 Subject: [PATCH 166/190] imx: pcl063: add nand boot support Booting from NAND needs nandbcb and nand boot device selection Signed-off-by: Parthiban Nallathambi Reviewed-by: Peng Fan --- board/phytec/pcl063/spl.c | 3 +++ configs/phycore_pcl063_defconfig | 1 + 2 files changed, 4 insertions(+) diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index 6d4c8279188..358156bfbcd 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -197,6 +197,9 @@ void board_boot_order(u32 *spl_boot_list) case IMX6_BMODE_EMMC: boot_dev = BOOT_DEVICE_MMC2; break; + case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX: + boot_dev = BOOT_DEVICE_NAND; + break; default: /* Default - BOOT_DEVICE_MMC1 */ printf("Wrong board boot order\n"); diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index be16f484d56..4fdcf67efe2 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NANDBCB=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)" CONFIG_CMD_UBI=y From 84d5e72ffbbb75826b1592a3474ce9b7b44d14cd Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 23 Aug 2019 18:35:08 +0200 Subject: [PATCH 167/190] imx: remove board specific boot order from spl boot order was added to handle both SD and eMMC. But commit 14d319b1 introduced to handle both eMMC and SD globally. Signed-off-by: Parthiban Nallathambi Reviewed-by: Peng Fan --- board/phytec/pcl063/spl.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index 358156bfbcd..b5e080c0723 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -183,31 +183,6 @@ int board_mmc_init(bd_t *bis) return 0; } -void board_boot_order(u32 *spl_boot_list) -{ - u32 bmode = imx6_src_get_boot_mode(); - u8 boot_dev = BOOT_DEVICE_MMC1; - - switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { - case IMX6_BMODE_SD: - case IMX6_BMODE_ESD: - boot_dev = BOOT_DEVICE_MMC1; - break; - case IMX6_BMODE_MMC: - case IMX6_BMODE_EMMC: - boot_dev = BOOT_DEVICE_MMC2; - break; - case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX: - boot_dev = BOOT_DEVICE_NAND; - break; - default: - /* Default - BOOT_DEVICE_MMC1 */ - printf("Wrong board boot order\n"); - break; - } - - spl_boot_list[0] = boot_dev; -} #endif /* CONFIG_FSL_ESDHC_IMX */ void board_init_f(ulong dummy) From 921bb8641d15f8a2570d43321e5c74ff65aa28f3 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 23 Aug 2019 18:35:09 +0200 Subject: [PATCH 168/190] imx: initialize fec only when enabled board early initialize fec ethernet controller pinmux only when FEC is enabled Signed-off-by: Parthiban Nallathambi Reviewed-by: Peng Fan --- board/phytec/pcl063/pcl063.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c index f8cbd1c11e8..96dd9e38f37 100644 --- a/board/phytec/pcl063/pcl063.c +++ b/board/phytec/pcl063/pcl063.c @@ -178,7 +178,9 @@ int board_phy_config(struct phy_device *phydev) int board_early_init_f(void) { setup_iomux_uart(); +#ifdef CONFIG_FEC_MXC setup_iomux_fec(); +#endif return 0; } From 4ee0ff1268d3302a83da97af2a61869f672be473 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 23 Aug 2019 18:35:10 +0200 Subject: [PATCH 169/190] imx: nandbcb: include long help only when enabled conditionally include long help text when enabled Signed-off-by: Parthiban Nallathambi Reviewed-by: Peng Fan --- arch/arm/mach-imx/cmd_nandbcb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index 065b814b2e3..7811c61d220 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -359,9 +359,11 @@ usage: return CMD_RET_USAGE; } +#ifdef CONFIG_SYS_LONGHELP static char nandbcb_help_text[] = "update addr off|partition len - update 'len' bytes starting at\n" " 'off|part' to memory address 'addr', skipping bad blocks"; +#endif U_BOOT_CMD(nandbcb, 5, 1, do_nandbcb, "i.MX6 Nand BCB", From 7949576664ac8fe8c0da08fcd8c611b9616719f1 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 14 Aug 2019 11:31:27 +0000 Subject: [PATCH 170/190] spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller is updated to have TDH field in FLSHCR register. According to reference manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX DDR delay logic won't be enabled. Another issue in DDR mode is the MCR register will be overwritten in every read/write/erase operation. This causes DDR_EN been cleared while TDH=1, then no clk2x output for TX data shift and all operations will fail. Signed-off-by: Ye Li --- drivers/spi/fsl_qspi.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 41abe1996f2..e877d99bb05 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -399,7 +399,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr); /* Read out the data directly from the AHB buffer. */ @@ -429,6 +429,14 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) reg |= BIT(29); qspi_write32(priv->flags, ®s->mcr, reg); + + /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc + * These two bits are reserved on other platforms + */ + reg = qspi_read32(priv->flags, ®s->flshcr); + reg &= ~(BIT(17)); + reg |= BIT(16); + qspi_write32(priv->flags, ®s->flshcr, reg); } /* @@ -482,7 +490,7 @@ static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); @@ -527,7 +535,7 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); @@ -573,7 +581,7 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); to_or_from = priv->sf_addr + priv->cur_amba_base; @@ -625,7 +633,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); status_reg = 0; @@ -700,7 +708,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); @@ -737,7 +745,7 @@ static void qspi_op_erase(struct fsl_qspi_priv *priv) mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); to_or_from = priv->sf_addr + priv->cur_amba_base; @@ -867,7 +875,6 @@ static int fsl_qspi_child_pre_probe(struct udevice *dev) static int fsl_qspi_probe(struct udevice *bus) { - u32 mcr_val; u32 amba_size_per_chip; struct fsl_qspi_platdata *plat = dev_get_platdata(bus); struct fsl_qspi_priv *priv = dev_get_priv(bus); @@ -900,15 +907,9 @@ static int fsl_qspi_probe(struct udevice *bus) return ret; } - mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); - - /* Set endianness to LE for i.mx */ - if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) - mcr_val = QSPI_MCR_END_CFD_LE; - qspi_write32(priv->flags, &priv->regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | - (mcr_val & QSPI_MCR_END_CFD_MASK)); + QSPI_MCR_END_CFD_LE); qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); From b866b9278a3b87e7f70f026785c002b109258022 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 14 Aug 2019 11:31:31 +0000 Subject: [PATCH 171/190] spi: fsl_qspi: Update write data size for page program LUT The write data size can be overwritten by writing to the IDATSZ field of IPCR register. Since the driver always updates the IDATSZ in page program operation. Set the LUT data size to 0 to align the codes with iMX. Signed-off-by: Ye Li --- drivers/spi/fsl_qspi.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e877d99bb05..57065698341 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -273,19 +273,9 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) - /* - * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. - * So, Use IDATSZ in IPCR to determine the size and here set 0. - */ + /* Use IDATSZ in IPCR to determine the size and here set 0. */ qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); -#else - qspi_write32(priv->flags, ®s->lut[lut_base + 1], - OPRND0(TX_BUFFER_SIZE) | - PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); -#endif qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); From ce7575a86d7135e11542fac2eee642acdb291266 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 14 Aug 2019 11:31:36 +0000 Subject: [PATCH 172/190] spi: fsl_qspi: Update to use driver data Add the driver data for each compatible string. So we can remove the SOC config and use driver data instead. Signed-off-by: Ye Li --- drivers/spi/fsl_qspi.c | 113 ++++++++++++++++++++++++++++------------- 1 file changed, 79 insertions(+), 34 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 57065698341..d759e98d899 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -19,14 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define RX_BUFFER_SIZE 0x80 -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) -#define TX_BUFFER_SIZE 0x200 -#else -#define TX_BUFFER_SIZE 0x40 -#endif - #define OFFSET_BITS_MASK GENMASK(23, 0) #define FLASH_STATUS_WEL 0x02 @@ -85,6 +77,23 @@ DECLARE_GLOBAL_DATA_PTR; /* QSPI max chipselect signals number */ #define FSL_QSPI_MAX_CHIPSELECT_NUM 4 +/* Controller needs driver to swap endian */ +#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) + +enum fsl_qspi_devtype { + FSL_QUADSPI_VYBRID, + FSL_QUADSPI_IMX6SX, + FSL_QUADSPI_IMX6UL_7D, +}; + +struct fsl_qspi_devtype_data { + enum fsl_qspi_devtype devtype; + u32 rxfifo; + u32 txfifo; + u32 ahb_buf_size; + u32 driver_data; +}; + /** * struct fsl_qspi_platdata - platform data for Freescale QSPI * @@ -133,8 +142,32 @@ struct fsl_qspi_priv { u32 flash_num; u32 num_chipselect; struct fsl_qspi_regs *regs; + struct fsl_qspi_devtype_data *devtype_data; }; +static const struct fsl_qspi_devtype_data vybrid_data = { + .devtype = FSL_QUADSPI_VYBRID, + .rxfifo = 128, + .txfifo = 64, + .ahb_buf_size = 1024, + .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN, +}; + +static const struct fsl_qspi_devtype_data imx6sx_data = { + .devtype = FSL_QUADSPI_IMX6SX, + .rxfifo = 128, + .txfifo = 512, + .ahb_buf_size = 1024, + .driver_data = 0, +}; + +static const struct fsl_qspi_devtype_data imx6ul_7d_data = { + .devtype = FSL_QUADSPI_IMX6UL_7D, + .rxfifo = 128, + .txfifo = 512, + .ahb_buf_size = 1024, + .driver_data = 0, +}; static u32 qspi_read32(u32 flags, u32 *addr) { @@ -162,13 +195,12 @@ static inline int is_controller_busy(const struct fsl_qspi_priv *priv) /* QSPI support swapping the flash read/write data * in hardware for LS102xA, but not for VF610 */ -static inline u32 qspi_endian_xchg(u32 data) +static inline u32 qspi_endian_xchg(struct fsl_qspi_priv *priv, u32 data) { -#ifdef CONFIG_VF610 - return swab32(data); -#else - return data; -#endif + if (priv->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN) + return swab32(data); + else + return data; } static void qspi_set_lut(struct fsl_qspi_priv *priv) @@ -210,7 +242,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) #endif qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | - OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | + OPRND1(priv->devtype_data->rxfifo) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); @@ -417,7 +449,6 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) reg |= QSPI_MCR_DDR_EN_MASK; /* Enable bit 29 for imx6sx */ reg |= BIT(29); - qspi_write32(priv->flags, ®s->mcr, reg); /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc @@ -451,7 +482,7 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | - (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); + ((priv->devtype_data->ahb_buf_size >> 3) << QSPI_BUF3CR_ADATSZ_SHIFT)); /* We only use the buffer3 */ qspi_write32(priv->flags, ®s->buf0ind, 0); @@ -503,7 +534,7 @@ static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) reg = qspi_read32(priv->flags, ®s->rbsr); if (reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, ®s->rbdr[0]); - data = qspi_endian_xchg(data); + data = qspi_endian_xchg(priv, data); memcpy(rxbuf, &data, len); qspi_write32(priv->flags, ®s->mcr, qspi_read32(priv->flags, ®s->mcr) | @@ -536,13 +567,13 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) ; i = 0; - while ((RX_BUFFER_SIZE >= len) && (len > 0)) { + while ((priv->devtype_data->rxfifo >= len) && (len > 0)) { WATCHDOG_RESET(); rbsr_reg = qspi_read32(priv->flags, ®s->rbsr); if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, ®s->rbdr[i]); - data = qspi_endian_xchg(data); + data = qspi_endian_xchg(priv, data); size = (len < 4) ? len : 4; memcpy(rxbuf, &data, size); len -= size; @@ -581,8 +612,8 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) qspi_write32(priv->flags, ®s->sfar, to_or_from); - size = (len > RX_BUFFER_SIZE) ? - RX_BUFFER_SIZE : len; + size = (len > priv->devtype_data->rxfifo) ? + priv->devtype_data->rxfifo : len; qspi_write32(priv->flags, ®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | @@ -594,9 +625,9 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) len -= size; i = 0; - while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + while ((priv->devtype_data->rxfifo >= size) && (size > 0)) { data = qspi_read32(priv->flags, ®s->rbdr[i]); - data = qspi_endian_xchg(data); + data = qspi_endian_xchg(priv, data); if (size < 4) memcpy(rxbuf, &data, size); else @@ -643,7 +674,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) reg = qspi_read32(priv->flags, ®s->rbsr); if (reg & QSPI_RBSR_RDBFL_MASK) { status_reg = qspi_read32(priv->flags, ®s->rbdr[0]); - status_reg = qspi_endian_xchg(status_reg); + status_reg = qspi_endian_xchg(priv, status_reg); } qspi_write32(priv->flags, ®s->mcr, qspi_read32(priv->flags, ®s->mcr) | @@ -665,8 +696,8 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) qspi_write32(priv->flags, ®s->sfar, to_or_from); - tx_size = (len > TX_BUFFER_SIZE) ? - TX_BUFFER_SIZE : len; + tx_size = (len > priv->devtype_data->txfifo) ? + priv->devtype_data->txfifo : len; size = tx_size / 16; /* @@ -677,7 +708,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) size++; for (i = 0; i < size * 4; i++) { memcpy(&data, txbuf, 4); - data = qspi_endian_xchg(data); + data = qspi_endian_xchg(priv, data); qspi_write32(priv->flags, ®s->tbdr, data); txbuf += 4; } @@ -714,7 +745,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) reg = qspi_read32(priv->flags, ®s->rbsr); if (reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, ®s->rbdr[0]); - data = qspi_endian_xchg(data); + data = qspi_endian_xchg(priv, data); memcpy(rxbuf, &data, len); qspi_write32(priv->flags, ®s->mcr, qspi_read32(priv->flags, ®s->mcr) | @@ -857,8 +888,9 @@ void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits) static int fsl_qspi_child_pre_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); + struct fsl_qspi_priv *priv = dev_get_priv(dev_get_parent(dev)); - slave->max_write_size = TX_BUFFER_SIZE; + slave->max_write_size = priv->devtype_data->txfifo; return 0; } @@ -889,6 +921,19 @@ static int fsl_qspi_probe(struct udevice *bus) priv->flash_num = plat->flash_num; priv->num_chipselect = plat->num_chipselect; + priv->devtype_data = (struct fsl_qspi_devtype_data *)dev_get_driver_data(bus); + if (!priv->devtype_data) { + printf("ERROR : No devtype_data found\n"); + return -ENODEV; + } + + debug("devtype=%d, txfifo=%d, rxfifo=%d, ahb=%d, data=0x%x\n", + priv->devtype_data->devtype, + priv->devtype_data->txfifo, + priv->devtype_data->rxfifo, + priv->devtype_data->ahb_buf_size, + priv->devtype_data->driver_data); + /* make sure controller is not busy anywhere */ ret = is_controller_busy(priv); @@ -1095,10 +1140,10 @@ static const struct dm_spi_ops fsl_qspi_ops = { }; static const struct udevice_id fsl_qspi_ids[] = { - { .compatible = "fsl,vf610-qspi" }, - { .compatible = "fsl,imx6sx-qspi" }, - { .compatible = "fsl,imx6ul-qspi" }, - { .compatible = "fsl,imx7d-qspi" }, + { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data }, + { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data }, + { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data }, + { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data }, { } }; From 9699fb4de55be35ac607cecbbd10c62a52cd7cfe Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 14 Aug 2019 11:31:40 +0000 Subject: [PATCH 173/190] spi: fsl_qspi: Add support for QSPI on iMX7ULP Add the compatible string and driver data for iMX7ULP platform Signed-off-by: Ye Li --- drivers/spi/fsl_qspi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index d759e98d899..8e2a09df366 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -84,6 +84,7 @@ enum fsl_qspi_devtype { FSL_QUADSPI_VYBRID, FSL_QUADSPI_IMX6SX, FSL_QUADSPI_IMX6UL_7D, + FSL_QUADSPI_IMX7ULP, }; struct fsl_qspi_devtype_data { @@ -169,6 +170,14 @@ static const struct fsl_qspi_devtype_data imx6ul_7d_data = { .driver_data = 0, }; +static const struct fsl_qspi_devtype_data imx7ulp_data = { + .devtype = FSL_QUADSPI_IMX7ULP, + .rxfifo = 64, + .txfifo = 64, + .ahb_buf_size = 128, + .driver_data = 0, +}; + static u32 qspi_read32(u32 flags, u32 *addr) { return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? @@ -1144,6 +1153,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data }, { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data }, { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data }, + { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data }, { } }; From ca729cd16cca26a8d8a1746e3080937206aca615 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 8 Aug 2019 09:59:02 +0000 Subject: [PATCH 174/190] ddr: imx8m: Fix ddr4 driver build issue Since the parameter of dram_pll_init is changed, update to use new. Also remove non-existed header file. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/ddr4_init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c index 031cdc57e16..b8aa104536c 100644 --- a/drivers/ddr/imx/imx8m/ddr4_init.c +++ b/drivers/ddr/imx/imx8m/ddr4_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #include void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) @@ -41,7 +40,7 @@ void ddr_init(struct dram_timing_info *dram_timing) CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); - dram_pll_init(DRAM_PLL_OUT_600M); + dram_pll_init(MHZ(600)); reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ From 7b14cc991ba85d2b035479177cc1391ed729abd3 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Thu, 8 Aug 2019 09:59:05 +0000 Subject: [PATCH 175/190] imx8mq: Update the ddrc QoS setting for B1 chip Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping Reviewed-by: Ye Li Tested-by: Robby Cai --- board/freescale/imx8mq_evk/lpddr4_timing.c | 16 ++++++++++------ drivers/ddr/imx/imx8m/lpddr4_init.c | 5 ++++- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c index f7ea799343b..46bc7f8591c 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -72,8 +72,10 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_SCHED(0), 0x29511505 }, { DDRC_SCHED1(0), 0x0000002c }, { DDRC_PERFHPR1(0), 0x5900575b }, - { DDRC_PERFLPR1(0), 0x00000009 }, - { DDRC_PERFWR1(0), 0x02005574 }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, { DDRC_DBG0(0), 0x00000016 }, { DDRC_DBG1(0), 0x00000000 }, { DDRC_DBGCMD(0), 0x00000000 }, @@ -83,10 +85,12 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_PCFGR_0(0), 0x000010f3 }, { DDRC_PCFGW_0(0), 0x000072ff }, { DDRC_PCTRL_0(0), 0x00000001 }, - { DDRC_PCFGQOS0_0(0), 0x01110d00 }, - { DDRC_PCFGQOS1_0(0), 0x00620790 }, - { DDRC_PCFGWQOS0_0(0), 0x00100001 }, - { DDRC_PCFGWQOS1_0(0), 0x0000041f }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, /* Frequency 1: 400mbps */ { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c index a4bc1de8eb6..0f46ca02b6c 100644 --- a/drivers/ddr/imx/imx8m/lpddr4_init.c +++ b/drivers/ddr/imx/imx8m/lpddr4_init.c @@ -54,7 +54,10 @@ void ddr_init(struct dram_timing_info *dram_timing) reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ debug("DDRINFO: cfg clk\n"); - dram_pll_init(MHZ(750)); + if (is_imx8mq()) + dram_pll_init(MHZ(800)); + else + dram_pll_init(MHZ(750)); /* * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, From 825ab6b406cba74ae63a1e3373c2f0b62b855f08 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 8 Aug 2019 09:59:08 +0000 Subject: [PATCH 176/190] driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/Kconfig | 6 + drivers/ddr/imx/imx8m/Makefile | 4 +- drivers/ddr/imx/imx8m/ddr4_init.c | 112 ---------------- drivers/ddr/imx/imx8m/ddr_init.c | 168 +++++++++++++++++++++++ drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 + drivers/ddr/imx/imx8m/helper.c | 10 +- drivers/ddr/imx/imx8m/lpddr4_init.c | 191 --------------------------- 7 files changed, 184 insertions(+), 311 deletions(-) delete mode 100644 drivers/ddr/imx/imx8m/ddr4_init.c create mode 100644 drivers/ddr/imx/imx8m/ddr_init.c delete mode 100644 drivers/ddr/imx/imx8m/lpddr4_init.c diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig index a83b0f43d78..5bf61eb2587 100644 --- a/drivers/ddr/imx/imx8m/Kconfig +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -16,6 +16,12 @@ config IMX8M_DDR4 help Select the i.MX8M DDR4 driver support on i.MX8M SOC. +config IMX8M_DDR3L + bool "imx8m ddr3l" + select IMX8M_DRAM + help + Select the i.MX8M DDR3L driver support on i.MX8M SOC. + config SAVED_DRAM_TIMING_BASE hex "Define the base address for saved dram timing" help diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile index 64f9ab20e6d..bd9bcb8d53b 100644 --- a/drivers/ddr/imx/imx8m/Makefile +++ b/drivers/ddr/imx/imx8m/Makefile @@ -5,7 +5,5 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o -obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o endif diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c deleted file mode 100644 index b8aa104536c..00000000000 --- a/drivers/ddr/imx/imx8m/ddr4_init.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include -#include -#include -#include - -void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) -{ - int i = 0; - - for (i = 0; i < num; i++) { - reg32_write(ddrc_cfg->reg, ddrc_cfg->val); - ddrc_cfg++; - } -} - -void ddr_init(struct dram_timing_info *dram_timing) -{ - volatile unsigned int tmp_t; - /* - * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, - * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, - * [4]src_system_rst_b! - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); - /* deassert [4]src_system_rst_b! */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); - - /* - * change the clock source of dram_apb_clk_root - * to source 4 --800MHz/4 - */ - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(4) | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); - - dram_pll_init(MHZ(600)); - - reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ - - /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); - - reg32_write(DDRC_DBG1(0), 0x00000001); - reg32_write(DDRC_PWRCTL(0), 0x00000001); - - while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) - ; - - /* config the uMCTL2's registers */ - ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); - - reg32_write(DDRC_RFSHCTL3(0), 0x00000001); - /* RESET: DEASSERTED */ - /* RESET: +#include +#include +#include +#include +#include + +void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int tmp, initial_drate, target_freq; + + printf("DDRINFO: start DRAM init\n"); + + /* Step1: Follow the power up procedure */ + if (is_imx8mq()) { + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + } else { + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + } + + debug("DDRINFO: cfg clk\n"); + /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + initial_drate = dram_timing->fsp_msg[0].drate; + /* default to the frequency point 0 clock */ + ddrphy_init_set_dfi_clk(initial_drate); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + /* D-aasert the presetn */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Step2: Program the dwc_ddr_umctl2 registers */ + debug("DDRINFO: ddrc config start\n"); + ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + /* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + /* + * Step4: Disable auto-refreshes, self-refresh, powerdown, and + * assertion of dfi_dram_clk_disable by setting RFSHCTL3.dis_auto_refresh = 1, + * PWRCTL.powerdown_en = 0, and PWRCTL.selfref_en = 0, PWRCTL.en_dfi_dram_clk_disable = 0 + */ + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_RFSHCTL3(0), 0x0000001); + reg32_write(DDRC_PWRCTL(0), 0xa0); + + /* if ddr type is LPDDR4, do it */ + tmp = reg32_read(DDRC_MSTR(0)); + if (tmp & (0x1 << 5)) + reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* determine the initial boot frequency */ + target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3; + target_freq = (tmp & (0x1 << 29)) ? target_freq : 0x0; + + /* Step5: Set SWCT.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Set the default boot frequency point */ + clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8); + /* Step6: Set DFIMISC.dfi_init_complete_en to 0 */ + clrbits_le32(DDRC_DFIMISC(0), 0x1); + + /* Step7: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* + * Step8 ~ Step13: Start PHY initialization and training by + * accessing relevant PUB registers + */ + debug("DDRINFO:ddrphy config start\n"); + ddr_cfg_phy(dram_timing); + debug("DDRINFO: ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + printf("DDRINFO:ddrphy calibration done\n"); + + /* Step15: Set SWCTL.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Step16: Set DFIMISC.dfi_init_start to 1 */ + setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); + + /* Step17: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step18: Polling DFISTAT.dfi_init_complete = 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step19: Set SWCTL.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Step20: Set DFIMISC.dfi_init_start to 0 */ + clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); + + /* Step21: optional */ + + /* Step22: Set DFIMISC.dfi_init_complete_en to 1 */ + setbits_le32(DDRC_DFIMISC(0), 0x1); + + /* Step23: Set PWRCTL.selfref_sw to 0 */ + clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5)); + + /* Step24: Set SWCTL.sw_done to 1; need polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step25: Wait for dwc_ddr_umctl2 to move to normal operating mode by monitoring + * STAT.operating_mode signal */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* Step26: Set back register in Step4 to the original values if desired */ + reg32_write(DDRC_RFSHCTL3(0), 0x0000000); + /* enable selfref_en by default */ + setbits_le32(DDRC_PWRCTL(0), 0x1 << 3); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + printf("DDRINFO: ddrmix config done\n"); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 47325397647..e60503309eb 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -122,6 +122,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(400)); dram_disable_bypass(); break; + case 1066: + dram_pll_init(MHZ(266)); + dram_disable_bypass(); + break; case 667: dram_pll_init(MHZ(167)); dram_disable_bypass(); diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c index 3e605353ea1..b3e63834ca8 100644 --- a/drivers/ddr/imx/imx8m/helper.c +++ b/drivers/ddr/imx/imx8m/helper.c @@ -67,7 +67,7 @@ void ddr_load_train_firmware(enum fw_type type) i += 4; } - debug("check ddr4_pmu_train_imem code\n"); + debug("check ddr_pmu_train_imem code\n"); pr_from32 = imem_start; pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; for (i = 0x0; i < IMEM_LEN; ) { @@ -84,9 +84,9 @@ void ddr_load_train_firmware(enum fw_type type) i += 4; } if (error) - printf("check ddr4_pmu_train_imem code fail=%d\n", error); + printf("check ddr_pmu_train_imem code fail=%d\n", error); else - debug("check ddr4_pmu_train_imem code pass\n"); + debug("check ddr_pmu_train_imem code pass\n"); debug("check ddr4_pmu_train_dmem code\n"); pr_from32 = dmem_start; @@ -105,9 +105,9 @@ void ddr_load_train_firmware(enum fw_type type) } if (error) - printf("check ddr4_pmu_train_dmem code fail=%d", error); + printf("check ddr_pmu_train_dmem code fail=%d", error); else - debug("check ddr4_pmu_train_dmem code pass\n"); + debug("check ddr_pmu_train_dmem code pass\n"); } void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c deleted file mode 100644 index 0f46ca02b6c..00000000000 --- a/drivers/ddr/imx/imx8m/lpddr4_init.c +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* -* Copyright 2018 NXP -* -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) -{ - int i = 0; - - for (i = 0; i < num; i++) { - reg32_write(ddrc_cfg->reg, ddrc_cfg->val); - ddrc_cfg++; - } -} - -void ddr_init(struct dram_timing_info *dram_timing) -{ - unsigned int tmp; - - debug("DDRINFO: start lpddr4 ddr init\n"); - /* step 1: reset */ - if (is_imx8mq()) { - reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); - reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); - } else { - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); - } - - mdelay(100); - - debug("DDRINFO: reset done\n"); - /* - * change the clock source of dram_apb_clk_root: - * source 4 800MHz /4 = 200MHz - */ - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(4) | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); - - /* disable iso */ - reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ - - debug("DDRINFO: cfg clk\n"); - if (is_imx8mq()) - dram_pll_init(MHZ(800)); - else - dram_pll_init(MHZ(750)); - - /* - * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, - * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); - - /*step2 Configure uMCTL2's registers */ - debug("DDRINFO: ddrc config start\n"); - lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); - debug("DDRINFO: ddrc config done\n"); - - /* - * step3 de-assert all reset - * RESET: DEASSERTED - * RESET: for Port 0 DEASSERT(0)ED - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); - - reg32_write(DDRC_DBG1(0), 0x00000000); - /* step4 */ - /* [0]dis_auto_refresh=1 */ - reg32_write(DDRC_RFSHCTL3(0), 0x00000011); - - /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ - reg32_write(DDRC_PWRCTL(0), 0x000000a8); - - do { - tmp = reg32_read(DDRC_STAT(0)); - } while ((tmp & 0x33f) != 0x223); - - reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ - - /* step5 */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* step6 */ - tmp = reg32_read(DDRC_MSTR2(0)); - if (tmp == 0x2) - reg32_write(DDRC_DFIMISC(0), 0x00000210); - else if (tmp == 0x1) - reg32_write(DDRC_DFIMISC(0), 0x00000110); - else - reg32_write(DDRC_DFIMISC(0), 0x00000010); - - /* step7 [0]--1: disable quasi-dynamic programming */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - - /* step8 Configure LPDDR4 PHY's registers */ - debug("DDRINFO:ddrphy config start\n"); - ddr_cfg_phy(dram_timing); - debug("DDRINFO: ddrphy config done\n"); - - /* - * step14 CalBusy.0 =1, indicates the calibrator is actively - * calibrating. Wait Calibrating done. - */ - do { - tmp = reg32_read(DDRPHY_CalBusy(0)); - } while ((tmp & 0x1)); - - debug("DDRINFO:ddrphy calibration done\n"); - - /* step15 [0]--0: to enable quasi-dynamic programming */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* step16 */ - tmp = reg32_read(DDRC_MSTR2(0)); - if (tmp == 0x2) - reg32_write(DDRC_DFIMISC(0), 0x00000230); - else if (tmp == 0x1) - reg32_write(DDRC_DFIMISC(0), 0x00000130); - else - reg32_write(DDRC_DFIMISC(0), 0x00000030); - - /* step17 [0]--1: disable quasi-dynamic programming */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - /* step18 wait DFISTAT.dfi_init_complete to 1 */ - do { - tmp = reg32_read(DDRC_DFISTAT(0)); - } while ((tmp & 0x1) == 0x0); - - /* step19 */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* step20~22 */ - tmp = reg32_read(DDRC_MSTR2(0)); - if (tmp == 0x2) { - reg32_write(DDRC_DFIMISC(0), 0x00000210); - /* set DFIMISC.dfi_init_complete_en again */ - reg32_write(DDRC_DFIMISC(0), 0x00000211); - } else if (tmp == 0x1) { - reg32_write(DDRC_DFIMISC(0), 0x00000110); - /* set DFIMISC.dfi_init_complete_en again */ - reg32_write(DDRC_DFIMISC(0), 0x00000111); - } else { - /* clear DFIMISC.dfi_init_complete_en */ - reg32_write(DDRC_DFIMISC(0), 0x00000010); - /* set DFIMISC.dfi_init_complete_en again */ - reg32_write(DDRC_DFIMISC(0), 0x00000011); - } - - /* step23 [5]selfref_sw=0; */ - reg32_write(DDRC_PWRCTL(0), 0x00000008); - /* step24 sw_done=1 */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - - /* step25 wait SWSTAT.sw_done_ack to 1 */ - do { - tmp = reg32_read(DDRC_SWSTAT(0)); - } while ((tmp & 0x1) == 0x0); - -#ifdef DFI_BUG_WR - reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); -#endif - /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ - do { - tmp = reg32_read(DDRC_STAT(0)); - } while ((tmp & 0x3) != 0x1); - - /* step26 */ - reg32_write(DDRC_RFSHCTL3(0), 0x00000010); - - /* enable port 0 */ - reg32_write(DDRC_PCTRL_0(0), 0x00000001); - debug("DDRINFO: ddrmix config done\n"); - - /* save the dram timing config into memory */ - dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); -} From 69b8e50975c3ca623cf0f0d5bde0c93df76889e9 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 8 Aug 2019 09:59:11 +0000 Subject: [PATCH 177/190] ddr: imx8m: Fix the ddr init hang on imx8mq On, i.MX8MQ, the PLL config must be done when ddrmix isolation is released. So move the dram pll init after iso config done. For other i.MX8M SOC, either init pll before or after isolation is ok. Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/ddr_init.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index 12967583ea7..d6e915c9b9c 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -41,14 +41,14 @@ void ddr_init(struct dram_timing_info *dram_timing) clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); - initial_drate = dram_timing->fsp_msg[0].drate; - /* default to the frequency point 0 clock */ - ddrphy_init_set_dfi_clk(initial_drate); - /* disable iso */ reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + initial_drate = dram_timing->fsp_msg[0].drate; + /* default to the frequency point 0 clock */ + ddrphy_init_set_dfi_clk(initial_drate); + /* D-aasert the presetn */ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); From 80be404a25953ff14743705f2ec7403eb894c6f5 Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Thu, 18 Jul 2019 20:44:31 +0000 Subject: [PATCH 178/190] mx6ulevk: Include SDP boot instructions in README Add instructions on how to boot mx6ul_14x14_evk_defconfig target using the Serial Download Protocol. Add examples from uuu and imx_usb_loader tools. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam --- board/freescale/mx6ul_14x14_evk/README | 50 ++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/board/freescale/mx6ul_14x14_evk/README b/board/freescale/mx6ul_14x14_evk/README index 1edccf688cb..e101abe48c7 100644 --- a/board/freescale/mx6ul_14x14_evk/README +++ b/board/freescale/mx6ul_14x14_evk/README @@ -9,6 +9,9 @@ $ make This will generate the SPL image called SPL and the u-boot.img. +1. Booting via SDCard +--------------------- + - Flash the SPL image into the micro SD card: sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync @@ -30,3 +33,50 @@ switch label numbers reference). - Insert the micro SD card in the board, power it up and U-Boot messages should come up. + +2. Booting via Serial Download Protocol (SDP) +--------------------------------------------- + +The mx6ulevk board can boot from USB OTG port using the SDP, target will +enter in SDP mode in case an SD Card is not connect or boot switches are +set as below: + +Sw602: 0 1 +SW601: x x x x + +The following tools can be used to boot via SDP, for both tools you must +connect an USB cable in USB OTG port. + +- Method 1: Universal Update Utility (uuu) + +The UUU binary can be downloaded in release tab from link below: +https://github.com/NXPmicro/mfgtools + +The following script should be created to boot SPL + u-boot-dtb.img binaries: + + $ cat uuu_script + uuu_version 1.1.4 + + SDP: boot -f SPL + SDPU: write -f u-boot-dtb.img -addr 0x877fffc0 + SDPU: jump -addr 0x877fffc0 + SDPU: done + +Please note that the address above is calculated based on SYS_TEXT_BASE address: + +0x877fffc0 = 0x87800000 (SYS_TEXT_BASE) - 0x40 (U-Boot proper Header size) + +Power on the target and run the following command from U-Boot root directory: + + $ sudo ./uuu uuu_script + +- Method 2: imx usb loader tool (imx_usb): + +The imx_usb_loader tool can be downloaded in link below: +https://github.com/boundarydevices/imx_usb_loader + +Build the source code and run the following commands from U-Boot root +directory: + + $ sudo ./imx_usb SPL + $ sudo ./imx_usb u-boot-dtb.img From a3ecce373af981f701b1c71a98da3df188c21960 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 7 Aug 2019 12:05:58 -0500 Subject: [PATCH 179/190] ARM: imx6qlogic: Cleanup board_init_f Per the workflow found in crt0.S, we don't need to clear BSS in board_init_f nor do we need to call board_init_r since that will be done for us from main when we return from board_init_f. This patch removes the unneeded function calls from board_init_f. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- board/logicpd/imx6/imx6logic.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 7a59b89d94a..36ebe12773a 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -350,11 +350,5 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); } #endif From 7cf388fa6977136dd2384bd746d237efc306c829 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 7 Aug 2019 12:05:59 -0500 Subject: [PATCH 180/190] ARM: imx6q_logic: Enable DM_SERIAL In order to call preloader_console_init from board_init_f when DM_SERIAL is enabled, it neesd to call spl_early_init() to get early access to DM and device tree. This patch calls spl_early_init just before preloader_console_init() and enables DM_SERIAL and SPL_DM_SERIAL. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- board/logicpd/imx6/imx6logic.c | 3 +++ configs/imx6q_logic_defconfig | 1 + 2 files changed, 4 insertions(+) diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 36ebe12773a..7fb6dc42c67 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -348,6 +348,9 @@ void board_init_f(ulong dummy) /* setup GP timer */ timer_init(); + /* Enable device tree and early DM support*/ + spl_early_init(); + /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); } diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index ec14b8eaf6c..6125ee2bc23 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -83,6 +83,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_DM_USB=y From a7031d9f54a1a5bad08cd177cfc616b7a2de7267 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Sun, 4 Aug 2019 19:36:42 +0200 Subject: [PATCH 181/190] imx: variscite: Fix regression of SPL and U-boot booting 1. Commit 3a7c45f6a772 ("simple-bus: add DM_FLAG_PRE_RELOC flag to simple-bus driver") causes some i.MX boards that were converted to DM, such as warp7, to fail to boot. As explained by Lukas Auer: "With the patch, U-Boot probes the drivers for devices under simple-bus device tree nodes in the pre-relocation device model. The default value of CONFIG_SYS_MALLOC_F_LEN (0x4000) leaves U-Boot with not enough memory to do this, causing it to hang." Fix this problem by providing a convenient default value for CONFIG_SYS_MALLOC_F_LEN. 2. CONFIG_SPL_TEXT_BASE was moved to Kconfig, so added in defconfig "configs: move CONFIG_SPL_TEXT_BASE to Kconfig" (sha1: f89d6133eef2e068f9c33853b6584d7fcbfa9d2e) Signed-off-by: Saravanan Sekar Reviewed-by: Peng Fan --- configs/variscite_dart6ul_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index cb1b17c4240..ca6ea9de37d 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -51,3 +51,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_LZO=y +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 From 39fd054feedcf23f76c999846a11e320e449f5f4 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Mon, 16 Sep 2019 17:21:50 +0200 Subject: [PATCH 182/190] configs: move CONFIG_SPL_TEXT_BASE to Kconfig CONFIG_SPL_TEXT_BASE is moved to common/spl/Kconfig, update pcl063_ull defconfig. Signed-off-by: Parthiban Nallathambi --- configs/phycore_pcl063_ull_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 4b9bb369846..b516248a5f0 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=8 CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0x908000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" From c115cd154c1da885299e461cda93c9fc4edc952d Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Wed, 24 Jul 2019 18:09:57 +0300 Subject: [PATCH 183/190] pinctrl: nxp: DM_FLAG_PRE_RELOC by default For NXP SoCs we have to set pinmux configuration ASAP (ideally before relocation) to get serial console working. Without this we miss almost the half of output (U-boot version, CPU defails, Reset cause, DRAM details etc.). To achieve this we need to force appropriate pinctrl drivers to get probed before relocation. Fixes: cd69e8ef9b ("colibri-imx6ull: migrate pinctrl and regulators to dtb/dm") Signed-off-by: Igor Opaniuk Reviewed-by: Fabio Estevam Reviewed-by: Lukasz Majewski Reviewed-by: Oleksandr Suvorov --- drivers/pinctrl/nxp/pinctrl-imx5.c | 2 -- drivers/pinctrl/nxp/pinctrl-imx6.c | 2 -- drivers/pinctrl/nxp/pinctrl-imx7.c | 2 -- drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 2 -- 4 files changed, 8 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c index 4e831b6f39e..5d173809198 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx5.c +++ b/drivers/pinctrl/nxp/pinctrl-imx5.c @@ -40,7 +40,5 @@ U_BOOT_DRIVER(imx5_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, -#endif }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index 0c1e7a9c05a..aafa3057ada 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -49,7 +49,5 @@ U_BOOT_DRIVER(imx6_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, -#endif }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c index 8776fd96504..769d428ddad 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c @@ -37,7 +37,5 @@ U_BOOT_DRIVER(imx7_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, -#endif }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c index d778f82aac7..598bbfaf350 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c @@ -41,7 +41,5 @@ U_BOOT_DRIVER(imx7ulp_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, -#endif }; From d714a75fd4dcfb0eb8b7e1dd29f43e07113cec0b Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 20 Sep 2019 08:47:53 +0200 Subject: [PATCH 184/190] imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic --- Makefile | 4 ++-- arch/arm/Kconfig | 4 ++-- arch/arm/include/asm/arch-mx7/clock.h | 2 +- arch/arm/include/asm/mach-imx/hab.h | 2 +- arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/Makefile | 4 ++-- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/mx6/clock.c | 2 +- arch/arm/mach-imx/mx6/soc.c | 2 +- arch/arm/mach-imx/mx7/clock.c | 2 +- arch/arm/mach-imx/mx7/soc.c | 2 +- arch/arm/mach-imx/mx7ulp/clock.c | 2 +- arch/arm/mach-imx/mx7ulp/soc.c | 2 +- arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-imx/spl_sd.cfg | 2 +- board/boundary/nitrogen6x/nitrogen6dl.cfg | 2 +- board/boundary/nitrogen6x/nitrogen6dl2g.cfg | 2 +- board/boundary/nitrogen6x/nitrogen6q.cfg | 2 +- board/boundary/nitrogen6x/nitrogen6q2g.cfg | 2 +- board/boundary/nitrogen6x/nitrogen6s.cfg | 2 +- board/boundary/nitrogen6x/nitrogen6s1g.cfg | 2 +- board/freescale/mx6slevk/imximage.cfg | 2 +- board/freescale/mx6sllevk/imximage.cfg | 2 +- board/freescale/mx6sxsabresd/imximage.cfg | 2 +- board/freescale/mx6ullevk/imximage.cfg | 2 +- board/freescale/mx7dsabresd/imximage.cfg | 2 +- board/freescale/mx7ulp_evk/imximage.cfg | 2 +- board/toradex/colibri-imx6ull/imximage.cfg | 2 +- board/toradex/colibri_imx7/imximage.cfg | 2 +- board/warp/imximage.cfg | 2 +- board/warp7/imximage.cfg | 2 +- board/warp7/warp7.c | 2 +- common/spl/spl_fit.c | 2 +- configs/colibri_imx7_defconfig | 2 +- configs/colibri_imx7_emmc_defconfig | 2 +- configs/imx6dl_mamoj_defconfig | 2 +- configs/warp7_bl33_defconfig | 2 +- configs/warp7_defconfig | 2 +- doc/imx/habv4/guides/encrypted_boot.txt | 2 +- doc/imx/habv4/guides/mx6_mx7_secure_boot.txt | 6 +++--- doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt | 6 +++--- tools/spl_size_limit.c | 2 +- 42 files changed, 49 insertions(+), 49 deletions(-) diff --git a/Makefile b/Makefile index 733bcecd081..80b7811f7be 100644 --- a/Makefile +++ b/Makefile @@ -830,10 +830,10 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin -ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy) +ifeq ($(CONFIG_MX6)$(CONFIG_IMX_HAB), yy) ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img else -ifeq ($(CONFIG_MX7)$(CONFIG_SECURE_BOOT), yy) +ifeq ($(CONFIG_MX7)$(CONFIG_IMX_HAB), yy) ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img else ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3b0e315061a..c219a53be82 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -812,7 +812,7 @@ config ARCH_MX7 select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_V7A - select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE imply MXC_GPIO @@ -820,7 +820,7 @@ config ARCH_MX7 config ARCH_MX6 bool "Freescale MX6" select CPU_V7A - select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE select SYS_THUMB_BUILD if SPL diff --git a/arch/arm/include/asm/arch-mx7/clock.h b/arch/arm/include/asm/arch-mx7/clock.h index 1d07fde5432..984bd3f141a 100644 --- a/arch/arm/include/asm/arch-mx7/clock.h +++ b/arch/arm/include/asm/arch-mx7/clock.h @@ -357,7 +357,7 @@ int set_clk_nand(void); void enable_ocotp_clk(unsigned char enable); #endif void enable_usboh3_clk(unsigned char enable); -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB void hab_caam_clock_enable(unsigned char enable); #endif void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq); diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index 95df88423cc..b905d84bdc8 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -130,7 +130,7 @@ struct imx_sec_config_fuse_t { int word; }; -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_IMX_HAB) extern struct imx_sec_config_fuse_t const imx_sec_config_fuse; #endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f721eaf937c..b0b9d2c070e 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -34,7 +34,7 @@ config USE_IMXIMG_PLUGIN i.MX6/7 supports DCD and Plugin. Enable this configuration to use Plugin, otherwise DCD will be used. -config SECURE_BOOT +config IMX_HAB bool "Support i.MX HAB features" depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 select FSL_CAAM if HAS_CAAM diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 87fd69706d2..fbd99a34998 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -44,12 +44,12 @@ ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif obj-$(CONFIG_SATA) += sata.o -obj-$(CONFIG_SECURE_BOOT) += hab.o +obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif ifeq ($(SOC),$(filter $(SOC),mx7ulp)) obj-y += cache.o -obj-$(CONFIG_SECURE_BOOT) += hab.o +obj-$(CONFIG_IMX_HAB) += hab.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index f9040491200..aeca82cdbf4 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_IMX_HAB) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, .word = 3, diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 5af1ae7cf38..7763c79e1c2 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1152,7 +1152,7 @@ int enable_pcie_clock(void) } #endif -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB void hab_caam_clock_enable(unsigned char enable) { u32 reg; diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index d37d3856d3e..6dccee484c5 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -50,7 +50,7 @@ U_BOOT_DEVICE(imx6_thermal) = { }; #endif -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_IMX_HAB) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 0, .word = 6, diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index 4f9724cadbf..0e08cabb7ad 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -1074,7 +1074,7 @@ void clock_init(void) } } -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB void hab_caam_clock_enable(unsigned char enable) { if (enable) diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 3b8e1ba9c3a..35160f4b379 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -122,7 +122,7 @@ static void isolate_resource(void) } #endif -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_IMX_HAB) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, .word = 3, diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 7bf83170eb9..d3365dd411d 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -314,7 +314,7 @@ void clock_init(void) enable_usboh3_clk(1); } -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB void hab_caam_clock_enable(unsigned char enable) { if (enable) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 6c53aa106e7..127fcfeea1a 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -11,7 +11,7 @@ static char *get_reset_cause(char *); -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_IMX_HAB) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 29, .word = 6, diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 30fa6aeb25f..9fa397c94da 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -222,7 +222,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_IMX_HAB) /* * +------------+ 0x0 (DDR_UIMAGE_START) - diff --git a/arch/arm/mach-imx/spl_sd.cfg b/arch/arm/mach-imx/spl_sd.cfg index e791debf10b..dbaee815357 100644 --- a/arch/arm/mach-imx/spl_sd.cfg +++ b/arch/arm/mach-imx/spl_sd.cfg @@ -12,6 +12,6 @@ BOOT_FROM sd /* * Secure boot support */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg index b1e3c0fe45c..56b3bcbb2fb 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -19,7 +19,7 @@ BOOT_FROM spi #define __ASSEMBLY__ #include -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif #include "asm/arch/mx6-ddr.h" diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg index 3e7d605bf5e..13f7a89232f 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -19,7 +19,7 @@ BOOT_FROM spi #define __ASSEMBLY__ #include -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif #include "asm/arch/mx6-ddr.h" diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg index 26bb6451a28..1304b52d183 100644 --- a/board/boundary/nitrogen6x/nitrogen6q.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -19,7 +19,7 @@ BOOT_FROM spi #define __ASSEMBLY__ #include -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif #include "asm/arch/mx6-ddr.h" diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg index 5ff3eedc195..e5e923d3cff 100644 --- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -19,7 +19,7 @@ BOOT_FROM spi #define __ASSEMBLY__ #include -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif #include "asm/arch/mx6-ddr.h" diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg index 5482656e8f5..e5f814b7158 100644 --- a/board/boundary/nitrogen6x/nitrogen6s.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -19,7 +19,7 @@ BOOT_FROM spi #define __ASSEMBLY__ #include -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif #include "asm/arch/mx6-ddr.h" diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg index dd30ca94395..f3d754e23aa 100644 --- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -19,7 +19,7 @@ BOOT_FROM spi #define __ASSEMBLY__ #include -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif #include "asm/arch/mx6-ddr.h" diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index b33bb93f4c1..fd71bef286b 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -24,7 +24,7 @@ BOOT_FROM sd /* * Secure boot support */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg index 2dcff0014ab..74b3a907bf2 100644 --- a/board/freescale/mx6sllevk/imximage.cfg +++ b/board/freescale/mx6sllevk/imximage.cfg @@ -27,7 +27,7 @@ BOOT_FROM sd PLUGIN board/freescale/mx6sllevk/plugin.bin 0x00907000 #else -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg index 0354bb36e25..28ffb2f8bc9 100644 --- a/board/freescale/mx6sxsabresd/imximage.cfg +++ b/board/freescale/mx6sxsabresd/imximage.cfg @@ -20,7 +20,7 @@ BOOT_FROM sd /* * Secure boot support */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg index 39306d4cd10..40818d0a037 100644 --- a/board/freescale/mx6ullevk/imximage.cfg +++ b/board/freescale/mx6ullevk/imximage.cfg @@ -33,7 +33,7 @@ BOOT_FROM sd PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 #else -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg index b72e0cf47cd..a0f39c4062e 100644 --- a/board/freescale/mx7dsabresd/imximage.cfg +++ b/board/freescale/mx7dsabresd/imximage.cfg @@ -24,7 +24,7 @@ BOOT_FROM sd /* * Secure boot support */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index 43ebc230914..ec3673040ba 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -27,7 +27,7 @@ BOOT_FROM sd PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 #else -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif /* diff --git a/board/toradex/colibri-imx6ull/imximage.cfg b/board/toradex/colibri-imx6ull/imximage.cfg index 2ce55a610a5..a11e288c6c9 100644 --- a/board/toradex/colibri-imx6ull/imximage.cfg +++ b/board/toradex/colibri-imx6ull/imximage.cfg @@ -25,7 +25,7 @@ BOOT_FROM nand /* * Secure boot support */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg index 25cfd5c6f8c..1b4f272bb62 100644 --- a/board/toradex/colibri_imx7/imximage.cfg +++ b/board/toradex/colibri_imx7/imximage.cfg @@ -25,7 +25,7 @@ BOOT_FROM sd /* * Secure boot support */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg index 4fb5a84205e..dea331cab15 100644 --- a/board/warp/imximage.cfg +++ b/board/warp/imximage.cfg @@ -24,7 +24,7 @@ BOOT_FROM sd /* * Secure boot support */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG__IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/warp7/imximage.cfg b/board/warp7/imximage.cfg index a6edfdacef3..a4c2f677a1a 100644 --- a/board/warp7/imximage.cfg +++ b/board/warp7/imximage.cfg @@ -12,7 +12,7 @@ #include IMAGE_VERSION 2 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 39ae9822573..c423e049cb3 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -146,7 +146,7 @@ int board_late_init(void) */ clrsetbits_le16(&wdog->wcr, 0, 0x10); -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB /* Determine HAB state */ env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled()); #else diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index b3e3ccd5a2b..cbc00a4e7c5 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -553,7 +553,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, spl_image->flags |= SPL_FIT_FOUND; -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_IMX_HAB board_spl_fit_post_load((ulong)fit, size); #endif diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index a9149dd15c7..a6457d50540 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SECURE_BOOT=y +CONFIG_IMX_HAB=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_NR_DRAM_BANKS=1 CONFIG_IMX_RDC=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index c5de2e7b1cc..b4ca115f13b 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SECURE_BOOT=y +CONFIG_IMX_HAB=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_TARGET_COLIBRI_IMX7_EMMC=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 983d98536ce..6b92f942e50 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SECURE_BOOT=y +CONFIG_IMX_HAB=y CONFIG_TARGET_MX6DL_MAMOJ=y CONFIG_NR_DRAM_BANKS=1 CONFIG_CSF_SIZE=0x2060 diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 80accfb5093..9d161f3ecbe 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SECURE_BOOT=y +CONFIG_IMX_HAB=y CONFIG_TARGET_WARP7=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_FIT=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index a0224549763..62e331d985f 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SECURE_BOOT=y +CONFIG_IMX_HAB=y CONFIG_TARGET_WARP7=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y diff --git a/doc/imx/habv4/guides/encrypted_boot.txt b/doc/imx/habv4/guides/encrypted_boot.txt index c59d204d38f..e2b435749e3 100644 --- a/doc/imx/habv4/guides/encrypted_boot.txt +++ b/doc/imx/habv4/guides/encrypted_boot.txt @@ -16,7 +16,7 @@ The DEK blob is generated by an authenticated U-Boot image with the dek_blob cmd enabled. The image used for DEK blob generation needs to have the following configurations enabled in Kconfig: -CONFIG_SECURE_BOOT=y +CONFIG_IMX_HAB=y CONFIG_CMD_DEKBLOB=y Note: The encrypted boot feature is only supported by HABv4 or diff --git a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt index 98e18beecd2..20fff937b66 100644 --- a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt +++ b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt @@ -17,7 +17,7 @@ introduction_habv4.txt document. The U-Boot provides support to secure boot configuration and also provide access to the HAB APIs exposed by the ROM vector table, the support is -enabled by selecting the CONFIG_SECURE_BOOT option. +enabled by selecting the CONFIG_IMX_HAB option. When built with this configuration, the U-Boot provides extra functions for HAB, such as the HAB status logs retrievement through the hab_status command @@ -57,12 +57,12 @@ The diagram below illustrate a signed u-boot-dtb.imx image layout: ------------------------------------- The first step is to generate an U-Boot image supporting the HAB features -mentioned above, this can be achieved by adding CONFIG_SECURE_BOOT to the +mentioned above, this can be achieved by adding CONFIG_IMX_HAB to the build configuration: - Defconfig: - CONFIG_SECURE_BOOT=y + CONFIG_IMX_HAB=y - Kconfig: diff --git a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt index 0d7931aac00..fde0f27efdc 100644 --- a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt +++ b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt @@ -27,7 +27,7 @@ root of trust. The U-Boot provides support to secure boot configuration and also provide access to the HAB APIs exposed by the ROM vector table, the support is -enabled by selecting the CONFIG_SECURE_BOOT option. +enabled by selecting the CONFIG_IMX_HAB option. When built with this configuration the U-Boot correctly pads the final SPL image by aligning to the next 0xC00 address, so the CSF signature data @@ -82,12 +82,12 @@ The diagram below illustrate a signed u-boot-ivt.img image layout: ------------------------------------- The first step is to generate an U-Boot image supporting the HAB features -mentioned above, this can be achieved by adding CONFIG_SECURE_BOOT to the +mentioned above, this can be achieved by adding CONFIG_IMX_HAB to the build configuration: - Defconfig: - CONFIG_SECURE_BOOT=y + CONFIG_IMX_HAB=y - Kconfig: diff --git a/tools/spl_size_limit.c b/tools/spl_size_limit.c index 8902e30129a..c6c139e834f 100644 --- a/tools/spl_size_limit.c +++ b/tools/spl_size_limit.c @@ -14,7 +14,7 @@ int main(int argc, char *argv[]) #ifdef CONFIG_SPL_SIZE_LIMIT spl_size_limit = CONFIG_SPL_SIZE_LIMIT; -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_CSF_SIZE) +#if defined(CONFIG_IMX_HAB) && defined(CONFIG_CSF_SIZE) spl_size_limit -= CONFIG_CSF_SIZE; #endif #ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD From f730fdf98b78deb331b7f114b75aebd4e6c6e523 Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Mon, 23 Sep 2019 14:54:40 +0200 Subject: [PATCH 185/190] pico-imx7d: fix splash logo drawing Signed-off-by: Joris Offouga Reviewed-by: Otavio Salvador --- board/technexion/pico-imx7d/pico-imx7d.c | 13 ------------- configs/pico-dwarf-imx7d_defconfig | 2 ++ configs/pico-hobbit-imx7d_defconfig | 2 ++ configs/pico-imx7d_bl33_defconfig | 2 ++ configs/pico-imx7d_defconfig | 2 ++ configs/pico-nymph-imx7d_defconfig | 2 ++ configs/pico-pi-imx7d_defconfig | 2 ++ include/configs/pico-imx7d.h | 1 + 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 916220516e4..32b04b8fd6d 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -19,10 +19,6 @@ #include #include #include "../../freescale/common/pfuze.h" -#ifdef CONFIG_DM_VIDEO -#include -#include -#endif DECLARE_GLOBAL_DATA_PTR; @@ -250,18 +246,9 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_DM_VIDEO - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); - if (ret) - return ret; setup_lcd(); - ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, 0, 0, true); - if (ret) - return ret; #endif #ifdef CONFIG_FEC_MXC setup_fec(); diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 97de873e7cb..5ddf8d9001d 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MII is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -67,3 +68,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index f3ed298087b..8628ba4275a 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MII is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -67,3 +68,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index ba347d2507e..d7752446cd2 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BMP=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 @@ -63,4 +64,5 @@ CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 1e54bcc0312..40b14d18e82 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MII is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -67,3 +68,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 97de873e7cb..5ddf8d9001d 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MII is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -67,3 +68,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index c44bc778ca1..f9069d9b087 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MII is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -67,3 +68,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 956c383a312..5c4b90a8a1e 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -85,6 +85,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ From 3a7f25b7653a00f8dad40a42a68da9d7b8a7a81d Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Mon, 23 Sep 2019 14:54:41 +0200 Subject: [PATCH 186/190] pico-imx7d: Remove dead code for dm_video Since convert dm_video, unused code introduced, so remove this Signed-off-by: Joris Offouga Reviewed-by: Otavio Salvador --- arch/arm/dts/imx7d-pico-u-boot.dtsi | 37 ------------------------ board/technexion/pico-imx7d/pico-imx7d.c | 12 -------- 2 files changed, 49 deletions(-) diff --git a/arch/arm/dts/imx7d-pico-u-boot.dtsi b/arch/arm/dts/imx7d-pico-u-boot.dtsi index ef19de2b308..7307fbaf687 100644 --- a/arch/arm/dts/imx7d-pico-u-boot.dtsi +++ b/arch/arm/dts/imx7d-pico-u-boot.dtsi @@ -4,37 +4,6 @@ usb0 = &usbotg1; display0 = &lcdif; }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm4 0 50000 0>; - brightness-levels = <0 36 72 108 144 180 216 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel { - compatible = "vxt,vl050-8048nt-c01"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; }; &usbotg1 { @@ -48,12 +17,6 @@ display = <&display0>; u-boot,dm-pre-reloc; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - display0: display { bits-per-pixel = <16>; bus-width = <24>; diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 32b04b8fd6d..bfa3c3c87f0 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -33,13 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - -#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ - PAD_CTL_DSE_3P3V_49OHM) - -#define LCD_SYNC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ - PAD_CTL_DSE_3P3V_196OHM) - #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -224,13 +217,8 @@ int board_early_init_f(void) } #ifdef CONFIG_DM_VIDEO -static iomux_v3_cfg_t const lcd_pads[] = { - MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - void setup_lcd(void) { - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness"); gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable"); /* Set Brightness to high */ From 86d2b28b28f547e3e53994b5fe7af3e25418e72e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 6 Oct 2019 15:37:51 +0200 Subject: [PATCH 187/190] configs: sheevaplug disable EFI_UNICODE_CAPITALIZATION With upcoming patches u-boot.kwb gets too large. Save 3740 bytes in u-boot.kwb by disabling Unicode support in the UEFI sub-system. Signed-off-by: Heinrich Schuchardt --- configs/sheevaplug_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 734e894c983..cc485364153 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -46,3 +46,4 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LZMA=y +# CONFIG_EFI_UNICODE_CAPITALIZATION is not set From 83afe3b1c9f3dd872068bb67ec5b5814ac5a0cb3 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 8 Oct 2019 11:01:53 +0200 Subject: [PATCH 188/190] Revert "imx: mmc_env: update runtime SD/MMC boot env device" This reverts commit 34f2feb92db6146831bafa696b7b46785c9f6b10. Signed-off-by: Stefano Babic --- arch/arm/mach-imx/mmc_env.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index addb50f5382..9c822f721c6 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -11,9 +11,6 @@ __weak int board_mmc_get_env_dev(int devno) { - if (CONFIG_IS_ENABLED(DM_MMC)) - return devno; - return CONFIG_SYS_MMC_ENV_DEV; } From 63ce94b16b3527bc6944d1ab8b2572c6f39e0aef Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 8 Oct 2019 07:56:44 -0500 Subject: [PATCH 189/190] Revert "spl: imx6: Let spl_boot_device return USDHC1 or USDHC2" Apologies to everyone whose board I broke by attempting to return MMC1 or MMC2. I misunderstood how the MMC indexing worked. This reverts commit 14d319b1856b86e593e01abd0a1e3c2d63b52a8a. Signed-off-by: Adam Ford --- arch/arm/mach-imx/spl.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 9fa397c94da..f025c4b301e 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -29,7 +29,6 @@ u32 spl_boot_device(void) { unsigned int bmode = readl(&src_base->sbmr2); u32 reg = imx6_src_get_boot_mode(); - u32 mmc_index = ((reg >> 11) & 0x03); /* * Check for BMODE if serial downloader is enabled @@ -90,12 +89,11 @@ u32 spl_boot_device(void) /* SD/eSD: 8.5.3, Table 8-15 */ case IMX6_BMODE_SD: case IMX6_BMODE_ESD: + return BOOT_DEVICE_MMC1; + /* MMC/eMMC: 8.5.3 */ case IMX6_BMODE_MMC: case IMX6_BMODE_EMMC: - if (mmc_index == 1) - return BOOT_DEVICE_MMC2; - else - return BOOT_DEVICE_MMC1; + return BOOT_DEVICE_MMC1; /* NAND Flash: 8.5.2, Table 8-10 */ case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX: return BOOT_DEVICE_NAND; From 9fb50c68daa696056c7842989e5f7fae1d326b34 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 8 Oct 2019 08:01:12 -0500 Subject: [PATCH 190/190] ARM: imx6q_logic: Fix MMC2 booting With the reverting of a previous change to spl_boot_device, this board needs a new solution to determining if we're booting from MMC1 or MMC2. This patch creates board_boot_order function which overrides the standard, and returns not only MMC1, or MMC2, but also can fall back to NAND or the serial downloader should other boot options fail. Signed-off-by: Adam Ford --- board/logicpd/imx6/imx6logic.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 7fb6dc42c67..4bacd8660a9 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -207,6 +207,35 @@ struct fsl_esdhc_cfg usdhc_cfg[] = { {USDHC2_BASE_ADDR} /* Baseboard */ }; +void board_boot_order(u32 *spl_boot_list) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1-SOM + * 0x2 SD2-Baseboard + */ + + reg &= 0x3; /* Only care about bottom 2 bits */ + switch (reg) { + case 0: + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case 1: + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + } + + /* If we cannot find a valid MMC/SD card, try NAND */ + spl_boot_list[1] = BOOT_DEVICE_NAND; + + /* As a last resort, use serial downloader */ + spl_boot_list[2] = BOOT_DEVICE_BOARD; +} + int board_mmc_init(bd_t *bis) { struct src *psrc = (struct src *)SRC_BASE_ADDR;