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Xilinx changes for v2022.10-rc2

Browse Source 
fpga:
 - Convert SYS_FPGA_CHECK_CTRLC and SYS_FPGA_PROG_FEEDBACK to Kconfig
 - Add support for secure bitstream loading
 
 spi:
 - xilinx_spi: Add support for memopers and supports_op
 - zynq_qspi: Add support for supports_op/child_pre_probe
 - zynq_qspi: Fix dummy cycle and qspi speed calculations
 
 xilinx:
 - Get rid of #stream-id-cells
 - Use fixed partitions for SOM
 - Add support for UUID reading from FRU
 - Use strlcpy instead of strncpy
 - Add reset driver support for ZynqMP and Versal
 - Enable power domain driver in ZynqMP and Versal
 
 zynqmp:
 - Do no place BSS at 0 which have issue with NULL pointer
 - Enable SLG gpio driver
 - Disable LMB for mini configurations
 - Remove duplicate PMIO_NODE_ID_BASE macro
 
 versal:
 - Add xlnx-versal-resets.h header
 
 mmc:
 - zynq_sdhci: Fix macro for MMC HS
 
 relocate-rela:
 - Fix support for BE hosts
 - Define all macros for e_machine and reloc types
 
 misc:
 - Get rid of guard macros from ARM and RISC-V
 
 lmb:
 - Add support for disabling LMB
 
 serial:
 - zynq: Fix baudrate calculation
 
 tests:
 - Mark bind tests to run only on sandbox
 - List also dm uclass and devres
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 Idn1AKCZaIz+7b/si1+pTmdVqdFSd3GrigCeLlVkhR7lXm36fVsv0TCQr0mwJPc=
 =KCC4
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Merge tag 'xilinx-for-v2022.10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.10-rc2

fpga:
- Convert SYS_FPGA_CHECK_CTRLC and SYS_FPGA_PROG_FEEDBACK to Kconfig
- Add support for secure bitstream loading

spi:
- xilinx_spi: Add support for memopers and supports_op
- zynq_qspi: Add support for supports_op/child_pre_probe
- zynq_qspi: Fix dummy cycle and qspi speed calculations

xilinx:
- Get rid of #stream-id-cells
- Use fixed partitions for SOM
- Add support for UUID reading from FRU
- Use strlcpy instead of strncpy
- Add reset driver support for ZynqMP and Versal
- Enable power domain driver in ZynqMP and Versal

zynqmp:
- Do no place BSS at 0 which have issue with NULL pointer
- Enable SLG gpio driver
- Disable LMB for mini configurations
- Remove duplicate PMIO_NODE_ID_BASE macro

versal:
- Add xlnx-versal-resets.h header

mmc:
- zynq_sdhci: Fix macro for MMC HS

relocate-rela:
- Fix support for BE hosts
- Define all macros for e_machine and reloc types

misc:
- Get rid of guard macros from ARM and RISC-V

lmb:
- Add support for disabling LMB

serial:
- zynq: Fix baudrate calculation

tests:
- Mark bind tests to run only on sandbox
- List also dm uclass and devres
This commit is contained in:
Tom Rini 2022-07-26 08:32:37 -04:00
commit e5f6fecda4
63 changed files with 837 additions and 390 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
README
View File

@ -1330,10 +1330,6 @@ The following options need to be configured:
Enables support for FPGA family.
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
CONFIG_SYS_FPGA_CHECK_BUSY
Enable checks on FPGA configuration interface busy
@ -1346,9 +1342,6 @@ The following options need to be configured:
If defined, a function that provides delays in the FPGA
configuration driver.
CONFIG_SYS_FPGA_CHECK_CTRLC
Allow Control-C to interrupt FPGA configuration
CONFIG_SYS_FPGA_CHECK_ERROR
Check for configuration errors during FPGA bitfile

2
arch/arc/lib/bootm.c
View File

@ -29,9 +29,11 @@ static int boot_prep_linux(bootm_headers_t *images)
{
int ret;
if (CONFIG_IS_ENABLED(LMB)) {
ret = image_setup_linux(images);
if (ret)
return ret;
}
return board_prep_linux(images);
}

1
arch/arm/dts/versal-mini-emmc0.dts
View File

@ -47,7 +47,6 @@
xlnx,device_id = <0>;
no-1-8-v;
xlnx,mio-bank = <0>;
#stream-id-cells = <1>;
};
};

1
arch/arm/dts/versal-mini-emmc1.dts
View File

@ -47,7 +47,6 @@
xlnx,device_id = <1>;
no-1-8-v;
xlnx,mio-bank = <0>;
#stream-id-cells = <1>;
};
};

9
arch/arm/dts/zynqmp-sm-k26-revA.dts
View File

@ -130,7 +130,7 @@
&qspi { /* MIO 0-5 - U143 */
status = "okay";
flash@0 { /* MT25QU512A */
spi_flash: flash@0 { /* MT25QU512A */
compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
@ -138,6 +138,12 @@
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>; /* 40MHz */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Image Selector";
reg = <0x0 0x80000>; /* 512KB */
@ -217,6 +223,7 @@
reg = <0x2250000 0x1db0000>; /* 29.5 MB */
};
};
};
};
&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */

28
arch/arm/dts/zynqmp.dtsi
View File

@ -281,7 +281,6 @@
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14e8>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -295,7 +294,6 @@
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14e9>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -309,7 +307,6 @@
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ea>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -323,7 +320,6 @@
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14eb>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -337,7 +333,6 @@
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ec>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -351,7 +346,6 @@
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ed>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -365,7 +359,6 @@
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ee>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -379,7 +372,6 @@
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
#stream-id-cells = <1>;
iommus = <&smmu 0x14ef>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
@ -420,7 +412,6 @@
interrupts = <0 77 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x868>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -434,7 +425,6 @@
interrupts = <0 78 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x869>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -448,7 +438,6 @@
interrupts = <0 79 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86a>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -462,7 +451,6 @@
interrupts = <0 80 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86b>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -476,7 +464,6 @@
interrupts = <0 81 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86c>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -490,7 +477,6 @@
interrupts = <0 82 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86d>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -504,7 +490,6 @@
interrupts = <0 83 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86e>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -518,7 +503,6 @@
interrupts = <0 84 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = <&smmu 0x86f>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
@ -540,7 +524,6 @@
interrupts = <0 14 4>;
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x872>;
power-domains = <&zynqmp_firmware PD_NAND>;
};
@ -554,7 +537,6 @@
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
@ -569,7 +551,6 @@
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
@ -584,7 +565,6 @@
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
@ -599,7 +579,6 @@
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
@ -676,7 +655,6 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x4d0>;
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
@ -698,7 +676,6 @@
<0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x873>;
power-domains = <&zynqmp_firmware PD_QSPI>;
};
@ -730,7 +707,6 @@
interrupts = <0 133 4>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
#stream-id-cells = <4>;
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
<&smmu 0x4c2>, <&smmu 0x4c3>;
/* dma-coherent; */
@ -745,7 +721,6 @@
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x870>;
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
@ -762,7 +737,6 @@
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <1>;
#stream-id-cells = <1>;
iommus = <&smmu 0x871>;
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
@ -892,7 +866,6 @@
interrupt-parent = <&gic>;
interrupt-names = "dwc_usb3", "otg", "hiber";
interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
@ -924,7 +897,6 @@
interrupt-parent = <&gic>;
interrupt-names = "dwc_usb3", "otg", "hiber";
interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;

4
arch/arm/lib/bootm.c
View File

@ -199,13 +199,11 @@ static void boot_prep_linux(bootm_headers_t *images)
{
char *commandline = env_get("bootargs");
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
if (CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
panic("FDT creation failed!");
}
#endif
} else if (BOOTM_ENABLE_TAGS) {
debug("using: ATAGS\n");
setup_start_tag(gd->bd);

1
arch/arm/mach-zynq/cpu.c
View File

@ -22,6 +22,7 @@ xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
.operations = &zynq_op,
.flags = FPGA_LEGACY,
};
#endif

5
arch/arm/mach-zynqmp/include/mach/sys_proto.h
View File

@ -46,11 +46,6 @@ enum {
TCM_SPLIT,
};
struct zynqmp_ipi_msg {
size_t len;
u32 *buf;
};
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);

2
arch/m68k/lib/bootm.c
View File

@ -60,9 +60,11 @@ int do_bootm_linux(int flag, int argc, char *const argv[],
}
set_clocks_in_mhz(kbd);
if (CONFIG_IS_ENABLED(LMB)) {
ret = image_setup_linux(images);
if (ret)
goto error;
}
kernel = (void (*)(struct bd_info *, ulong, ulong, ulong, ulong))images->ep;

2
arch/microblaze/lib/bootm.c
View File

@ -73,7 +73,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
static void boot_prep_linux(bootm_headers_t *images)
{
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");

2
arch/powerpc/lib/bootm.c
View File

@ -214,9 +214,11 @@ static int boot_body_linux(bootm_headers_t *images)
if (ret)
return ret;
if (CONFIG_IS_ENABLED(LMB)) {
ret = image_setup_linux(images);
if (ret)
return ret;
}
return 0;
}

4
arch/riscv/lib/bootm.c
View File

@ -64,14 +64,12 @@ static void announce_and_cleanup(int fake)
static void boot_prep_linux(bootm_headers_t *images)
{
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
if (CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");
hang();
}
#endif
} else {
printf("Device tree not found or missing FDT support\n");
hang();

5
arch/x86/lib/bootm.c
View File

@ -78,15 +78,14 @@ static int boot_prep_linux(bootm_headers_t *images)
size_t len;
int ret;
#ifdef CONFIG_OF_LIBFDT
if (images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
puts("FDT creation failed! hanging...");
hang();
}
}
#endif
if (images->legacy_hdr_valid) {
hdr = images->legacy_hdr_os;
if (image_check_type(hdr, IH_TYPE_MULTI)) {

26
board/xilinx/common/board.c
View File

@ -23,6 +23,7 @@
#include <soc.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <uuid.h>
#include "fru.h"
@ -86,6 +87,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
#define EEPROM_HDR_SERIAL_LEN 20
#define EEPROM_HDR_NO_OF_MAC_ADDR 4
#define EEPROM_HDR_ETH_ALEN ETH_ALEN
#define EEPROM_HDR_UUID_LEN 16
struct xilinx_board_description {
u32 header;
@ -94,6 +96,7 @@ struct xilinx_board_description {
char revision[EEPROM_HDR_REV_LEN + 1];
char serial[EEPROM_HDR_SERIAL_LEN + 1];
u8 mac_addr[EEPROM_HDR_NO_OF_MAC_ADDR][EEPROM_HDR_ETH_ALEN + 1];
char uuid[EEPROM_HDR_UUID_LEN + 1];
};
static int highest_id = -1;
@ -235,21 +238,23 @@ static int xilinx_read_eeprom_fru(struct udevice *dev, char *name,
}
/* It is clear that FRU was captured and structures were filled */
strncpy(desc->manufacturer, (char *)fru_data.brd.manufacturer_name,
strlcpy(desc->manufacturer, (char *)fru_data.brd.manufacturer_name,
sizeof(desc->manufacturer));
strncpy(desc->name, (char *)fru_data.brd.product_name,
strlcpy(desc->uuid, (char *)fru_data.brd.uuid,
sizeof(desc->uuid));
strlcpy(desc->name, (char *)fru_data.brd.product_name,
sizeof(desc->name));
for (i = 0; i < sizeof(desc->name); i++) {
if (desc->name[i] == ' ')
desc->name[i] = '\0';
}
strncpy(desc->revision, (char *)fru_data.brd.rev,
strlcpy(desc->revision, (char *)fru_data.brd.rev,
sizeof(desc->revision));
for (i = 0; i < sizeof(desc->revision); i++) {
if (desc->revision[i] == ' ')
desc->revision[i] = '\0';
}
strncpy(desc->serial, (char *)fru_data.brd.serial_number,
strlcpy(desc->serial, (char *)fru_data.brd.serial_number,
sizeof(desc->serial));
while (id < EEPROM_HDR_NO_OF_MAC_ADDR) {
@ -452,6 +457,19 @@ int board_late_init_xilinx(void)
ret |= env_set_by_index("serial", id,
desc->serial);
if (desc->uuid[0]) {
char uuid[UUID_STR_LEN + 1];
char *t = desc->uuid;
memset(uuid, 0, UUID_STR_LEN + 1);
sprintf(uuid, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x",
t[0], t[1], t[2], t[3], t[4], t[5],
t[6], t[7], t[8], t[9], t[10], t[11],
t[12], t[13], t[14], t[15]);
ret |= env_set_by_index("uuid", id, uuid);
}
if (!CONFIG_IS_ENABLED(NET))
continue;

5
board/xilinx/versal/board.c
View File

@ -27,7 +27,10 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FPGA_VERSALPL)
static xilinx_desc versalpl = XILINX_VERSAL_DESC;
static xilinx_desc versalpl = {
xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
FPGA_LEGACY
};
#endif
int board_init(void)

8
board/xilinx/zynqmp/zynqmp.c
View File

@ -48,7 +48,10 @@
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
static xilinx_desc zynqmppl = {
xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL,
ZYNQMP_FPGA_FLAGS
};
#endif
int __maybe_unused psu_uboot_init(void)
@ -253,6 +256,7 @@ int dram_init(void)
return 0;
}
#if defined(CONFIG_LMB)
ulong board_get_usable_ram_top(ulong total_size)
{
phys_size_t size;
@ -277,6 +281,8 @@ ulong board_get_usable_ram_top(ulong total_size)
return reg + size;
}
#endif
#else
int dram_init_banksize(void)
{

4
boot/Kconfig
View File

@ -210,8 +210,8 @@ config SPL_LOAD_FIT
1. "loadables" images, other than FDTs, which do not have a "load"
property will not be loaded. This limitation also applies to FPGA
images with the correct "compatible" string.
2. For FPGA images, only the "compatible" = "u-boot,fpga-legacy"
loading method is supported.
2. For FPGA images, the supported "compatible" list is in the
doc/uImage.FIT/source_file_format.txt.
3. FDTs are only loaded for images with an "os" property of "u-boot".
"linux" images are also supported with Falcon boot mode.

8
boot/image-board.c
View File

@ -537,6 +537,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images,
return 0;
}
#if defined(CONFIG_LMB)
/**
* boot_ramdisk_high - relocate init ramdisk
* @lmb: pointer to lmb handle, will be used for memory mgmt
@ -630,6 +631,7 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
error:
return -1;
}
#endif
int boot_get_setup(bootm_headers_t *images, u8 arch,
ulong *setup_start, ulong *setup_len)
@ -703,14 +705,14 @@ int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images,
img_len, BIT_FULL);
if (err)
err = fpga_load(devnum, (const void *)img_data,
img_len, BIT_FULL);
img_len, BIT_FULL, 0);
} else {
name = "partial";
err = fpga_loadbitstream(devnum, (char *)img_data,
img_len, BIT_PARTIAL);
if (err)
err = fpga_load(devnum, (const void *)img_data,
img_len, BIT_PARTIAL);
img_len, BIT_PARTIAL, 0);
}
if (err)
@ -823,6 +825,7 @@ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
return 0;
}
#if defined(CONFIG_LMB)
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
/**
* boot_get_cmdline - allocate and initialize kernel cmdline
@ -932,6 +935,7 @@ int image_setup_linux(bootm_headers_t *images)
return 0;
}
#endif
void genimg_print_size(uint32_t size)
{

3
cmd/Kconfig
View File

@ -1038,8 +1038,9 @@ config CMD_FPGA_LOADP
a partial bitstream.
config CMD_FPGA_LOAD_SECURE
bool "fpga loads - loads secure bitstreams (Xilinx only)"
bool "fpga loads - loads secure bitstreams"
depends on CMD_FPGA
select FPGA_LOAD_SECURE
help
Enables the fpga loads command which is used to load secure
(authenticated or encrypted or both) bitstreams on to FPGA.

8
cmd/fpga.c
View File

@ -178,7 +178,7 @@ static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc,
if (ret)
return ret;
return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL);
return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL, 0);
}
static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc,
@ -209,7 +209,7 @@ static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc,
if (ret)
return ret;
return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL);
return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL, 0);
}
#endif
@ -315,7 +315,7 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
data_size = image_get_data_size(hdr);
}
return fpga_load(dev, (void *)data, data_size,
BIT_FULL);
BIT_FULL, 0);
}
#endif
#if defined(CONFIG_FIT)
@ -355,7 +355,7 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
return CMD_RET_FAILURE;
}
return fpga_load(dev, fit_data, data_size, BIT_FULL);
return fpga_load(dev, fit_data, data_size, BIT_FULL, 0);
}
#endif
default:

3
common/spl/Kconfig
View File

@ -107,7 +107,7 @@ config SPL_PAD_TO
config SPL_HAS_BSS_LINKER_SECTION
depends on SPL_FRAMEWORK
bool "Use a specific address for the BSS via the linker script"
default y if ARCH_SUNXI || ARCH_MX6 || ARCH_OMAP2PLUS || MIPS || RISCV
default y if ARCH_SUNXI || ARCH_MX6 || ARCH_OMAP2PLUS || MIPS || RISCV || ARCH_ZYNQMP
config SPL_BSS_START_ADDR
hex "Link address for the BSS within the SPL binary"
@ -118,6 +118,7 @@ config SPL_BSS_START_ADDR
default 0x81f80000 if ARCH_SUNXI && MACH_SUNIV
default 0x4ff80000 if ARCH_SUNXI && !(MACH_SUN9I || MACH_SUNIV)
default 0x2ff80000 if ARCH_SUNXI && MACH_SUN9I
default 0x1000 if ARCH_ZYNQMP
choice
prompt "Enforce SPL BSS limit"

17
common/spl/spl_fit.c
View File

@ -581,18 +581,25 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node,
{
const char *compatible;
int ret;
int devnum = 0;
int flags = 0;
debug("FPGA bitstream at: %x, size: %x\n",
(u32)fpga_image->load_addr, fpga_image->size);
compatible = fdt_getprop(ctx->fit, node, "compatible", NULL);
if (!compatible)
if (!compatible) {
warn_deprecated("'fpga' image without 'compatible' property");
else if (strcmp(compatible, "u-boot,fpga-legacy"))
printf("Ignoring compatible = %s property\n", compatible);
} else {
if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE))
flags = fpga_compatible2flag(devnum, compatible);
if (strcmp(compatible, "u-boot,fpga-legacy"))
debug("Ignoring compatible = %s property\n",
compatible);
}
ret = fpga_load(0, (void *)fpga_image->load_addr, fpga_image->size,
BIT_FULL);
ret = fpga_load(devnum, (void *)fpga_image->load_addr,
fpga_image->size, BIT_FULL, flags);
if (ret) {
printf("%s: Cannot load the image to the FPGA\n", __func__);
return ret;

1
configs/astro_mcf5373l_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_FPGA_PROG_FEEDBACK=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000

2
configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
View File

@ -27,8 +27,6 @@ CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x0
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0xfffffffc

4
configs/xilinx_versal_virt_defconfig
View File

@ -69,6 +69,8 @@ CONFIG_FPGA_XILINX=y
CONFIG_FPGA_VERSALPL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MAILBOX=y
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
@ -100,6 +102,8 @@ CONFIG_PHY_GIGE=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_XILINX_AXIMRMAC=y
CONFIG_ZYNQ_GEM=y
CONFIG_DM_RESET=y
CONFIG_RESET_ZYNQMP=y
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_XILINX_UARTLITE=y

1
configs/xilinx_zynqmp_mini_defconfig
View File

@ -63,3 +63,4 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set

3
configs/xilinx_zynqmp_mini_emmc0_defconfig
View File

@ -25,8 +25,6 @@ CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x0
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0xfffffffc
@ -80,3 +78,4 @@ CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set

3
configs/xilinx_zynqmp_mini_emmc1_defconfig
View File

@ -25,8 +25,6 @@ CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x0
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0xfffffffc
@ -80,3 +78,4 @@ CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set

3
configs/xilinx_zynqmp_mini_qspi_defconfig
View File

@ -24,8 +24,6 @@ CONFIG_REMAKE_ELF=y
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x0
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0xfffffffc
@ -84,3 +82,4 @@ CONFIG_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set

7
configs/xilinx_zynqmp_virt_defconfig
View File

@ -32,8 +32,6 @@ CONFIG_PREBOOT="run scsi_init;usb start"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x0
CONFIG_SPL_BSS_MAX_SIZE=0x80000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0xfffffffc
@ -139,6 +137,7 @@ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_GPIO_HOG=y
CONFIG_XILINX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_SLG7XL45106_I2C_GPO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_I2C_MUX=y
@ -180,10 +179,14 @@ CONFIG_PHY_FIXED=y
CONFIG_DM_ETH_PHY=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_ZYNQ_GEM=y
CONFIG_POWER_DOMAIN=y
CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_CADENCE_TTC=y
CONFIG_DM_RESET=y
CONFIG_RESET_ZYNQMP=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_RTC_ZYNQMP=y

7
doc/uImage.FIT/source_file_format.txt
View File

@ -184,7 +184,12 @@ the '/images' node should have the following layout:
Mandatory for types: "firmware", and "kernel".
- compatible : compatible method for loading image.
Mandatory for types: "fpga", and images that do not specify a load address.
To use the generic fpga loading routine, use "u-boot,fpga-legacy".
Supported compatible methods:
"u-boot,fpga-legacy" - the generic fpga loading routine.
"u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
Xilinx Zynq UltraScale+ (ZymqMP) device.
"u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq
UltraScale+ (ZynqMP) device.
Optional nodes:
- hash-1 : Each hash sub-node represents separate hash or checksum

22
drivers/firmware/firmware-zynqmp.c
View File

@ -70,12 +70,21 @@ int zynqmp_pmufw_config_close(void)
int zynqmp_pmufw_node(u32 id)
{
static bool skip_config;
int ret;
if (skip_config)
return 0;
/* Record power domain id */
xpm_configobject[NODE_ID_LOCATION] = id;
zynqmp_pmufw_load_config_object(xpm_configobject,
ret = zynqmp_pmufw_load_config_object(xpm_configobject,
sizeof(xpm_configobject));
if (ret && id == NODE_APU_0)
skip_config = true;
return 0;
}
@ -227,7 +236,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
* @cfg_obj: Pointer to the configuration object
* @size: Size of @cfg_obj in bytes
*/
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
{
int err;
u32 ret_payload[PAYLOAD_ARG_CNT];
@ -241,12 +250,12 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
0, ret_payload);
if (err == XST_PM_NO_ACCESS) {
printf("PMUFW no permission to change config object\n");
return;
return -EACCES;
}
if (err == XST_PM_ALREADY_CONFIGURED) {
debug("PMUFW Node is already configured\n");
return;
return -ENODEV;
}
if (err)
@ -257,6 +266,8 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_SPL_BUILD))
panic("PMUFW config object loading failed in EL3\n");
return 0;
}
static int zynqmp_power_probe(struct udevice *dev)
@ -282,6 +293,9 @@ static int zynqmp_power_probe(struct udevice *dev)
ret >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
ret & ZYNQMP_PM_VERSION_MINOR_MASK);
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
zynqmp_pmufw_node(NODE_APU_0);
return 0;
};

27
drivers/fpga/Kconfig
View File

@ -91,4 +91,31 @@ config FPGA_ZYNQPL
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq devices.
config SYS_FPGA_CHECK_CTRLC
bool "Allow Control-C to interrupt FPGA configuration"
depends on FPGA
help
User can interrupt FPGA configuration by pressing CTRL+C.
config SYS_FPGA_PROG_FEEDBACK
bool "Progress output during FPGA configuration"
depends on FPGA
default y if FPGA_VIRTEX2
help
Enable printing of hash marks during FPGA configuration.
config FPGA_LOAD_SECURE
bool "Enable loading secure bitstreams"
depends on FPGA
help
Enables the fpga loads() functions that are used to load secure
(authenticated or encrypted or both) bitstreams on to FPGA.
config SPL_FPGA_LOAD_SECURE
bool "Enable loading secure bitstreams for SPL"
depends on SPL_FPGA
help
Enables the fpga loads() functions that are used to load secure
(authenticated or encrypted or both) bitstreams on to FPGA.
endmenu

33
drivers/fpga/fpga.c
View File

@ -220,7 +220,7 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
}
#endif
#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
int fpga_loads(int devnum, const void *buf, size_t size,
struct fpga_secure_info *fpga_sec_info)
{
@ -252,7 +252,8 @@ int fpga_loads(int devnum, const void *buf, size_t size,
/*
* Generic multiplexing code
*/
int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype)
int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
int flags)
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
@ -263,7 +264,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype)
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_load(desc->devdesc, buf, bsize,
bstype);
bstype, flags);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
#endif
@ -356,3 +357,29 @@ int fpga_info(int devnum)
return fpga_dev_info(devnum);
}
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
int fpga_compatible2flag(int devnum, const char *compatible)
{
const fpga_desc * const desc = fpga_get_desc(devnum);
if (!desc)
return 0;
switch (desc->devtype) {
#if defined(CONFIG_FPGA_XILINX)
case fpga_xilinx:
{
xilinx_desc *xdesc = (xilinx_desc *)desc->devdesc;
if (xdesc->operations && xdesc->operations->str2flag)
return xdesc->operations->str2flag(xdesc, compatible);
}
#endif
default:
break;
}
return 0;
}
#endif

3
drivers/fpga/spartan2.c
View File

@ -15,7 +15,6 @@
#endif
#undef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
@ -41,7 +40,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
int ret_val = FPGA_FAIL;

2
drivers/fpga/spartan3.c
View File

@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
int ret_val = FPGA_FAIL;

2
drivers/fpga/versalpl.c
View File

@ -27,7 +27,7 @@ static ulong versal_align_dma_buffer(ulong *buf, u32 len)
}
static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
ulong bin_buf;
int ret;

13
drivers/fpga/virtex2.c
View File

@ -41,17 +41,6 @@
#define CONFIG_FPGA_DELAY()
#endif
#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#endif
/*
* Don't allow config cycle to be interrupted
*/
#ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
#undef CONFIG_SYS_FPGA_CHECK_CTRLC
#endif
/*
* Check for errors during configuration by default
*/
@ -94,7 +83,7 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
int ret_val = FPGA_FAIL;

8
drivers/fpga/xilinx.c
View File

@ -135,11 +135,11 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
dataptr += 4;
printf(" bytes in bitstream = %d\n", swapsize);
return fpga_load(devnum, dataptr, swapsize, bstype);
return fpga_load(devnum, dataptr, swapsize, bstype, 0);
}
int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
@ -151,7 +151,7 @@ int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
return FPGA_FAIL;
}
return desc->operations->load(desc, buf, bsize, bstype);
return desc->operations->load(desc, buf, bsize, bstype, flags);
}
#if defined(CONFIG_CMD_FPGA_LOADFS)
@ -172,7 +172,7 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
}
#endif
#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
struct fpga_secure_info *fpga_sec_info)
{

101
drivers/fpga/zynqmppl.c
View File

@ -9,6 +9,7 @@
#include <common.h>
#include <compiler.h>
#include <cpu_func.h>
#include <fpga.h>
#include <log.h>
#include <zynqmppl.h>
#include <zynqmp_firmware.h>
@ -199,53 +200,106 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
return 0;
}
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
static int zynqmp_check_compatible(xilinx_desc *desc, int flags)
{
/*
* If no flags set, the image may be legacy, but we need to
* signal caller this situation with specific error code.
*/
if (!flags)
return -ENODATA;
/* For legacy bitstream images no need for other methods exist */
if ((flags & desc->flags) && flags == FPGA_LEGACY)
return 0;
/*
* Other images are handled in secure callback loads(). Check
* callback existence besides image type support.
*/
if (desc->operations->loads && (flags & desc->flags))
return 0;
return -ENODEV;
}
#endif
static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
u32 swap = 0;
ulong bin_buf;
int ret;
u32 buf_lo, buf_hi;
u32 bsize_req = (u32)bsize;
u32 ret_payload[PAYLOAD_ARG_CNT];
bool xilfpga_old = false;
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
struct fpga_secure_info info = { 0 };
ret = zynqmp_check_compatible(desc, flags);
if (ret) {
if (ret != -ENODATA) {
puts("Missing loads() operation or unsupported bitstream type\n");
return FPGA_FAIL;
}
/* If flags is not set, the image treats as legacy */
flags = FPGA_LEGACY;
}
switch (flags) {
case FPGA_LEGACY:
break; /* Handle the legacy image later in this function */
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
case FPGA_XILINX_ZYNQMP_DDRAUTH:
/* DDR authentication */
info.authflag = ZYNQMP_FPGA_AUTH_DDR;
info.encflag = FPGA_NO_ENC_OR_NO_AUTH;
return desc->operations->loads(desc, buf, bsize, &info);
case FPGA_XILINX_ZYNQMP_ENC:
/* Encryption using device key */
info.authflag = FPGA_NO_ENC_OR_NO_AUTH;
info.encflag = FPGA_ENC_DEV_KEY;
return desc->operations->loads(desc, buf, bsize, &info);
#endif
default:
printf("Unsupported bitstream type %d\n", flags);
return FPGA_FAIL;
}
#endif
if (zynqmp_firmware_version() <= PMUFW_V1_0) {
puts("WARN: PMUFW v1.0 or less is detected\n");
puts("WARN: Not all bitstream formats are supported\n");
puts("WARN: Please upgrade PMUFW\n");
xilfpga_old = true;
if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
return FPGA_FAIL;
bsizeptr = (u32 *)&bsize;
flush_dcache_range((ulong)bsizeptr,
(ulong)bsizeptr + sizeof(size_t));
bsize_req = (u32)(uintptr_t)bsizeptr;
bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
} else {
bstype = 0;
}
bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
debug("%s called!\n", __func__);
flush_dcache_range(bin_buf, bin_buf + bsize);
buf_lo = (u32)bin_buf;
buf_hi = upper_32_bits(bin_buf);
if (xilfpga_old)
ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi, (u32)(uintptr_t)bsizeptr,
bstype, ret_payload);
else
ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi, (u32)bsize, 0, ret_payload);
ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi,
bsize_req, bstype, ret_payload);
if (ret)
printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
return ret;
}
#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
struct fpga_secure_info *fpga_sec_info)
{
@ -304,10 +358,25 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
return ret;
}
static int __maybe_unused zynqmp_str2flag(xilinx_desc *desc, const char *str)
{
if (!strncmp(str, "u-boot,fpga-legacy", 18))
return FPGA_LEGACY;
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
if (!strncmp(str, "u-boot,zynqmp-fpga-ddrauth", 26))
return FPGA_XILINX_ZYNQMP_DDRAUTH;
if (!strncmp(str, "u-boot,zynqmp-fpga-enc", 22))
return FPGA_XILINX_ZYNQMP_ENC;
#endif
return 0;
}
struct xilinx_fpga_op zynqmp_op = {
.load = zynqmp_load,
#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
.loads = zynqmp_loads,
#endif
.info = zynqmp_pcap_info,
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
.loads = zynqmp_loads,
.str2flag = zynqmp_str2flag,
#endif
};

2
drivers/fpga/zynqpl.c
View File

@ -371,7 +371,7 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
}
static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
unsigned long ts; /* Timestamp */
u32 isr_status, swap;

2
drivers/mailbox/Kconfig
View File

@ -54,7 +54,7 @@ config K3_SEC_PROXY
config ZYNQMP_IPI
bool "Xilinx ZynqMP IPI controller support"
depends on DM_MAILBOX && ARCH_ZYNQMP
depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL)
help
This enables support for the Xilinx ZynqMP Inter Processor Interrupt
communication controller.

2
drivers/mailbox/zynqmp-ipi.c
View File

@ -11,10 +11,10 @@
#include <dm.h>
#include <mailbox-uclass.h>
#include <dm/device_compat.h>
#include <mach/sys_proto.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <wait_bit.h>
#include <zynqmp_firmware.h>
/* IPI bitmasks, register base */
/* TODO: move reg base to DT */

4
drivers/mmc/zynq_sdhci.c
View File

@ -101,8 +101,8 @@ static const u8 mode2timing[] = {
[MMC_LEGACY] = MMC_TIMING_LEGACY,
[MMC_HS] = MMC_TIMING_MMC_HS,
[SD_HS] = MMC_TIMING_SD_HS,
[MMC_HS_52] = MMC_TIMING_UHS_SDR50,
[MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
[MMC_HS_52] = MMC_TIMING_MMC_HS,
[MMC_DDR_52] = MMC_TIMING_MMC_DDR52,
[UHS_SDR12] = MMC_TIMING_UHS_SDR12,
[UHS_SDR25] = MMC_TIMING_UHS_SDR25,
[UHS_SDR50] = MMC_TIMING_UHS_SDR50,

6
drivers/reset/Kconfig
View File

@ -199,11 +199,11 @@ config RESET_SCMI
protocol communication with a SCMI server.
config RESET_ZYNQMP
bool "Reset Driver for Xilinx ZynqMP SoC's"
bool "Reset Driver for Xilinx ZynqMP & Versal SoC's"
depends on DM_RESET && ZYNQMP_FIRMWARE
help
Support for reset controller on Xilinx ZynqMP SoC. Driver is only
passing request via Xilinx firmware interface to TF-A and PMU
Support for reset controller on Xilinx ZynqMP & Versal SoC's. Driver
is only passing request via Xilinx firmware interface to TF-A and PMU
firmware.
config RESET_DRA7

6
drivers/reset/reset-zynqmp.c
View File

@ -53,7 +53,7 @@ static int zynqmp_reset_request(struct reset_ctl *rst)
dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__,
rst, rst->id, priv->nr_reset);
if (rst->id > priv->nr_reset)
if (priv->nr_reset && rst->id > priv->nr_reset)
return -EINVAL;
return 0;
@ -63,8 +63,11 @@ static int zynqmp_reset_probe(struct udevice *dev)
{
struct zynqmp_reset_priv *priv = dev_get_priv(dev);
if (device_is_compatible(dev, "xlnx,zynqmp-reset")) {
priv->reset_id = ZYNQMP_RESET_ID;
priv->nr_reset = ZYNQMP_NR_RESETS;
}
return 0;
}
@ -76,6 +79,7 @@ const struct reset_ops zynqmp_reset_ops = {
static const struct udevice_id zynqmp_reset_ids[] = {
{ .compatible = "xlnx,zynqmp-reset" },
{ .compatible = "xlnx,versal-reset" },
{ }
};

2
drivers/serial/serial_zynq.c
View File

@ -75,7 +75,7 @@ static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
* Find acceptable values for baud generation.
*/
for (bdiv = 4; bdiv < 255; bdiv++) {
bgen = clock / (baud * (bdiv + 1));
bgen = DIV_ROUND_CLOSEST(clock, baud * (bdiv + 1));
if (bgen < 2 || bgen > 65535)
continue;

236
drivers/spi/xilinx_spi.c
View File

@ -19,6 +19,7 @@
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <spi-mem.h>
#include <asm/io.h>
#include <wait_bit.h>
#include <linux/bitops.h>
@ -73,7 +74,7 @@
#define XILSPI_MAX_XFER_BITS 8
#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
SPICR_SPE)
SPICR_SPE | SPICR_MASTER_INHIBIT)
#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
@ -119,6 +120,15 @@ static int xilinx_spi_probe(struct udevice *bus)
writel(SPISSR_RESET_VALUE, &regs->srr);
/*
* Reset RX & TX FIFO
* Enable Manual Slave Select Assertion,
* Set SPI controller into master mode, and enable it
*/
writel(SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST |
SPICR_MANUAL_SS | SPICR_MASTER_MODE | SPICR_SPE,
&regs->spicr);
return 0;
}
@ -136,7 +146,10 @@ static void spi_cs_deactivate(struct udevice *dev)
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
u32 reg;
reg = readl(&regs->spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST;
writel(reg, &regs->spicr);
writel(SPISSR_OFF, &regs->spissr);
}
@ -205,81 +218,24 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
return i;
}
static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
const void *dout, void *din)
static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len)
{
struct udevice *bus = dev_get_parent(dev);
struct udevice *bus = spi->dev->parent;
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
const unsigned char *txp = dout;
unsigned char *rxp = din;
u32 reg;
u32 txbytes = bytes;
u32 rxbytes = bytes;
u32 count, txbytes, rxbytes;
int reg, ret;
const unsigned char *txp = (const unsigned char *)dout;
unsigned char *rxp = (unsigned char *)din;
/*
* This loop runs two times. First time to send the command.
* Second time to transfer data. After transferring data,
* it sets txp to the initial value for the normal operation.
*/
for ( ; priv->startup < 2; priv->startup++) {
xilinx_spi_fill_txfifo(bus, txp, txbytes);
reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
txbytes = len;
rxbytes = len;
while (txbytes || rxbytes) {
/* Disable master transaction */
reg = readl(&regs->spicr) | SPICR_MASTER_INHIBIT;
writel(reg, &regs->spicr);
xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
txp = din;
if (priv->startup) {
spi_cs_deactivate(dev);
spi_cs_activate(dev, slave_plat->cs);
txp = dout;
}
}
}
static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
/* assume spi core configured to do 8 bit transfers */
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
unsigned char *rxp = din;
u32 txbytes = bytes;
u32 rxbytes = bytes;
u32 reg, count;
int ret;
debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
dev_seq(bus), slave_plat->cs, bitlen, bytes, flags);
if (bitlen == 0)
goto done;
if (bitlen % XILSPI_MAX_XFER_BITS) {
printf("XILSPI warning: Not a multiple of %d bits\n",
XILSPI_MAX_XFER_BITS);
flags |= SPI_XFER_END;
goto done;
}
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);
/*
* This is the work around for the startup block issue in
* the spi controller. SPI clock is passing through STARTUP
* block to FLASH. STARTUP block don't provide clock as soon
* as QSPI provides command. So first command fails.
*/
xilinx_spi_startup_block(dev, bytes, dout, din);
while (txbytes && rxbytes) {
count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
/* Enable master transaction */
reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
writel(reg, &regs->spicr);
txbytes -= count;
@ -293,21 +249,142 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
return ret;
}
debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
reg = readl(&regs->spicr) | SPICR_MASTER_INHIBIT;
writel(reg, &regs->spicr);
count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
rxbytes -= count;
if (rxp)
rxp += count;
debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
}
done:
if (flags & SPI_XFER_END)
spi_cs_deactivate(dev);
return 0;
}
static void xilinx_spi_startup_block(struct spi_slave *spi)
{
struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(spi->dev);
unsigned char txp;
unsigned char rxp[8];
/*
* Perform a dummy read as a work around for
* the startup block issue.
*/
spi_cs_activate(spi->dev, slave_plat->cs);
txp = 0x9f;
start_transfer(spi, (void *)&txp, NULL, 1);
start_transfer(spi, NULL, (void *)rxp, 6);
spi_cs_deactivate(spi->dev);
}
static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
const struct spi_mem_op *op)
{
struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(spi->dev);
static u32 startup;
u32 dummy_len, ret;
/*
* This is the work around for the startup block issue in
* the spi controller. SPI clock is passing through STARTUP
* block to FLASH. STARTUP block don't provide clock as soon
* as QSPI provides command. So first command fails.
*/
if (!startup) {
xilinx_spi_startup_block(spi);
startup++;
}
spi_cs_activate(spi->dev, slave_plat->cs);
if (op->cmd.opcode) {
ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
if (ret)
goto done;
}
if (op->addr.nbytes) {
int i;
u8 addr_buf[4];
for (i = 0; i < op->addr.nbytes; i++)
addr_buf[i] = op->addr.val >>
(8 * (op->addr.nbytes - i - 1));
ret = start_transfer(spi, (void *)addr_buf, NULL,
op->addr.nbytes);
if (ret)
goto done;
}
if (op->dummy.nbytes) {
dummy_len = (op->dummy.nbytes * op->data.buswidth) /
op->dummy.buswidth;
ret = start_transfer(spi, NULL, NULL, dummy_len);
if (ret)
goto done;
}
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN) {
ret = start_transfer(spi, NULL,
op->data.buf.in, op->data.nbytes);
} else {
ret = start_transfer(spi, op->data.buf.out,
NULL, op->data.nbytes);
}
if (ret)
goto done;
}
done:
spi_cs_deactivate(spi->dev);
return ret;
}
static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width)
{
u32 mode = slave->mode;
switch (width) {
case 1:
return 0;
case 2:
if (mode & SPI_RX_DUAL)
return 0;
break;
case 4:
if (mode & SPI_RX_QUAD)
return 0;
break;
}
return -EOPNOTSUPP;
}
bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth))
return false;
if (op->addr.nbytes &&
xilinx_qspi_check_buswidth(slave, op->addr.buswidth))
return false;
if (op->dummy.nbytes &&
xilinx_qspi_check_buswidth(slave, op->dummy.buswidth))
return false;
if (op->data.dir != SPI_MEM_NO_DATA &&
xilinx_qspi_check_buswidth(slave, op->data.buswidth))
return false;
return true;
}
static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
@ -343,12 +420,17 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
return 0;
}
static const struct spi_controller_mem_ops xilinx_spi_mem_ops = {
.exec_op = xilinx_spi_mem_exec_op,
.supports_op = xilinx_qspi_mem_exec_op,
};
static const struct dm_spi_ops xilinx_spi_ops = {
.claim_bus = xilinx_spi_claim_bus,
.release_bus = xilinx_spi_release_bus,
.xfer = xilinx_spi_xfer,
.set_speed = xilinx_spi_set_speed,
.set_mode = xilinx_spi_set_mode,
.mem_ops = &xilinx_spi_mem_ops,
};
static const struct udevice_id xilinx_spi_ids[] = {

73
drivers/spi/zynq_qspi.c
View File

@ -94,6 +94,7 @@ struct zynq_qspi_priv {
u8 mode;
u8 fifo_depth;
u32 freq; /* required frequency */
u32 max_hz;
const void *tx_buf;
void *rx_buf;
unsigned len;
@ -174,6 +175,16 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
}
static int zynq_qspi_child_pre_probe(struct udevice *bus)
{
struct spi_slave *slave = dev_get_parent_priv(bus);
struct zynq_qspi_priv *priv = dev_get_priv(bus->parent);
priv->max_hz = slave->max_hz;
return 0;
}
static int zynq_qspi_probe(struct udevice *bus)
{
struct zynq_qspi_plat *plat = dev_get_plat(bus);
@ -611,15 +622,12 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
uint32_t confr;
u8 baud_rate_val = 0;
if (speed > plat->frequency)
speed = plat->frequency;
if (!speed || speed > priv->max_hz)
speed = priv->max_hz;
/* Set the clock frequency */
confr = readl(&regs->cr);
if (speed == 0) {
/* Set baudrate x8, if the freq is 0 */
baud_rate_val = 0x2;
} else if (plat->speed_hz != speed) {
if (plat->speed_hz != speed) {
while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
((plat->frequency /
(2 << baud_rate_val)) > speed))
@ -668,6 +676,7 @@ static int zynq_qspi_exec_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
int op_len, pos = 0, ret, i;
u32 dummy_bytes = 0;
unsigned int flag = 0;
const u8 *tx_buf = NULL;
u8 *rx_buf = NULL;
@ -680,6 +689,11 @@ static int zynq_qspi_exec_op(struct spi_slave *slave,
}
op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
if (op->dummy.nbytes) {
op_len = op->cmd.nbytes + op->addr.nbytes +
op->dummy.nbytes / op->dummy.buswidth;
dummy_bytes = op->dummy.nbytes / op->dummy.buswidth;
}
u8 op_buf[op_len];
@ -693,8 +707,8 @@ static int zynq_qspi_exec_op(struct spi_slave *slave,
pos += op->addr.nbytes;
}
if (op->dummy.nbytes)
memset(op_buf + pos, 0xff, op->dummy.nbytes);
if (dummy_bytes)
memset(op_buf + pos, 0xff, dummy_bytes);
/* 1st transfer: opcode + address + dummy cycles */
/* Make sure to set END bit if no tx or rx data messages follow */
@ -719,8 +733,50 @@ static int zynq_qspi_exec_op(struct spi_slave *slave,
return 0;
}
static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width)
{
u32 mode = slave->mode;
switch (width) {
case 1:
return 0;
case 2:
if (mode & SPI_RX_DUAL)
return 0;
break;
case 4:
if (mode & SPI_RX_QUAD)
return 0;
break;
}
return -EOPNOTSUPP;
}
bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth))
return false;
if (op->addr.nbytes &&
zynq_qspi_check_buswidth(slave, op->addr.buswidth))
return false;
if (op->dummy.nbytes &&
zynq_qspi_check_buswidth(slave, op->dummy.buswidth))
return false;
if (op->data.dir != SPI_MEM_NO_DATA &&
zynq_qspi_check_buswidth(slave, op->data.buswidth))
return false;
return true;
}
static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
.exec_op = zynq_qspi_exec_op,
.supports_op = zynq_qspi_mem_exec_op,
};
static const struct dm_spi_ops zynq_qspi_ops = {
@ -746,4 +802,5 @@ U_BOOT_DRIVER(zynq_qspi) = {
.plat_auto = sizeof(struct zynq_qspi_plat),
.priv_auto = sizeof(struct zynq_qspi_priv),
.probe = zynq_qspi_probe,
.child_pre_probe = zynq_qspi_child_pre_probe,
};

1
include/configs/astro_mcf5373l.h
View File

@ -131,7 +131,6 @@
* it needs non-blocking CFI routines.
*/
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000
/* End of user parameters to be customized */

105
include/dt-bindings/reset/xlnx-versal-resets.h Normal file
View File

@ -0,0 +1,105 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_VERSAL_RESETS_H
#define _DT_BINDINGS_VERSAL_RESETS_H
#define VERSAL_RST_PMC_POR (0xc30c001U)
#define VERSAL_RST_PMC (0xc410002U)
#define VERSAL_RST_PS_POR (0xc30c003U)
#define VERSAL_RST_PL_POR (0xc30c004U)
#define VERSAL_RST_NOC_POR (0xc30c005U)
#define VERSAL_RST_FPD_POR (0xc30c006U)
#define VERSAL_RST_ACPU_0_POR (0xc30c007U)
#define VERSAL_RST_ACPU_1_POR (0xc30c008U)
#define VERSAL_RST_OCM2_POR (0xc30c009U)
#define VERSAL_RST_PS_SRST (0xc41000aU)
#define VERSAL_RST_PL_SRST (0xc41000bU)
#define VERSAL_RST_NOC (0xc41000cU)
#define VERSAL_RST_NPI (0xc41000dU)
#define VERSAL_RST_SYS_RST_1 (0xc41000eU)
#define VERSAL_RST_SYS_RST_2 (0xc41000fU)
#define VERSAL_RST_SYS_RST_3 (0xc410010U)
#define VERSAL_RST_FPD (0xc410011U)
#define VERSAL_RST_PL0 (0xc410012U)
#define VERSAL_RST_PL1 (0xc410013U)
#define VERSAL_RST_PL2 (0xc410014U)
#define VERSAL_RST_PL3 (0xc410015U)
#define VERSAL_RST_APU (0xc410016U)
#define VERSAL_RST_ACPU_0 (0xc410017U)
#define VERSAL_RST_ACPU_1 (0xc410018U)
#define VERSAL_RST_ACPU_L2 (0xc410019U)
#define VERSAL_RST_ACPU_GIC (0xc41001aU)
#define VERSAL_RST_RPU_ISLAND (0xc41001bU)
#define VERSAL_RST_RPU_AMBA (0xc41001cU)
#define VERSAL_RST_R5_0 (0xc41001dU)
#define VERSAL_RST_R5_1 (0xc41001eU)
#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU)
#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U)
#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U)
#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U)
#define VERSAL_RST_SYSMON_LPD (0xc410023U)
#define VERSAL_RST_PDMA_RST1 (0xc410024U)
#define VERSAL_RST_PDMA_RST0 (0xc410025U)
#define VERSAL_RST_ADMA (0xc410026U)
#define VERSAL_RST_TIMESTAMP (0xc410027U)
#define VERSAL_RST_OCM (0xc410028U)
#define VERSAL_RST_OCM2_RST (0xc410029U)
#define VERSAL_RST_IPI (0xc41002aU)
#define VERSAL_RST_SBI (0xc41002bU)
#define VERSAL_RST_LPD (0xc41002cU)
#define VERSAL_RST_QSPI (0xc10402dU)
#define VERSAL_RST_OSPI (0xc10402eU)
#define VERSAL_RST_SDIO_0 (0xc10402fU)
#define VERSAL_RST_SDIO_1 (0xc104030U)
#define VERSAL_RST_I2C_PMC (0xc104031U)
#define VERSAL_RST_GPIO_PMC (0xc104032U)
#define VERSAL_RST_GEM_0 (0xc104033U)
#define VERSAL_RST_GEM_1 (0xc104034U)
#define VERSAL_RST_SPARE (0xc104035U)
#define VERSAL_RST_USB_0 (0xc104036U)
#define VERSAL_RST_UART_0 (0xc104037U)
#define VERSAL_RST_UART_1 (0xc104038U)
#define VERSAL_RST_SPI_0 (0xc104039U)
#define VERSAL_RST_SPI_1 (0xc10403aU)
#define VERSAL_RST_CAN_FD_0 (0xc10403bU)
#define VERSAL_RST_CAN_FD_1 (0xc10403cU)
#define VERSAL_RST_I2C_0 (0xc10403dU)
#define VERSAL_RST_I2C_1 (0xc10403eU)
#define VERSAL_RST_GPIO_LPD (0xc10403fU)
#define VERSAL_RST_TTC_0 (0xc104040U)
#define VERSAL_RST_TTC_1 (0xc104041U)
#define VERSAL_RST_TTC_2 (0xc104042U)
#define VERSAL_RST_TTC_3 (0xc104043U)
#define VERSAL_RST_SWDT_FPD (0xc104044U)
#define VERSAL_RST_SWDT_LPD (0xc104045U)
#define VERSAL_RST_USB (0xc104046U)
#define VERSAL_RST_DPC (0xc208047U)
#define VERSAL_RST_PMCDBG (0xc208048U)
#define VERSAL_RST_DBG_TRACE (0xc208049U)
#define VERSAL_RST_DBG_FPD (0xc20804aU)
#define VERSAL_RST_DBG_TSTMP (0xc20804bU)
#define VERSAL_RST_RPU0_DBG (0xc20804cU)
#define VERSAL_RST_RPU1_DBG (0xc20804dU)
#define VERSAL_RST_HSDP (0xc20804eU)
#define VERSAL_RST_DBG_LPD (0xc20804fU)
#define VERSAL_RST_CPM_POR (0xc30c050U)
#define VERSAL_RST_CPM (0xc410051U)
#define VERSAL_RST_CPMDBG (0xc208052U)
#define VERSAL_RST_PCIE_CFG (0xc410053U)
#define VERSAL_RST_PCIE_CORE0 (0xc410054U)
#define VERSAL_RST_PCIE_CORE1 (0xc410055U)
#define VERSAL_RST_PCIE_DMA (0xc410056U)
#define VERSAL_RST_CMN (0xc410057U)
#define VERSAL_RST_L2_0 (0xc410058U)
#define VERSAL_RST_L2_1 (0xc410059U)
#define VERSAL_RST_ADDR_REMAP (0xc41005aU)
#define VERSAL_RST_CPI0 (0xc41005bU)
#define VERSAL_RST_CPI1 (0xc41005cU)
#define VERSAL_RST_XRAM (0xc30c05dU)
#define VERSAL_RST_AIE_ARRAY (0xc10405eU)
#define VERSAL_RST_AIE_SHIM (0xc10405fU)
#endif

4
include/fpga.h
View File

@ -20,6 +20,7 @@
/* device numbers must be non-negative */
#define FPGA_INVALID_DEVICE -1
#define FPGA_ENC_DEV_KEY 0
#define FPGA_ENC_USR_KEY 1
#define FPGA_NO_ENC_OR_NO_AUTH 2
@ -64,7 +65,7 @@ int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_is_partial_data(int devnum, size_t img_len);
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
bitstream_type bstype, int flags);
int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
int fpga_loads(int devnum, const void *buf, size_t size,
@ -75,5 +76,6 @@ int fpga_dump(int devnum, const void *buf, size_t bsize);
int fpga_info(int devnum);
const fpga_desc *const fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn);
int fpga_compatible2flag(int devnum, const char *compatible);
#endif /* _FPGA_H_ */

2
include/lmb.h
View File

@ -68,7 +68,7 @@ struct lmb_region {
struct lmb {
struct lmb_region memory;
struct lmb_region reserved;
#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
#if IS_ENABLED(CONFIG_LMB_MEMORY_REGIONS)
struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS];
struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS];
#endif

3
include/versalpl.h
View File

@ -14,7 +14,4 @@
extern struct xilinx_fpga_op versal_op;
#define XILINX_VERSAL_DESC \
{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
#endif /* _VERSALPL_H_ */

21
include/xilinx.h
View File

@ -37,6 +37,11 @@ typedef enum { /* typedef xilinx_family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */
/* FPGA bitstream supported types */
#define FPGA_LEGACY BIT(0)
#define FPGA_XILINX_ZYNQMP_DDRAUTH BIT(1)
#define FPGA_XILINX_ZYNQMP_ENC BIT(2)
typedef struct { /* typedef xilinx_desc */
xilinx_family family; /* part type */
xilinx_iface iface; /* interface type */
@ -45,21 +50,27 @@ typedef struct { /* typedef xilinx_desc */
int cookie; /* implementation specific cookie */
struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */
int flags; /* compatible flags */
} xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op {
int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
int (*load)(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype, int flags);
int (*loadfs)(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fpga_fsinfo);
int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize,
struct fpga_secure_info *fpga_sec_info);
int (*dump)(xilinx_desc *, const void *, size_t);
int (*info)(xilinx_desc *);
int (*dump)(xilinx_desc *desc, const void *buf, size_t bsize);
int (*info)(xilinx_desc *desc);
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
int (*str2flag)(xilinx_desc *desc, const char *string);
#endif
};
/* Generic Xilinx Functions
*********************************************************************/
int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
bitstream_type bstype);
bitstream_type bstype, int flags);
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int xilinx_info(xilinx_desc *desc);
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,

9
include/zynqmp_firmware.h
View File

@ -435,8 +435,6 @@ enum pm_gem_config_type {
#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
#define PMIO_NODE_ID_BASE 0x1410801B
#define PMIO_NODE_ID_BASE 0x1410801B
/*
* Return payload size
* Not every firmware call expects the same amount of return bytes, however the
@ -449,7 +447,7 @@ enum pm_gem_config_type {
unsigned int zynqmp_firmware_version(void);
int zynqmp_pmufw_node(u32 id);
int zynqmp_pmufw_config_close(void);
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
@ -492,4 +490,9 @@ enum zynqmp_pm_request_ack {
/* PM API versions */
#define PM_API_VERSION_2 2
struct zynqmp_ipi_msg {
size_t len;
u32 *buf;
};
#endif /* _ZYNQMP_FIRMWARE_H_ */

9
include/zynqmppl.h
View File

@ -25,7 +25,12 @@
extern struct xilinx_fpga_op zynqmp_op;
#define XILINX_ZYNQMP_DESC \
{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | \
FPGA_XILINX_ZYNQMP_DDRAUTH | \
FPGA_XILINX_ZYNQMP_ENC)
#else
#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
#endif
#endif /* _ZYNQMPPL_H_ */

2
lib/lmb.c
View File

@ -108,7 +108,7 @@ void lmb_init(struct lmb *lmb)
#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
lmb->memory.max = CONFIG_LMB_MAX_REGIONS;
lmb->reserved.max = CONFIG_LMB_MAX_REGIONS;
#else
#elif IS_ENABLED(CONFIG_LMB_MEMORY_REGIONS)
lmb->memory.max = CONFIG_LMB_MEMORY_REGIONS;
lmb->reserved.max = CONFIG_LMB_RESERVED_REGIONS;
lmb->memory.region = lmb->memory_regions;

1
scripts/config_whitelist.txt
View File

@ -743,7 +743,6 @@ CONFIG_SYS_FPGA_FTIM0
CONFIG_SYS_FPGA_FTIM1
CONFIG_SYS_FPGA_FTIM2
CONFIG_SYS_FPGA_FTIM3
CONFIG_SYS_FPGA_PROG_FEEDBACK
CONFIG_SYS_FPGA_SIZE
CONFIG_SYS_FPGA_WAIT
CONFIG_SYS_FSL_BMAN_ADDR

3
test/py/tests/test_bind.py
View File

@ -25,7 +25,7 @@ def in_tree(response, name, uclass, drv, depth, last_child):
return True
return False
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_bind')
def test_bind_unbind_with_node(u_boot_console):
@ -117,6 +117,7 @@ def get_next_line(tree, name):
break
return child_line
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_bind')
def test_bind_unbind_with_uclass(u_boot_console):
#bind /bind-test

8
test/py/tests/test_dm.py
View File

@ -33,3 +33,11 @@ def test_dm_static(u_boot_console):
response = u_boot_console.run_command('dm drivers')
for driver in drivers:
assert driver in response
@pytest.mark.buildconfigspec("cmd_dm")
def test_dm_uclass(u_boot_console):
response = u_boot_console.run_command("dm uclass")
@pytest.mark.buildconfigspec("cmd_dm")
def test_dm_devres(u_boot_console):
response = u_boot_console.run_command("dm devres")

151
tools/relocate-rela.c
View File

@ -16,10 +16,34 @@
#include <string.h>
#include "compiler.h"
#ifndef EM_AARCH64
#define EM_AARCH64 183
#endif
#ifndef R_AARCH64_RELATIVE
#define R_AARCH64_RELATIVE 1027
#endif
#ifndef EM_MICROBLAZE
#define EM_MICROBLAZE 189
#endif
#ifndef R_MICROBLAZE_NONE
#define R_MICROBLAZE_NONE 0
#endif
#ifndef R_MICROBLAZE_32
#define R_MICROBLAZE_32 1
#endif
#ifndef R_MICROBLAZE_REL
#define R_MICROBLAZE_REL 16
#endif
#ifndef R_MICROBLAZE_GLOB_DAT
#define R_MICROBLAZE_GLOB_DAT 18
#endif
static int ei_class;
static uint64_t rela_start, rela_end, text_base, dyn_start;
@ -43,10 +67,8 @@ static bool supported_rela(Elf64_Rela *rela)
uint32_t type = rela->r_info & mask;
switch (type) {
#ifdef R_AARCH64_RELATIVE
case R_AARCH64_RELATIVE:
return true;
#endif
default:
fprintf(stderr, "warning: unsupported relocation type %"
PRIu32 " at %" PRIx64 "\n",
@ -60,7 +82,9 @@ static int decode_elf64(FILE *felf, char **argv)
{
size_t size;
Elf64_Ehdr header;
uint64_t section_header_base, section_header_size, sh_offset, sh_size;
uint64_t section_header_base, section_header_size;
uint64_t sh_addr, sh_offset, sh_size;
Elf64_Half sh_index, sh_num;
Elf64_Shdr *sh_table; /* Elf symbol table */
int ret, i, machine;
char *sh_str;
@ -76,7 +100,7 @@ static int decode_elf64(FILE *felf, char **argv)
return 25;
}
machine = header.e_machine;
machine = le16_to_cpu(header.e_machine);
debug("Machine\t%d\n", machine);
if (machine != EM_AARCH64) {
@ -84,9 +108,10 @@ static int decode_elf64(FILE *felf, char **argv)
return 30;
}
text_base = header.e_entry;
section_header_base = header.e_shoff;
section_header_size = header.e_shentsize * header.e_shnum;
text_base = le64_to_cpu(header.e_entry);
section_header_base = le64_to_cpu(header.e_shoff);
section_header_size = le16_to_cpu(header.e_shentsize) *
le16_to_cpu(header.e_shnum);
sh_table = malloc(section_header_size);
if (!sh_table) {
@ -114,9 +139,9 @@ static int decode_elf64(FILE *felf, char **argv)
return 27;
}
sh_size = sh_table[header.e_shstrndx].sh_size;
debug("e_shstrndx\t0x%08x\n", header.e_shstrndx);
debug("sh_size\t\t0x%08lx\n", sh_size);
sh_index = le16_to_cpu(header.e_shstrndx);
sh_size = le64_to_cpu(sh_table[sh_index].sh_size);
debug("e_shstrndx %x, sh_size %lx\n", sh_index, sh_size);
sh_str = malloc(sh_size);
if (!sh_str) {
@ -130,9 +155,8 @@ static int decode_elf64(FILE *felf, char **argv)
* Specifies the byte offset from the beginning of the file
* to the first byte in the section.
*/
sh_offset = sh_table[header.e_shstrndx].sh_offset;
debug("sh_offset\t0x%08x\n", header.e_shnum);
sh_offset = le64_to_cpu(sh_table[sh_index].sh_offset);
sh_num = le16_to_cpu(header.e_shnum);
ret = fseek(felf, sh_offset, SEEK_SET);
if (ret) {
@ -153,18 +177,22 @@ static int decode_elf64(FILE *felf, char **argv)
return 30;
}
for (i = 0; i < header.e_shnum; i++) {
/* fprintf(stderr, "%s\n", sh_str + sh_table[i].sh_name); Debug only */
if (!strcmp(".rela.dyn", (sh_str + sh_table[i].sh_name))) {
for (i = 0; i < sh_num; i++) {
char *sh_name = sh_str + le32_to_cpu(sh_table[i].sh_name);
debug("%s\n", sh_name);
sh_addr = le64_to_cpu(sh_table[i].sh_addr);
sh_offset = le64_to_cpu(sh_table[i].sh_offset);
sh_size = le64_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
debug(" at addr\t0x%08x\n",
(unsigned int)sh_table[i].sh_addr);
debug(" at offset\t0x%08x\n",
(unsigned int)sh_table[i].sh_offset);
debug(" of size\t0x%08x\n",
(unsigned int)sh_table[i].sh_size);
rela_start = sh_table[i].sh_addr;
rela_end = rela_start + sh_table[i].sh_size;
debug(" at addr\t0x%08x\n", sh_addr);
debug(" at offset\t0x%08x\n", sh_offset);
debug(" of size\t0x%08x\n", sh_size);
rela_start = sh_addr;
rela_end = rela_start + sh_size;
break;
}
}
@ -188,7 +216,9 @@ static int decode_elf32(FILE *felf, char **argv)
{
size_t size;
Elf32_Ehdr header;
uint64_t section_header_base, section_header_size, sh_offset, sh_size;
uint64_t section_header_base, section_header_size;
uint32_t sh_addr, sh_offset, sh_size;
Elf32_Half sh_index, sh_num;
Elf32_Shdr *sh_table; /* Elf symbol table */
int ret, i, machine;
char *sh_str;
@ -204,7 +234,7 @@ static int decode_elf32(FILE *felf, char **argv)
return 25;
}
machine = header.e_machine;
machine = le16_to_cpu(header.e_machine);
debug("Machine %d\n", machine);
if (machine != EM_MICROBLAZE) {
@ -212,14 +242,10 @@ static int decode_elf32(FILE *felf, char **argv)
return 30;
}
text_base = header.e_entry;
section_header_base = header.e_shoff;
debug("Section header base %x\n", section_header_base);
section_header_size = header.e_shentsize * header.e_shnum;
debug("Section header size %d\n", section_header_size);
text_base = le32_to_cpu(header.e_entry);
section_header_base = le32_to_cpu(header.e_shoff);
section_header_size = le16_to_cpu(header.e_shentsize) *
le16_to_cpu(header.e_shnum);
sh_table = malloc(section_header_size);
if (!sh_table) {
@ -247,8 +273,9 @@ static int decode_elf32(FILE *felf, char **argv)
return 27;
}
sh_size = sh_table[header.e_shstrndx].sh_size;
debug("e_shstrndx %x, sh_size %lx\n", header.e_shstrndx, sh_size);
sh_index = le16_to_cpu(header.e_shstrndx);
sh_size = le32_to_cpu(sh_table[sh_index].sh_size);
debug("e_shstrndx %x, sh_size %lx\n", sh_index, sh_size);
sh_str = malloc(sh_size);
if (!sh_str) {
@ -262,9 +289,8 @@ static int decode_elf32(FILE *felf, char **argv)
* Specifies the byte offset from the beginning of the file
* to the first byte in the section.
*/
sh_offset = sh_table[header.e_shstrndx].sh_offset;
debug("sh_offset %x\n", header.e_shnum);
sh_offset = le32_to_cpu(sh_table[sh_index].sh_offset);
sh_num = le16_to_cpu(header.e_shnum);
ret = fseek(felf, sh_offset, SEEK_SET);
if (ret) {
@ -277,7 +303,7 @@ static int decode_elf32(FILE *felf, char **argv)
size = fread(sh_str, 1, sh_size, felf);
if (size != sh_size) {
fprintf(stderr, "%s: Can't read section: %lx/%lx\n",
fprintf(stderr, "%s: Can't read section: %lx/%x\n",
argv[0], size, sh_size);
free(sh_str);
free(sh_table);
@ -285,22 +311,29 @@ static int decode_elf32(FILE *felf, char **argv)
return 30;
}
for (i = 0; i < header.e_shnum; i++) {
debug("%s\n", sh_str + sh_table[i].sh_name);
if (!strcmp(".rela.dyn", (sh_str + sh_table[i].sh_name))) {
for (i = 0; i < sh_num; i++) {
char *sh_name = sh_str + le32_to_cpu(sh_table[i].sh_name);
debug("%s\n", sh_name);
sh_addr = le64_to_cpu(sh_table[i].sh_addr);
sh_offset = le64_to_cpu(sh_table[i].sh_offset);
sh_size = le64_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
debug(" at addr\t0x%08x\n", (unsigned int)sh_table[i].sh_addr);
debug(" at offset\t0x%08x\n", (unsigned int)sh_table[i].sh_offset);
debug(" of size\t0x%08x\n", (unsigned int)sh_table[i].sh_size);
rela_start = sh_table[i].sh_addr;
rela_end = rela_start + sh_table[i].sh_size;
debug(" at addr\t0x%08x\n", sh_addr);
debug(" at offset\t0x%08x\n", sh_offset);
debug(" of size\t0x%08x\n", sh_size);
rela_start = sh_addr;
rela_end = rela_start + sh_size;
}
if (!strcmp(".dynsym", (sh_str + sh_table[i].sh_name))) {
if (!strcmp(".dynsym", sh_name)) {
debug("Found section\t\".dynsym\"\n");
debug(" at addr\t0x%08x\n", (unsigned int)sh_table[i].sh_addr);
debug(" at offset\t0x%08x\n", (unsigned int)sh_table[i].sh_offset);
debug(" of size\t0x%08x\n", (unsigned int)sh_table[i].sh_size);
dyn_start = sh_table[i].sh_addr;
debug(" at addr\t0x%08x\n", sh_addr);
debug(" at offset\t0x%08x\n", sh_offset);
debug(" of size\t0x%08x\n", sh_size);
dyn_start = sh_addr;
}
}
@ -386,9 +419,9 @@ static int rela_elf64(char **argv, FILE *f)
return 4;
}
swrela.r_offset = cpu_to_le64(rela.r_offset);
swrela.r_info = cpu_to_le64(rela.r_info);
swrela.r_addend = cpu_to_le64(rela.r_addend);
swrela.r_offset = le64_to_cpu(rela.r_offset);
swrela.r_info = le64_to_cpu(rela.r_info);
swrela.r_addend = le64_to_cpu(rela.r_addend);
if (!supported_rela(&swrela))
continue;
@ -487,9 +520,9 @@ static int rela_elf32(char **argv, FILE *f)
PRIu32 " r_addend:\t%" PRIx32 "\n",
rela.r_offset, rela.r_info, rela.r_addend);
swrela.r_offset = cpu_to_le32(rela.r_offset);
swrela.r_info = cpu_to_le32(rela.r_info);
swrela.r_addend = cpu_to_le32(rela.r_addend);
swrela.r_offset = le32_to_cpu(rela.r_offset);
swrela.r_info = le32_to_cpu(rela.r_info);
swrela.r_addend = le32_to_cpu(rela.r_addend);
debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%"
PRIu32 " r_addend:\t%" PRIx32 "\n",