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clk: mediatek: rename CLK_DOMAIN_SCPSYS

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Rename CLK_DOMAIN_SCPSYS to CLK_MUX_DOMAIN_SCPSYS to make it more clear
that this flag only applies to MUX clocks and not other clock types.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-2-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner 2026-03-06 16:05:49 -06:00
parent f922929828
commit e40978fff3
5 changed files with 7 additions and 7 deletions
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2
drivers/clk/mediatek/clk-mt7622.c
View File

@ -362,7 +362,7 @@ static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_5 */
MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
CLK_DOMAIN_SCPSYS),
CLK_MUX_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),

6
drivers/clk/mediatek/clk-mt7623.c
View File

@ -701,12 +701,12 @@ static const struct mtk_composite top_muxes[] = {
MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
CLK_DOMAIN_SCPSYS),
CLK_MUX_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
CLK_DOMAIN_SCPSYS),
CLK_MUX_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
@ -745,7 +745,7 @@ static const struct mtk_composite top_muxes[] = {
MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
CLK_DOMAIN_SCPSYS),
CLK_MUX_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),

2
drivers/clk/mediatek/clk-mt7629.c
View File

@ -397,7 +397,7 @@ static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_5 */
MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15,
CLK_DOMAIN_SCPSYS),
CLK_MUX_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23),
MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),

2
drivers/clk/mediatek/clk-mtk.c
View File

@ -788,7 +788,7 @@ static int mtk_clk_mux_enable(struct clk *clk)
writel(val, priv->base + mux->gate_reg);
}
if (mux->flags & CLK_DOMAIN_SCPSYS) {
if (mux->flags & CLK_MUX_DOMAIN_SCPSYS) {
/* enable scpsys clock off control */
writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,

2
drivers/clk/mediatek/clk-mtk.h
View File

@ -22,7 +22,7 @@
#define CLK_PLL_HAVE_RST_BAR BIT(0)
#define CLK_DOMAIN_SCPSYS BIT(0)
#define CLK_MUX_DOMAIN_SCPSYS BIT(0)
#define CLK_MUX_SETCLR_UPD BIT(1)
#define CLK_GATE_SETCLR BIT(0)