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phy: samsung: add support for exynos7870 USB PHY
The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface. Add its dedicated variant enum, compatible, and init/exit functions. The PHY enable bit of Exynos7870's PHY is different in contrast to that of Exynos850 and most Exynos PHYs. To allow this change, a simple if condition is added in exynos_usbdrd_phy_isol() which changes the bitmask. Since the variant enum is required, the function argument is changed to accept the driver data itself. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Kaustabh Chakraborty
Minkyu Kang
parent
ae1e081f83
commit
e4001865ff
@ -21,6 +21,7 @@
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/* Offset of PMU register controlling USB PHY output isolation */
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#define EXYNOS_USBDRD_PHY_CONTROL 0x0704
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#define EXYNOS_PHY_ENABLE BIT(0)
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#define EXYNOS7870_PHY_ENABLE BIT(1)
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/* Exynos USB PHY registers */
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#define EXYNOS5_FSEL_9MHZ6 0x0
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@ -32,6 +33,88 @@
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#define EXYNOS5_FSEL_26MHZ 0x6
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#define EXYNOS5_FSEL_50MHZ 0x7
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/* Exynos5: USB DRD PHY registers */
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#define EXYNOS5_DRD_LINKSYSTEM 0x04
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#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
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#define LINKSYSTEM_FORCE_VBUSVALID BIT(8)
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#define LINKSYSTEM_FORCE_BVALID BIT(7)
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#define LINKSYSTEM_FLADJ GENMASK(6, 1)
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#define EXYNOS5_DRD_PHYUTMI 0x08
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#define PHYUTMI_UTMI_SUSPEND_COM_N BIT(12)
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#define PHYUTMI_UTMI_L1_SUSPEND_COM_N BIT(11)
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#define PHYUTMI_VBUSVLDEXTSEL BIT(10)
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#define PHYUTMI_VBUSVLDEXT BIT(9)
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#define PHYUTMI_TXBITSTUFFENH BIT(8)
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#define PHYUTMI_TXBITSTUFFEN BIT(7)
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#define PHYUTMI_OTGDISABLE BIT(6)
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#define PHYUTMI_IDPULLUP BIT(5)
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#define PHYUTMI_DRVVBUS BIT(4)
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#define PHYUTMI_DPPULLDOWN BIT(3)
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#define PHYUTMI_DMPULLDOWN BIT(2)
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#define PHYUTMI_FORCESUSPEND BIT(1)
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#define PHYUTMI_FORCESLEEP BIT(0)
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#define EXYNOS5_DRD_PHYCLKRST 0x10
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#define PHYCLKRST_EN_UTMISUSPEND BIT(31)
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#define PHYCLKRST_SSC_REFCLKSEL GENMASK(30, 23)
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#define PHYCLKRST_SSC_RANGE GENMASK(22, 21)
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#define PHYCLKRST_SSC_EN BIT(20)
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#define PHYCLKRST_REF_SSP_EN BIT(19)
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#define PHYCLKRST_REF_CLKDIV2 BIT(18)
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#define PHYCLKRST_MPLL_MULTIPLIER GENMASK(17, 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF 0x19
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF 0x32
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF 0x68
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF 0x7d
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#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF 0x02
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#define PHYCLKRST_FSEL_PIPE GENMASK(10, 8)
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#define PHYCLKRST_FSEL_UTMI GENMASK(7, 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ 0x27
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#define PHYCLKRST_FSEL_PAD_24MHZ 0x2a
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#define PHYCLKRST_FSEL_PAD_20MHZ 0x31
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#define PHYCLKRST_FSEL_PAD_19_2MHZ 0x38
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#define PHYCLKRST_RETENABLEN BIT(4)
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#define PHYCLKRST_REFCLKSEL GENMASK(3, 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK 0x2
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK 0x3
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#define PHYCLKRST_PORTRESET BIT(1)
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#define PHYCLKRST_COMMONONN BIT(0)
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#define EXYNOS5_DRD_PHYPARAM0 0x1c
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#define PHYPARAM0_REF_USE_PAD BIT(31)
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#define PHYPARAM0_REF_LOSLEVEL GENMASK(30, 26)
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#define PHYPARAM0_REF_LOSLEVEL_VAL 0x9
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#define PHYPARAM0_TXVREFTUNE GENMASK(25, 22)
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#define PHYPARAM0_TXRISETUNE GENMASK(21, 20)
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#define PHYPARAM0_TXRESTUNE GENMASK(19, 18)
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#define PHYPARAM0_TXPREEMPPULSETUNE BIT(17)
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#define PHYPARAM0_TXPREEMPAMPTUNE GENMASK(16, 15)
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#define PHYPARAM0_TXHSXVTUNE GENMASK(14, 13)
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#define PHYPARAM0_TXFSLSTUNE GENMASK(12, 9)
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#define PHYPARAM0_SQRXTUNE GENMASK(8, 6)
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#define PHYPARAM0_OTGTUNE GENMASK(5, 3)
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#define PHYPARAM0_COMPDISTUNE GENMASK(2, 0)
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#define EXYNOS5_DRD_LINKPORT 0x44
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#define LINKPORT_HOST_U3_PORT_DISABLE BIT(8)
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#define LINKPORT_HOST_U2_PORT_DISABLE BIT(7)
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#define LINKPORT_HOST_PORT_OVCR_U3 BIT(5)
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#define LINKPORT_HOST_PORT_OVCR_U2 BIT(4)
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#define LINKPORT_HOST_PORT_OVCR_U3_SEL BIT(3)
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#define LINKPORT_HOST_PORT_OVCR_U2_SEL BIT(2)
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/* Exynos7870: USB DRD PHY registers */
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#define EXYNOS7870_DRD_HSPHYCTRL 0x54
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#define HSPHYCTRL_PHYSWRSTALL BIT(31)
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#define HSPHYCTRL_SIDDQ BIT(6)
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#define HSPHYCTRL_PHYSWRST BIT(0)
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#define EXYNOS7870_DRD_HSPHYPLLTUNE 0x70
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#define HSPHYPLLTUNE_PLL_B_TUNE BIT(6)
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#define HSPHYPLLTUNE_PLL_I_TUNE GENMASK(5, 4)
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#define HSPHYPLLTUNE_PLL_P_TUNE GENMASK(3, 0)
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/* Exynos850: USB DRD PHY registers */
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#define EXYNOS850_DRD_LINKCTRL 0x04
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#define LINKCTRL_FORCE_QACT BIT(8)
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@ -67,6 +150,7 @@
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#define MHZ (KHZ * KHZ)
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enum exynos_usbdrd_phy_variant {
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EXYNOS7870_USBDRD_PHY,
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EXYNOS850_USBDRD_PHY,
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};
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@ -88,16 +172,20 @@ struct exynos_usbdrd_phy {
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enum exynos_usbdrd_phy_variant variant;
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};
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static void exynos_usbdrd_phy_isol(struct regmap *reg_pmu, bool isolate)
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static void exynos_usbdrd_phy_isol(struct exynos_usbdrd_phy *phy_drd,
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bool isolate)
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{
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unsigned int val;
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unsigned int mask = EXYNOS_PHY_ENABLE, val;
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if (!reg_pmu)
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if (!phy_drd->reg_pmu)
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return;
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val = isolate ? 0 : EXYNOS_PHY_ENABLE;
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regmap_update_bits(reg_pmu, EXYNOS_USBDRD_PHY_CONTROL,
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EXYNOS_PHY_ENABLE, val);
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if (phy_drd->variant == EXYNOS7870_USBDRD_PHY)
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mask = EXYNOS7870_PHY_ENABLE;
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val = isolate ? 0 : mask;
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regmap_update_bits(phy_drd->reg_pmu, EXYNOS_USBDRD_PHY_CONTROL,
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mask, val);
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}
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/*
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@ -138,6 +226,111 @@ static unsigned int exynos_rate_to_clk(unsigned long rate, u32 *reg)
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return 0;
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}
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static void exynos7870_usbdrd_utmi_init(struct phy *phy)
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{
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struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
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void __iomem *regs_base = phy_drd->reg_phy;
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u32 reg;
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reg = readl(regs_base + EXYNOS5_DRD_PHYCLKRST);
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/* Use PADREFCLK as ref clock */
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reg &= ~PHYCLKRST_REFCLKSEL;
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reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_PAD_REFCLK);
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/* Select ref clock rate */
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reg &= ~PHYCLKRST_FSEL_UTMI;
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reg &= ~PHYCLKRST_FSEL_PIPE;
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reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk);
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/* Enable suspend and reset the port */
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reg |= PHYCLKRST_EN_UTMISUSPEND;
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reg |= PHYCLKRST_COMMONONN;
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reg |= PHYCLKRST_PORTRESET;
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writel(reg, regs_base + EXYNOS5_DRD_PHYCLKRST);
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udelay(10);
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/* Clear the port reset bit */
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reg &= ~PHYCLKRST_PORTRESET;
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writel(reg, regs_base + EXYNOS5_DRD_PHYCLKRST);
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/* Change PHY PLL tune value */
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reg = readl(regs_base + EXYNOS7870_DRD_HSPHYPLLTUNE);
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if (phy_drd->extrefclk == EXYNOS5_FSEL_24MHZ)
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reg |= HSPHYPLLTUNE_PLL_B_TUNE;
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else
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reg &= ~HSPHYPLLTUNE_PLL_B_TUNE;
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reg &= ~HSPHYPLLTUNE_PLL_P_TUNE;
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reg |= FIELD_PREP(HSPHYPLLTUNE_PLL_P_TUNE, 14);
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writel(reg, regs_base + EXYNOS7870_DRD_HSPHYPLLTUNE);
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/* High-Speed PHY control */
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reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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reg &= ~HSPHYCTRL_SIDDQ;
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reg &= ~HSPHYCTRL_PHYSWRST;
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reg &= ~HSPHYCTRL_PHYSWRSTALL;
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writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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udelay(500);
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reg = readl(regs_base + EXYNOS5_DRD_LINKSYSTEM);
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/*
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* Setting the Frame length Adj value[6:1] to default 0x20
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* See xHCI 1.0 spec, 5.2.4
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*/
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reg |= LINKSYSTEM_XHCI_VERSION_CONTROL;
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reg &= ~LINKSYSTEM_FLADJ;
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reg |= FIELD_PREP(LINKSYSTEM_FLADJ, 0x20);
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/* Set VBUSVALID signal as the VBUS pad is not used */
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reg |= LINKSYSTEM_FORCE_BVALID;
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reg |= LINKSYSTEM_FORCE_VBUSVALID;
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writel(reg, regs_base + EXYNOS5_DRD_LINKSYSTEM);
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reg = readl(regs_base + EXYNOS5_DRD_PHYUTMI);
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/* Release force_sleep & force_suspend */
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reg &= ~PHYUTMI_FORCESLEEP;
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reg &= ~PHYUTMI_FORCESUSPEND;
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/* DP/DM pull down control */
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reg &= ~PHYUTMI_DMPULLDOWN;
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reg &= ~PHYUTMI_DPPULLDOWN;
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reg &= ~PHYUTMI_DRVVBUS;
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/* Set DP-pull up as the VBUS pad is not used */
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reg |= PHYUTMI_VBUSVLDEXTSEL;
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reg |= PHYUTMI_VBUSVLDEXT;
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/* Disable OTG block and VBUS valid comparator */
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reg |= PHYUTMI_OTGDISABLE;
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writel(reg, regs_base + EXYNOS5_DRD_PHYUTMI);
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/* Configure OVC IO usage */
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reg = readl(regs_base + EXYNOS5_DRD_LINKPORT);
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reg |= LINKPORT_HOST_PORT_OVCR_U3_SEL | LINKPORT_HOST_PORT_OVCR_U2_SEL;
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writel(reg, regs_base + EXYNOS5_DRD_LINKPORT);
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/* High-Speed PHY swrst */
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reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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reg |= HSPHYCTRL_PHYSWRST;
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writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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udelay(20);
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/* Clear the PHY swrst bit */
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reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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reg &= ~HSPHYCTRL_PHYSWRST;
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writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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reg = readl(regs_base + EXYNOS5_DRD_PHYPARAM0);
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reg &= ~(PHYPARAM0_TXVREFTUNE | PHYPARAM0_TXRISETUNE |
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PHYPARAM0_TXRESTUNE | PHYPARAM0_TXPREEMPPULSETUNE |
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PHYPARAM0_TXPREEMPAMPTUNE | PHYPARAM0_TXHSXVTUNE |
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PHYPARAM0_TXFSLSTUNE | PHYPARAM0_SQRXTUNE |
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PHYPARAM0_OTGTUNE | PHYPARAM0_COMPDISTUNE);
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reg |= FIELD_PREP_CONST(PHYPARAM0_TXVREFTUNE, 14) |
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FIELD_PREP_CONST(PHYPARAM0_TXRISETUNE, 1) |
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FIELD_PREP_CONST(PHYPARAM0_TXRESTUNE, 3) |
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FIELD_PREP_CONST(PHYPARAM0_TXPREEMPAMPTUNE, 0) |
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FIELD_PREP_CONST(PHYPARAM0_TXHSXVTUNE, 0) |
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FIELD_PREP_CONST(PHYPARAM0_TXFSLSTUNE, 3) |
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FIELD_PREP_CONST(PHYPARAM0_SQRXTUNE, 6) |
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FIELD_PREP_CONST(PHYPARAM0_OTGTUNE, 2) |
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FIELD_PREP_CONST(PHYPARAM0_COMPDISTUNE, 3);
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writel(reg, regs_base + EXYNOS5_DRD_PHYPARAM0);
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}
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static void exynos850_usbdrd_utmi_init(struct phy *phy)
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{
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struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
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@ -225,6 +418,33 @@ static void exynos850_usbdrd_utmi_init(struct phy *phy)
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writel(reg, regs_base + EXYNOS850_DRD_HSP);
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}
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static void exynos7870_usbdrd_utmi_exit(struct phy *phy)
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{
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struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
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void __iomem *regs_base = phy_drd->reg_phy;
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u32 reg;
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/*
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* Disable the VBUS signal and the ID pull-up resistor.
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* Enable force-suspend and force-sleep modes.
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*/
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reg = readl(regs_base + EXYNOS5_DRD_PHYUTMI);
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reg &= ~(PHYUTMI_DRVVBUS | PHYUTMI_VBUSVLDEXT | PHYUTMI_VBUSVLDEXTSEL);
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reg &= ~PHYUTMI_IDPULLUP;
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reg |= PHYUTMI_FORCESUSPEND | PHYUTMI_FORCESLEEP;
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writel(reg, regs_base + EXYNOS5_DRD_PHYUTMI);
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/* Power down PHY analog blocks */
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reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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reg |= HSPHYCTRL_SIDDQ;
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writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL);
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/* Clear VBUSVALID signal as the VBUS pad is not used */
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reg = readl(regs_base + EXYNOS5_DRD_LINKSYSTEM);
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reg &= ~(LINKSYSTEM_FORCE_BVALID | LINKSYSTEM_FORCE_VBUSVALID);
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writel(reg, regs_base + EXYNOS5_DRD_LINKSYSTEM);
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}
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static void exynos850_usbdrd_utmi_exit(struct phy *phy)
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{
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struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
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@ -261,6 +481,9 @@ static int exynos_usbdrd_phy_init(struct phy *phy)
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return ret;
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switch (phy_drd->variant) {
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case EXYNOS7870_USBDRD_PHY:
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exynos7870_usbdrd_utmi_init(phy);
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break;
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case EXYNOS850_USBDRD_PHY:
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exynos850_usbdrd_utmi_init(phy);
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break;
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@ -283,6 +506,9 @@ static int exynos_usbdrd_phy_exit(struct phy *phy)
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return ret;
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switch (phy_drd->variant) {
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case EXYNOS7870_USBDRD_PHY:
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exynos7870_usbdrd_utmi_exit(phy);
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break;
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case EXYNOS850_USBDRD_PHY:
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exynos850_usbdrd_utmi_exit(phy);
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break;
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@ -307,7 +533,7 @@ static int exynos_usbdrd_phy_power_on(struct phy *phy)
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return ret;
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/* Power-on PHY */
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exynos_usbdrd_phy_isol(phy_drd->reg_pmu, false);
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exynos_usbdrd_phy_isol(phy_drd, false);
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return 0;
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}
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@ -319,7 +545,7 @@ static int exynos_usbdrd_phy_power_off(struct phy *phy)
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dev_dbg(phy->dev, "Request to power_off usbdrd_phy phy\n");
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/* Power-off the PHY */
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exynos_usbdrd_phy_isol(phy_drd->reg_pmu, true);
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exynos_usbdrd_phy_isol(phy_drd, true);
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clk_disable_unprepare(phy_drd->core_clk);
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@ -390,6 +616,10 @@ static const struct phy_ops exynos_usbdrd_phy_ops = {
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};
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static const struct udevice_id exynos_usbdrd_phy_of_match[] = {
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{
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.compatible = "samsung,exynos7870-usbdrd-phy",
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.data = EXYNOS7870_USBDRD_PHY,
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},
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{
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.compatible = "samsung,exynos850-usbdrd-phy",
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.data = EXYNOS850_USBDRD_PHY,
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