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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

Browse Source 
Assorted fixes and tweaks, HUSH parser, preboot env variable, SMC
command enablement, s_init and 32bit/64bit code clean up, DBSC and APMU
remoteproc clean ups, UFS dev_phys_to_bus() remap support and SCIF R-Car
Gen5 support.
This commit is contained in:
Tom Rini 2026-04-09 16:34:38 -06:00
commit e2fa3e570f
13 changed files with 41 additions and 96 deletions
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11
arch/arm/mach-renesas/Makefile
View File

@ -9,10 +9,15 @@ obj-y += emac.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN5) += cpu_info-rcar.o
ifneq ($(CONFIG_ARM64),)
obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RCAR_GEN5) += cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RCAR_GEN3) += memmap-gen3.o
obj-$(CONFIG_RCAR_GEN4) += memmap-gen3.o
obj-$(CONFIG_RCAR_GEN5) += memmap-gen3.o
endif
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o

71
arch/arm/mach-renesas/lowlevel_init_gen3.S
View File

@ -30,74 +30,3 @@ ENTRY(save_boot_params)
stp x2, x3, [x8], #16
b save_boot_params_ret
ENDPROC(save_boot_params)
.pushsection .text.s_init, "ax"
WEAK(s_init)
ret
ENDPROC(s_init)
.popsection
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
#ifndef CONFIG_ARMV8_MULTIENTRY
/*
* For single-entry systems the lowlevel init is very simple.
*/
ldr x0, =GICD_BASE
bl gic_init_secure
#else /* CONFIG_ARMV8_MULTIENTRY is set */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
bl gic_init_secure
1:
#if defined(CONFIG_GICV3)
ldr x0, =GICR_BASE
bl gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
#endif
branch_if_master x0, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
ldr x0, =GICC_BASE
#endif
bl gic_wait_for_interrupt
#endif
/*
* All slaves will enter EL2 and optionally EL1.
*/
adr x4, lowlevel_in_el2
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el2
lowlevel_in_el2:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, lowlevel_in_el1
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el1
lowlevel_in_el1:
#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
bl s_init
2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)

4
board/renesas/common/gen3-spl.c
View File

@ -29,10 +29,6 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_UART;
}
void s_init(void)
{
}
void reset_cpu(void)
{
}

4
board/renesas/common/gen4-common.c
View File

@ -41,10 +41,12 @@ static void init_gic_v3(void)
writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
}
void s_init(void)
int mach_cpu_init(void)
{
if (current_el() == 3)
init_generic_timer();
return 0;
}
int board_early_init_f(void)

4
board/renesas/common/gen4-spl.c
View File

@ -82,7 +82,7 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
#define RTGRP3_BIT BIT(19)
#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
void s_init(void)
int mach_cpu_init(void)
{
/* Unlock CPG access */
writel(0x5A5AFFFF, CPGWPR);
@ -95,6 +95,8 @@ void s_init(void)
writel(0x00ff00ff, APMU_BASE + 0x18);
writel(0x00ff00ff, APMU_BASE + 0x1c);
clrbits_le32(APMU_BASE + 0x68, BIT(29));
return 0;
}
void reset_cpu(void)

4
board/renesas/common/gen5-common.c
View File

@ -37,10 +37,12 @@ static void init_gic_v3(void)
writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
}
void s_init(void)
int mach_cpu_init(void)
{
if (current_el() == 3)
init_generic_timer();
return 0;
}
int board_early_init_f(void)

5
board/renesas/common/rcar64-common.c
View File

@ -24,7 +24,8 @@ int dram_init(void)
{
int ret = fdtdec_setup_mem_size_base();
if (current_el() == 3 && gd->ram_base == 0x48000000) {
if (IS_ENABLED(CONFIG_ARM64) && current_el() == 3 &&
gd->ram_base == 0x48000000) {
/*
* If this U-Boot runs in EL3, make the bottom 128 MiB
* available for loading of follow up firmware blobs.
@ -44,7 +45,7 @@ int dram_init_banksize(void)
fdtdec_setup_memory_banksize();
if (current_el() != 3)
if (IS_ENABLED(CONFIG_ARM64) && current_el() != 3)
return 0;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {

3
configs/renesas_rcar.config
View File

@ -21,6 +21,8 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_HUSH_OLD_PARSER is not set
CONFIG_HUSH_MODERN_PARSER=y
CONFIG_MTD=y
CONFIG_OF_CONTROL=y
CONFIG_PROT_TCP_SACK=y
@ -28,5 +30,6 @@ CONFIG_RCAR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SERIAL_RX_BUFFER=y
CONFIG_SPI=y
CONFIG_USE_PREBOOT=y
CONFIG_VERSION_VARIABLE=y
CONFIG_WGET=y

1
configs/renesas_rcar64.config
View File

@ -1,6 +1,7 @@
#include <configs/renesas_rcar.config>
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_SMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_DM_THERMAL=y

2
drivers/remoteproc/Kconfig
View File

@ -45,7 +45,7 @@ config REMOTEPROC_RENESAS_APMU
select REMOTEPROC
depends on ARCH_RENESAS && RCAR_GEN4 && DM && OF_CONTROL
help
Say 'y' here to add support for Renesas R-Car Gen4 Cortex-A52
Say 'y' here to add support for Renesas R-Car Gen4 Cortex-R52
processor via the remoteproc framework.
config REMOTEPROC_SANDBOX

2
drivers/serial/serial_sh.c
View File

@ -59,7 +59,7 @@ static void sh_serial_init_generic(struct uart_port *port)
sci_out(port, SCSPTR, 0x0003);
#endif
#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) || IS_ENABLED(CONFIG_RCAR_GEN4)
#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) || IS_ENABLED(CONFIG_RCAR_GEN4) || IS_ENABLED(CONFIG_RCAR_GEN5)
if (port->type == PORT_HSCIF)
sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8);
#endif

24
drivers/ufs/ufs-uclass.c
View File

@ -19,6 +19,7 @@
#include <dm/device-internal.h>
#include <malloc.h>
#include <hexdump.h>
#include <phys2bus.h>
#include <scsi.h>
#include <ufs.h>
#include <asm/io.h>
@ -466,13 +467,13 @@ static int ufshcd_make_hba_operational(struct ufs_hba *hba)
ufshcd_disable_intr_aggr(hba);
/* Configure UTRL and UTMRL base address registers */
ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),
ufshcd_writel(hba, lower_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utrdl))),
REG_UTP_TRANSFER_REQ_LIST_BASE_L);
ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),
ufshcd_writel(hba, upper_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utrdl))),
REG_UTP_TRANSFER_REQ_LIST_BASE_H);
ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),
ufshcd_writel(hba, lower_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utmrdl))),
REG_UTP_TASK_REQ_LIST_BASE_L);
ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),
ufshcd_writel(hba, upper_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utmrdl))),
REG_UTP_TASK_REQ_LIST_BASE_H);
/*
@ -660,7 +661,7 @@ static void ufshcd_host_memory_configure(struct ufs_hba *hba)
u16 prdt_offset;
utrdlp = hba->utrdl;
cmd_desc_dma_addr = (dma_addr_t)hba->ucdl;
cmd_desc_dma_addr = dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->ucdl));
utrdlp->command_desc_base_addr_lo =
cpu_to_le32(lower_32_bits(cmd_desc_dma_addr));
@ -1612,12 +1613,15 @@ void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
ufshcd_cache_flush(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
}
static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
static inline void prepare_prdt_desc(struct ufs_hba *hba,
struct ufshcd_sg_entry *entry,
unsigned char *buf, ulong len)
{
dma_addr_t da = dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)buf);
entry->size = cpu_to_le32(len) | GENMASK(1, 0);
entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf));
entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf));
entry->base_addr = cpu_to_le32(lower_32_bits(da));
entry->upper_addr = cpu_to_le32(upper_32_bits(da));
}
static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
@ -1639,13 +1643,13 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
buf = pccb->pdata;
i = table_length;
while (--i) {
prepare_prdt_desc(&prd_table[table_length - i - 1], buf,
prepare_prdt_desc(hba, &prd_table[table_length - i - 1], buf,
MAX_PRDT_ENTRY - 1);
buf += MAX_PRDT_ENTRY;
datalen -= MAX_PRDT_ENTRY;
}
prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
prepare_prdt_desc(hba, &prd_table[table_length - i - 1], buf, datalen - 1);
req_desc->prd_table_length = table_length;
ufshcd_cache_flush(prd_table, sizeof(*prd_table) * table_length);

2
include/dbsc5.h
View File

@ -50,7 +50,7 @@ struct renesas_dbsc5_board_config {
u8 bdcfg_dm_swap[SLICE_CNT];
/* SoC ckeX([1][0]) -> MEM csY */
u8 bdcfg_cs_swap;
} ch[4];
} ch[DRAM_CH_CNT];
};
#endif /* __INCLUDE_DBSC5_H__ */