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am43xx: Do not allow EMIF to control DDR_RESET in rtconly config

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Prevent EMIF control of DDR_RESET line on DDR3 am43xx platforms for
am43xx_evm_rtconly_config. Without this DDR is unstable and can become
corrupted after multiple iterations of RTC+DDR mode.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[j-keerthy@ti.com Ported to latest master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Dave Gerlach 2018-03-17 13:24:30 +05:30 committed by Tom Rini
parent 7619badb9c
commit e18945ad22
1 changed files with 5 additions and 0 deletions
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5
arch/arm/mach-omap2/am33xx/emif4.c
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@ -95,8 +95,13 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
#ifndef CONFIG_SPL_RTC_DDR_SUPPORT
/* Allow EMIF to control DDR_RESET */ /* Allow EMIF to control DDR_RESET */
writel(0x00000000, &ddrctrl->ddrioctrl); writel(0x00000000, &ddrctrl->ddrioctrl);
#else
/* Override EMIF DDR_RESET control */
writel(0x80000000, &ddrctrl->ddrioctrl);
#endif /* CONFIG_SPL_RTC_DDR_SUPPORT */
#endif #endif
/* Program EMIF instance */ /* Program EMIF instance */