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arch: arm: dts: fsl-lx2160a.dtsi: sync serial nodes with Linux

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Sync the serial nodes of the LX2160A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ioana Ciornei 2023-03-15 13:04:16 +02:00 committed by Peng Fan
parent 853493b9f9
commit dea0f1a27f
3 changed files with 33 additions and 11 deletions
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11
arch/arm/dts/fsl-lx2160a-qds.dtsi
View File

@ -2,7 +2,7 @@
/* /*
* NXP LX2160AQDS common device tree source * NXP LX2160AQDS common device tree source
* *
* Copyright 2018-2020 NXP * Copyright 2018-2020, 2023 NXP
* *
*/ */
@ -11,6 +11,7 @@
/ { / {
aliases { aliases {
spi0 = &fspi; spi0 = &fspi;
serial0 = &uart0;
}; };
}; };
@ -286,3 +287,11 @@
&sata3 { &sata3 {
status = "okay"; status = "okay";
}; };
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

11
arch/arm/dts/fsl-lx2160a-rdb.dts
View File

@ -5,7 +5,7 @@
* Author: Priyanka Jain <priyanka.jain@nxp.com> * Author: Priyanka Jain <priyanka.jain@nxp.com>
* Sriram Dash <sriram.dash@nxp.com> * Sriram Dash <sriram.dash@nxp.com>
* *
* Copyright 2018 NXP * Copyright 2018, 2023 NXP
* *
*/ */
@ -18,6 +18,7 @@
compatible = "fsl,lx2160ardb", "fsl,lx2160a"; compatible = "fsl,lx2160ardb", "fsl,lx2160a";
aliases { aliases {
spi0 = &fspi; spi0 = &fspi;
serial0 = &uart0;
}; };
}; };
@ -137,3 +138,11 @@
&sata3 { &sata3 {
status = "okay"; status = "okay";
}; };
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

22
arch/arm/dts/fsl-lx2160a.dtsi
View File

@ -2,7 +2,7 @@
/* /*
* NXP lx2160a SOC common device tree source * NXP lx2160a SOC common device tree source
* *
* Copyright 2018-2021 NXP * Copyright 2018-2021, 2023 NXP
* *
*/ */
@ -35,30 +35,34 @@
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
uart0: serial@21c0000 { uart0: serial@21c0000 {
compatible = "arm,pl011"; compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21c0000 0x0 0x1000>; reg = <0x0 0x21c0000 0x0 0x1000>;
clocks = <&clockgen 4 0>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled"; status = "disabled";
}; };
uart1: serial@21d0000 { uart1: serial@21d0000 {
compatible = "arm,pl011"; compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21d0000 0x0 0x1000>; reg = <0x0 0x21d0000 0x0 0x1000>;
clocks = <&clockgen 4 0>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled"; status = "disabled";
}; };
uart2: serial@21e0000 { uart2: serial@21e0000 {
compatible = "arm,pl011"; compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21e0000 0x0 0x1000>; reg = <0x0 0x21e0000 0x0 0x1000>;
clocks = <&clockgen 4 0>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled"; status = "disabled";
}; };
uart3: serial@21f0000 { uart3: serial@21f0000 {
compatible = "arm,pl011"; compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21f0000 0x0 0x1000>; reg = <0x0 0x21f0000 0x0 0x1000>;
clocks = <&clockgen 4 0>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled"; status = "disabled";
}; };
}; };