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imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock

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The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li 2021-10-29 09:46:30 +08:00 committed by Stefano Babic
parent 0f9b10aaba
commit dc77d0f9fc
3 changed files with 18 additions and 0 deletions
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1
arch/arm/include/asm/arch-imx8ulp/cgc.h
View File

@ -152,6 +152,7 @@ void cgc1_soscdiv_init(void);
void cgc1_init_core_clk(void);
void cgc2_pll4_init(void);
void cgc2_ddrclk_config(u32 src, u32 div);
void cgc2_ddrclk_wait_unlock(void);
u32 cgc1_sosc_div(enum cgc_clk clk);
void cgc1_enet_stamp_sel(u32 clk_src);
void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd);

11
arch/arm/mach-imx/imx8ulp/cgc.c
View File

@ -269,12 +269,23 @@ void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div)
void cgc2_ddrclk_config(u32 src, u32 div)
{
/* If reg lock is set, wait until unlock by HW */
/* This lock is triggered by div updating and ddrclk halt status change, */
while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
;
writel((src << 28) | (div << 21), &cgc2_regs->ddrclk);
/* wait for DDRCLK switching done */
while (!(readl(&cgc2_regs->ddrclk) & BIT(27)))
;
}
void cgc2_ddrclk_wait_unlock(void)
{
while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
;
}
void cgc2_lpav_init(enum cgc_clk clk)
{
u32 i, scs, reg;

6
arch/arm/mach-imx/imx8ulp/clock.c
View File

@ -107,6 +107,9 @@ void init_clk_ddr(void)
/* enable ddr pcc */
writel(0xd0000000, PCC5_LPDDR4_ADDR);
/* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
cgc2_ddrclk_wait_unlock();
/* for debug */
/* setclkout_ddr(); */
}
@ -144,6 +147,9 @@ int set_ddr_clk(u32 phy_freq_mhz)
return -EINVAL;
}
/* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
cgc2_ddrclk_wait_unlock();
return 0;
}