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sunxi: extend R528/T113-s3/D1(s) DRAM initialisation
The T113-s4 SoC is using the same die as the T113-s3, but comes with 256MiB of co-packaged DRAM. Besides the doubled size, the DRAM chip seems to be connected slightly differently, which requires to use a different pin remapping. Extend the DRAM initialisation code to add support for the T113-S4 aka T113M4020DC0 by checking the SoC's CHIPID, which is stored in the first word of the SID efuses. Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li> Tested-by: John Watts <contact@jookia.org> Reviewed-by: John Watts <contact@jookia.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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@ -54,6 +54,11 @@ static void sid_read_ldoB_cal(const dram_para_t *para)
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clrsetbits_le32(0x3000150, 0xff00, reg << 8);
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}
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static uint32_t sid_read_soc_chipid(void)
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{
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return readl(SUNXI_SID_BASE + 0x00) & 0xffff;
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}
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static void dram_voltage_set(const dram_para_t *para)
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{
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int vol;
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@ -663,6 +668,11 @@ static void mctl_phy_ac_remapping(const dram_para_t *para,
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fuse = (readl(SUNXI_SID_BASE + 0x28) & 0xf00) >> 8;
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debug("DDR efuse: 0x%x\n", fuse);
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debug("SoC Chip ID: 0x%08x\n", sid_read_soc_chipid());
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/* No remapping needed on T113-s4 with 256MB co-packaged DRAM */
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if (sid_read_soc_chipid() == SUNXI_CHIPID_T113M4020DC0)
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return;
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if (para->dram_type == SUNXI_DRAM_TYPE_DDR2) {
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if (fuse == 15)
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@ -19,6 +19,17 @@ enum sunxi_dram_type {
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SUNXI_DRAM_TYPE_LPDDR3 = 7,
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};
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/*
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* Chip-IDs taken from
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* https://github.com/ua1arn/hftrx/blob/25d8cb9e4cfe1d7d0e4a2f641025c88a9ec5e758/inc/clocks.h#L250
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*/
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enum sunxi_soc_chipid {
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SUNXI_CHIPID_F133A = 0x5C00,
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SUNXI_CHIPID_D1S = 0x5E00,
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SUNXI_CHIPID_T113S3 = 0x6000,
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SUNXI_CHIPID_T113M4020DC0 = 0x7200,
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};
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/*
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* This structure contains a mixture of fixed configuration settings,
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* variables that are used at runtime to communicate settings between
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