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gpio: renesas: Access INDT, POSNEG, INEN registers via match data offsets
The Renesas R-Car Gen5 GPIO controller has INDT, POSNEG, INEN registers
at different offsets compared to previous generations. Introduce three
new entries in struct rcar_gpio_data {} match data to describe these
register offsets for each GPIO controller. Update the driver to access
these three registers through the match data offsets. No functional
change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
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01a15d7699
commit
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@ -18,9 +18,9 @@
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#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
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#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
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#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
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#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
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#define GPIO_OUTDT 0x08 /* General Output Register */
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#define GPIO_OUTDT 0x08 /* General Output Register */
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#define GPIO_INDT 0x0c /* General Input Register */
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#define GPIO_INDT_G2 0x0c /* General Input Register */
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#define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
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#define GPIO_POSNEG_G2 0x20 /* Positive/Negative Logic Select Register */
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#define GPIO_INEN 0x50 /* General Input Enable Register */
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#define GPIO_INEN_G4 0x50 /* General Input Enable Register */
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#define RCAR_MAX_GPIO_PER_BANK 32
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#define RCAR_MAX_GPIO_PER_BANK 32
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@ -30,6 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
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struct rcar_gpio_data {
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struct rcar_gpio_data {
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u32 quirks;
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u32 quirks;
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u32 indt_offset;
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u32 posneg_offset;
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u32 inen_offset;
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};
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};
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struct rcar_gpio_priv {
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struct rcar_gpio_priv {
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@ -40,6 +43,7 @@ struct rcar_gpio_priv {
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static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
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static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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{
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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const struct rcar_gpio_data *data = priv->data;
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const u32 bit = BIT(offset);
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const u32 bit = BIT(offset);
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/*
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/*
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@ -49,7 +53,7 @@ static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
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if (readl(priv->regs + GPIO_INOUTSEL) & bit)
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if (readl(priv->regs + GPIO_INOUTSEL) & bit)
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return !!(readl(priv->regs + GPIO_OUTDT) & bit);
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return !!(readl(priv->regs + GPIO_OUTDT) & bit);
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else
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else
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return !!(readl(priv->regs + GPIO_INDT) & bit);
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return !!(readl(priv->regs + data->indt_offset) & bit);
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}
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}
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static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
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static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
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@ -79,14 +83,14 @@ static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
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*/
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*/
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/* Configure postive logic in POSNEG */
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/* Configure postive logic in POSNEG */
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clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
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clrbits_le32(regs + data->posneg_offset, BIT(offset));
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/* Select "Input Enable/Disable" in INEN */
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/* Select "Input Enable/Disable" in INEN */
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if (data->quirks & RCAR_GPIO_HAS_INEN) {
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if (data->quirks & RCAR_GPIO_HAS_INEN) {
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if (output)
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if (output)
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clrbits_le32(regs + GPIO_INEN, BIT(offset));
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clrbits_le32(regs + data->inen_offset, BIT(offset));
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else
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else
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setbits_le32(regs + GPIO_INEN, BIT(offset));
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setbits_le32(regs + data->inen_offset, BIT(offset));
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}
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}
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/* Select "General Input/Output Mode" in IOINTSEL */
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/* Select "General Input/Output Mode" in IOINTSEL */
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@ -169,10 +173,15 @@ static int rcar_gpio_probe(struct udevice *dev)
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}
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}
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static const struct rcar_gpio_data rcar_gpio_gen2_data = {
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static const struct rcar_gpio_data rcar_gpio_gen2_data = {
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.indt_offset = GPIO_INDT_G2,
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.posneg_offset = GPIO_POSNEG_G2,
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};
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};
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static const struct rcar_gpio_data rcar_gpio_gen3_data = {
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static const struct rcar_gpio_data rcar_gpio_gen3_data = {
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.quirks = RCAR_GPIO_HAS_INEN,
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.quirks = RCAR_GPIO_HAS_INEN,
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.indt_offset = GPIO_INDT_G2,
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.posneg_offset = GPIO_POSNEG_G2,
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.inen_offset = GPIO_INEN_G4,
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};
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};
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static const struct udevice_id rcar_gpio_ids[] = {
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static const struct udevice_id rcar_gpio_ids[] = {
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