From bdf30e84909d8d99c2700a0fc6c3e799e3d8e2d4 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 5 Dec 2019 13:29:25 +0530 Subject: [PATCH 1/3] usb: cdns3: ep0: Fix build warnings related to cache ops Since, commit 62f9b6544728 ("common: Move older CPU functions to their own header") cache ops functions are declared in a separate header. Include the same to avoid build warnings. Signed-off-by: Vignesh Raghavendra --- drivers/usb/cdns3/ep0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c index 1903f611038..0b6d9cf7274 100644 --- a/drivers/usb/cdns3/ep0.c +++ b/drivers/usb/cdns3/ep0.c @@ -10,6 +10,7 @@ * Peter Chen */ +#include #include #include From 5c7fa84f4b356746a591cf2e726feeed11e1848e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 17 Dec 2019 10:37:19 +0100 Subject: [PATCH 2/3] MAINTAINERS: assign usb.c and and usb_kbd.c Marek is already maintaining USB. Assign files common/usb.c and common/usb_kbd.c to him. Signed-off-by: Heinrich Schuchardt --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d588b7d641..438fb225ab0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -883,6 +883,8 @@ M: Marek Vasut S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git F: drivers/usb/ +F: common/usb.c +F: common/usb_kbd.c USB xHCI M: Bin Meng From 5c207282f53f86ecbf8c25cb691030d8c643ba1c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 18 Dec 2019 13:00:02 +0530 Subject: [PATCH 3/3] usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko Signed-off-by: Jagan Teki --- drivers/usb/dwc3/core.c | 12 ++++++++---- drivers/usb/dwc3/core.h | 20 ++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 0f9a6328161..77c555e7692 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -622,15 +622,19 @@ static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev, /* Set dwc3 usb2 phy config */ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_PHYIF; - reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; switch (hsphy_mode) { case USBPHY_INTERFACE_MODE_UTMI: - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); break; case USBPHY_INTERFACE_MODE_UTMIW: - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); break; default: break; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index bff53e072b9..1c08a2c5b6e 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -162,18 +162,14 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) -#define DWC3_GUSB2PHYCFG_PHYIF BIT(3) - -/* Global USB2 PHY Configuration Mask */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) - -/* Global USB2 PHY Configuration Offset */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10 - -#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ - DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) -#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ - DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define USBTRDTIM_UTMI_8_BIT 9 +#define USBTRDTIM_UTMI_16_BIT 5 +#define UTMI_PHYIF_16_BIT 1 +#define UTMI_PHYIF_8_BIT 0 /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)