mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-11-04 02:11:25 +01:00
- Fix and improve microchip's clock driver to allow sync'ing DTS with linux - Improve the help message in "SBI_V02" Kconfig - Improve DTS property "isa-string" parsing rule
This commit is contained in:
Tom Rini
commit
d78cccb1ac
@ -257,16 +257,16 @@ config SBI_V01
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deprecated in future once legacy M-mode software are no longer in use.
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config SBI_V02
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bool "SBI v0.2 support"
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bool "SBI v0.2 or later support"
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depends on SBI
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help
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This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
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scalable and extendable to handle future needs for RISC-V supervisor
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interfaces. For example, with SBI v0.2 HSM extension, only a single
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hart need to boot and enter operating system. The booting hart can
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bring up secondary harts one by one afterwards.
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The SBI specification introduced the concept of extensions in version
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v0.2. With this configuration option U-Boot can detect and use SBI
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extensions. With the HSM extension introduced in SBI 0.2, only a
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single hart needs to boot and enter the operating system. The booting
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hart can bring up secondary harts one by one afterwards.
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Choose this option if OpenSBI v0.7 or above release is used together
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Choose this option if OpenSBI release v0.7 or above is used together
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with U-Boot.
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endchoice
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@ -36,6 +36,7 @@ static inline bool supports_extension(char ext)
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#ifdef CONFIG_CPU
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struct udevice *dev;
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char desc[32];
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int i;
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uclass_find_first_device(UCLASS_CPU, &dev);
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if (!dev) {
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@ -43,9 +44,16 @@ static inline bool supports_extension(char ext)
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return false;
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}
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if (!cpu_get_desc(dev, desc, sizeof(desc))) {
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/* skip the first 4 characters (rv32|rv64) */
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if (strchr(desc + 4, ext))
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return true;
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/*
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* skip the first 4 characters (rv32|rv64) and
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* check until underscore
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*/
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for (i = 4; i < sizeof(desc); i++) {
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if (desc[i] == '_' || desc[i] == '\0')
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break;
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if (desc[i] == ext)
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return true;
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}
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}
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return false;
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@ -54,6 +54,10 @@
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};
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&uart1 {
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status = "okay";
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};
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@ -170,6 +170,11 @@
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};
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};
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -225,16 +230,9 @@
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&cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
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};
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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clock-output-names = "msspllclk";
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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reg-names = "mss_sysreg";
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clocks = <&refclk>;
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#clock-cells = <1>;
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@ -21,3 +21,5 @@ CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_BOOTP_SEND_HOSTNAME=y
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CONFIG_DM_MTD=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET_SBI=y
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@ -1 +1 @@
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obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
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obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o mpfs_clk_msspll.o
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@ -11,34 +11,51 @@
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/microchip-mpfs-clock.h>
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#include <linux/err.h>
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#include "mpfs_clk.h"
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static int mpfs_clk_probe(struct udevice *dev)
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{
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int ret;
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struct clk *parent_clk = dev_get_priv(dev);
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struct clk clk_msspll = { .id = CLK_MSSPLL };
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void __iomem *base;
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u32 clk_rate;
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const char *parent_clk_name;
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struct clk *clk = dev_get_priv(dev);
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void __iomem *msspll_base;
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int ret;
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base = dev_read_addr_ptr(dev);
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base = dev_read_addr_index_ptr(dev, 0);
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if (!base)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, clk);
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ret = clk_get_by_index(dev, 0, parent_clk);
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if (ret)
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return ret;
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dev_read_u32(clk->dev, "clock-frequency", &clk_rate);
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parent_clk_name = clk->dev->name;
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/*
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* The original devicetrees for mpfs messed up & defined the msspll's
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* output as a fixed-frequency, 600 MHz clock & used that as the input
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* for the clock controller node. The msspll is however not a fixed
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* frequency clock and later devicetrees handled this properly. Check
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* the devicetree & if it is one of the fixed ones, register the msspll.
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* Otherwise, skip registering it & pass the reference clock directly
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* to the cfg clock registration function.
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*/
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msspll_base = dev_read_addr_index_ptr(dev, 1);
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if (msspll_base) {
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ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
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if (ret)
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return ret;
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ret = mpfs_clk_register_cfgs(base, clk_rate, parent_clk_name);
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clk_request(dev, &clk_msspll);
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parent_clk = &clk_msspll;
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}
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ret = mpfs_clk_register_cfgs(base, parent_clk);
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if (ret)
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return ret;
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ret = mpfs_clk_register_periphs(base, clk_rate, "clk_ahb");
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ret = mpfs_clk_register_periphs(base, dev);
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return ret;
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}
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@ -11,22 +11,26 @@
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* mpfs_clk_register_cfgs() - register configuration clocks
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*
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* @base: base address of the mpfs system register.
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* @clk_rate: the mpfs pll clock rate.
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* @parent_name: a pointer to parent clock name.
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* @parent: a pointer to parent clock.
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* Return: zero on success, or a negative error code.
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*/
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int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
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const char *parent_name);
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int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
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/**
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* mpfs_clk_register_msspll() - register the mss pll
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*
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* @base: base address of the mpfs system register.
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* @parent: a pointer to parent clock.
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* Return: zero on success, or a negative error code.
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*/
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int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent);
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/**
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* mpfs_clk_register_periphs() - register peripheral clocks
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*
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* @base: base address of the mpfs system register.
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* @clk_rate: the mpfs pll clock rate.
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* @parent_name: a pointer to parent clock name.
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* @dev: udevice representing the clock controller.
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* Return: zero on success, or a negative error code.
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*/
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int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
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const char *parent_name);
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int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev);
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/**
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* divider_get_val() - get the clock divider value
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*
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@ -117,8 +117,7 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
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CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
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};
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int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
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const char *parent_name)
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int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
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{
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int ret;
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int i, id, num_clks;
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@ -129,9 +128,9 @@ int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
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for (i = 0; i < num_clks; i++) {
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hw = &mpfs_cfg_clks[i].hw;
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mpfs_cfg_clks[i].sys_base = base;
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mpfs_cfg_clks[i].prate = clk_rate;
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mpfs_cfg_clks[i].prate = clk_get_rate(parent);
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name = mpfs_cfg_clks[i].cfg.name;
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ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent_name);
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ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent->dev->name);
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if (ret)
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ERR_PTR(ret);
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id = mpfs_cfg_clks[i].cfg.id;
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119
drivers/clk/microchip/mpfs_clk_msspll.c
Normal file
119
drivers/clk/microchip/mpfs_clk_msspll.c
Normal file
@ -0,0 +1,119 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Microchip Technology Inc.
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/microchip-mpfs-clock.h>
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#include <linux/err.h>
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#include "mpfs_clk.h"
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#define MPFS_MSSPLL_CLOCK "mpfs_msspll_clock"
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/* address offset of control registers */
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#define REG_MSSPLL_REF_CR 0x08u
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#define REG_MSSPLL_POSTDIV_CR 0x10u
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#define REG_MSSPLL_SSCG_2_CR 0x2Cu
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#define MSSPLL_FBDIV_SHIFT 0x00u
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#define MSSPLL_FBDIV_WIDTH 0x0Cu
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#define MSSPLL_REFDIV_SHIFT 0x08u
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#define MSSPLL_REFDIV_WIDTH 0x06u
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#define MSSPLL_POSTDIV_SHIFT 0x08u
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#define MSSPLL_POSTDIV_WIDTH 0x07u
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#define MSSPLL_FIXED_DIV 4u
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/**
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* struct mpfs_msspll_hw_clock
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* @id: index of the msspll clock
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* @name: the msspll clocks name
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* @reg_offset: offset to the core complex's output of the msspll
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* @shift: shift to the divider bit field of a msspll clock output
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* @width: width of the divider bit field of the msspll clock output
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* @flags: common clock framework flags
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* @prate: the reference clock rate
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* @hw: clock instance
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*/
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struct mpfs_msspll_hw_clock {
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void __iomem *base;
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unsigned int id;
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const char *name;
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u32 reg_offset;
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u32 shift;
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u32 width;
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u32 flags;
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u32 prate;
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struct clk hw;
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};
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#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
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static unsigned long mpfs_clk_msspll_recalc_rate(struct clk *hw)
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{
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struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
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void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
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void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
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void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
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u32 mult, ref_div, postdiv;
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unsigned long temp;
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mult = readl(mult_addr) >> MSSPLL_FBDIV_SHIFT;
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mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
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ref_div = readl(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
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ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
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postdiv = readl(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
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postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
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temp = msspll_hw->prate / (ref_div * MSSPLL_FIXED_DIV * postdiv);
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return temp * mult;
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}
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#define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \
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.id = _id, \
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.name = _name, \
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.shift = _shift, \
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.width = _width, \
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.reg_offset = _reg_offset, \
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.flags = _flags, \
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}
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static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
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CLK_PLL(CLK_MSSPLL, "clk_msspll", MSSPLL_FBDIV_SHIFT,
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MSSPLL_FBDIV_WIDTH, REG_MSSPLL_SSCG_2_CR, 0),
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};
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int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent)
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{
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int id, ret;
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const char *name;
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struct clk *hw;
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hw = &mpfs_msspll_clks[0].hw;
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mpfs_msspll_clks[0].base = base;
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mpfs_msspll_clks[0].prate = clk_get_rate(parent);
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name = mpfs_msspll_clks[0].name;
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ret = clk_register(hw, MPFS_MSSPLL_CLOCK, name, parent->dev->name);
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if (ret)
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ERR_PTR(ret);
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id = mpfs_msspll_clks[0].id;
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clk_dm(id, hw);
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return 0;
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}
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const struct clk_ops mpfs_msspll_clk_ops = {
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.get_rate = mpfs_clk_msspll_recalc_rate,
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};
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U_BOOT_DRIVER(mpfs_msspll_clock) = {
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.name = MPFS_MSSPLL_CLOCK,
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.id = UCLASS_CLK,
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.ops = &mpfs_msspll_clk_ops,
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};
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@ -29,12 +29,14 @@
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/**
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* struct mpfs_periph_clock - per instance of peripheral clock
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* @id: index of a peripheral clock
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* @parent_id: index of the parent clock
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* @name: name of a peripheral clock
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* @shift: shift to a peripheral clock bit field
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* @flags: common clock framework flags
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*/
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struct mpfs_periph_clock {
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unsigned int id;
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unsigned int parent_id;
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const char *name;
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u8 shift;
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unsigned long flags;
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@ -99,59 +101,66 @@ static int mpfs_periph_clk_disable(struct clk *hw)
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static ulong mpfs_periph_clk_recalc_rate(struct clk *hw)
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{
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struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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void __iomem *base_addr = periph_hw->sys_base;
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unsigned long rate;
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u32 val;
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val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT;
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val &= clk_div_mask(CFG_WIDTH);
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rate = periph_hw->prate / (1u << val);
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hw->rate = rate;
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return periph_hw->prate;
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return rate;
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}
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#define CLK_PERIPH(_id, _name, _shift, _flags) { \
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#define CLK_PERIPH(_id, _name, _parent_id, _shift, _flags) { \
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.periph.id = _id, \
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.periph.parent_id = _parent_id, \
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.periph.name = _name, \
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.periph.shift = _shift, \
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.periph.flags = _flags, \
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}
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/*
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* Critical clocks:
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* - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
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* trap handler
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* - CLK_MMUART0: reserved by the hss
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* - CLK_DDRC: provides clock to the ddr subsystem
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* - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
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* if the AHB interface clock is disabled
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* - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
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* clock domain crossers which provide the interface to the FPGA fabric. Disabling them
|
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* causes the FPGA fabric to go into reset.
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* - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
|
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*/
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static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
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CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL),
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CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0),
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CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0),
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CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0),
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CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0),
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CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0),
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CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0),
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CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0),
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CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0),
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CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0),
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CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0),
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CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0),
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CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0),
|
||||
CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0),
|
||||
CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0),
|
||||
CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0),
|
||||
CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0),
|
||||
CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0),
|
||||
CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0),
|
||||
CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0),
|
||||
CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0),
|
||||
CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0),
|
||||
CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0),
|
||||
CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", 25, 0),
|
||||
CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", 26, 0),
|
||||
CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", 27, 0),
|
||||
CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", 28, 0),
|
||||
CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0),
|
||||
CLK_PERIPH(CLK_ENVM, "clk_periph_envm", CLK_AHB, 0, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", CLK_AHB, 1, 0),
|
||||
CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", CLK_AHB, 2, 0),
|
||||
CLK_PERIPH(CLK_MMC, "clk_periph_mmc", CLK_AHB, 3, 0),
|
||||
CLK_PERIPH(CLK_TIMER, "clk_periph_timer", CLK_RTCREF, 4, 0),
|
||||
CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", CLK_AHB, 6, 0),
|
||||
CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", CLK_AHB, 7, 0),
|
||||
CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", CLK_AHB, 8, 0),
|
||||
CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", CLK_AHB, 9, 0),
|
||||
CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", CLK_AHB, 10, 0),
|
||||
CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", CLK_AHB, 11, 0),
|
||||
CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", CLK_AHB, 12, 0),
|
||||
CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", CLK_AHB, 13, 0),
|
||||
CLK_PERIPH(CLK_CAN0, "clk_periph_can0", CLK_AHB, 14, 0),
|
||||
CLK_PERIPH(CLK_CAN1, "clk_periph_can1", CLK_AHB, 15, 0),
|
||||
CLK_PERIPH(CLK_USB, "clk_periph_usb", CLK_AHB, 16, 0),
|
||||
CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", CLK_AHB, 19, 0),
|
||||
CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", CLK_AHB, 20, 0),
|
||||
CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", CLK_AHB, 21, 0),
|
||||
CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", CLK_AHB, 22, 0),
|
||||
CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", CLK_AHB, 23, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0),
|
||||
};
|
||||
|
||||
int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
|
||||
const char *parent_name)
|
||||
int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
int i, id, num_clks;
|
||||
@ -160,11 +169,14 @@ int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
|
||||
|
||||
num_clks = ARRAY_SIZE(mpfs_periph_clks);
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
struct clk parent = { .id = mpfs_periph_clks[i].periph.parent_id };
|
||||
|
||||
clk_request(dev, &parent);
|
||||
hw = &mpfs_periph_clks[i].hw;
|
||||
mpfs_periph_clks[i].sys_base = base;
|
||||
mpfs_periph_clks[i].prate = clk_rate;
|
||||
mpfs_periph_clks[i].prate = clk_get_rate(&parent);
|
||||
name = mpfs_periph_clks[i].periph.name;
|
||||
ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent_name);
|
||||
ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent.dev->name);
|
||||
if (ret)
|
||||
ERR_PTR(ret);
|
||||
id = mpfs_periph_clks[i].periph.id;
|
||||
|
||||
@ -42,4 +42,7 @@
|
||||
#define CLK_ATHENA 31
|
||||
#define CLK_CFM 32
|
||||
|
||||
#define CLK_RTCREF 33
|
||||
#define CLK_MSSPLL 34
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user