From 34be2ada130bc2fcad958794e1c6675625984c3a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 23 Sep 2022 03:31:22 +0200 Subject: [PATCH 1/7] ARM: dts: stm32: Remove buck3 regulator-always-on on AV96 In case the regulator-always-on is present in regulator DT node, the regulator is always reconfigured to the voltage set in DT on probe, even if regulator_set_value() has been called before. Drop the property from AV96 U-Boot DT and enable the regulator manually in code, as the board already reconfigures the Buck3 regulator in code per PMIC NVM content instead. Fixes: 0adf10a87b1 ("ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96") Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 4 ++++ board/dhelectronics/dh_stm32mp1/board.c | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index 5bed53e3fdb..b6fceb9ad58 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -102,6 +102,10 @@ hnp-srp-disable; }; +&vdd { + /delete-property/ regulator-always-on; +}; + &vdd_io { u-boot,dm-spl; }; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 2bc0d7b943a..05f884cfbfd 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -595,6 +595,7 @@ static void board_init_regulator_av96(void) /* Adjust Buck3 per preconfigured PMIC voltage from NVM. */ regulator_set_value(rdev, uv); + regulator_set_enable(rdev, true); } static void board_init_regulator(void) From 08e8495ee89ecb8cd5522eeba1225866c3af932d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Sep 2022 18:44:58 +0200 Subject: [PATCH 2/7] ARM: stm32: Enable btrfs support on DHSOM The btrfs filesystem provides advanced functionality like copy-on-write and snapshots, as well as metadata and data duplication and checksumming. Enable btrfs in U-Boot to permit even the primary partition to be btrfs and let system boot from it. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index f47e70be44a..67e238af3a1 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -79,6 +79,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=nor0" diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 02cce50691e..a630713f926 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -77,6 +77,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=nor0" From f8edb1e79c7b2470add9c3bb91fdf30260023a61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Sep 2022 18:46:31 +0200 Subject: [PATCH 3/7] ARM: dts: stm32: Drop extra newline from AV96 U-Boot extras DT Remove duplicate newline, no functional change. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index b6fceb9ad58..6dee51dc1c2 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -19,7 +19,6 @@ }; }; - ðernet0 { phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; From 0de10e2fe1d6c06e2142f492cce86aad501893b5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Sep 2022 18:50:00 +0200 Subject: [PATCH 4/7] ARM: dts: stm32: Add DHCOR based Testbench board Add DT for DHCOR Testbench board, which is a testbench for testing of DHCOR SoM during manufacturing. This is effectively a trimmed down version of AV96 board with CSI-2 bridge, HDMI bridge, WiFi, Audio and LEDs removed and used as GPIOs instead. Furthermore, the PMIC Buck3 is always configured from PMIC NVM to cater for both 1V8 and 3V3 SoM variant. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/Makefile | 3 +- .../stm32mp15xx-dhcor-testbench-u-boot.dtsi | 100 ++++++++++ arch/arm/dts/stm32mp15xx-dhcor-testbench.dts | 178 ++++++++++++++++++ board/dhelectronics/dh_stm32mp1/board.c | 40 ++-- .../dh_stm32mp1/u-boot-dhcor.its | 21 ++- 5 files changed, 325 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-testbench.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9b00b645091..54bff65e18c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1205,7 +1205,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcom-picoitx.dtb \ stm32mp15xx-dhcor-avenger96.dtb \ - stm32mp15xx-dhcor-drc-compact.dtb + stm32mp15xx-dhcor-drc-compact.dtb \ + stm32mp15xx-dhcor-testbench.dtb dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi new file mode 100644 index 00000000000..5b051b8ac45 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022 Marek Vasut + */ + +#include "stm32mp15xx-dhcor-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + usb0 = &usbotg_hs; + }; + + config { + dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>; + }; +}; + +ðernet0 { + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + + mdio0 { + ethernet-phy@7 { + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_b { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_c { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_b { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; + hnp-srp-disable; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts new file mode 100644 index 00000000000..c9163e1c028 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP15xx DHCOR Testbench"; + compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &uart7; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vdd { + /delete-property/ regulator-always-on; + regulator-min-microvolt = <1200000>; +}; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 05f884cfbfd..8d8104ad4bd 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -547,7 +547,7 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv) if (!prop || !len) return -ENODEV; - if (!strstr(prop, "avenger96")) + if (!strstr(prop, "avenger96") && !strstr(prop, "dhcor-testbench")) return -EINVAL; /* Read out STPMIC1 NVM and determine default Buck3 voltage. */ @@ -564,18 +564,32 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv) bucks_vout >>= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(3); bucks_vout &= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASK; - /* - * Avenger96 board comes in multiple regulator configurations: - * - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on - * boot and contains extra Enpirion EP53A8LQI DCDC converter which - * supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power. - * - rev.200L have Buck3 preconfigured to 1V8 operation and have no - * Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3. - */ - if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) - *uv = 2900000; - else - *uv = 1800000; + if (strstr(prop, "avenger96")) { + /* + * Avenger96 board comes in multiple regulator configurations: + * - rev.100 or rev.200 have Buck3 preconfigured to + * 3V3 operation on boot and contains extra Enpirion + * EP53A8LQI DCDC converter which supplies the IO. + * Reduce Buck3 voltage to 2V9 to not waste power. + * - rev.200L have Buck3 preconfigured to 1V8 operation + * and have no Enpirion EP53A8LQI DCDC anymore, the + * IO is supplied from Buck3. + */ + if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) + *uv = 2900000; + else + *uv = 1800000; + } else { + /* Testbench always respects Buck3 NVM settings */ + if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) + *uv = 3300000; + else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V0) + *uv = 3000000; + else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V8) + *uv = 1800000; + else /* STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 */ + *uv = 1200000; + } return 0; } diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its index de7dcb317f3..f9c1075616b 100644 --- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its +++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its @@ -18,13 +18,21 @@ fdt-1 { description = ".dtb"; - data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb"); + data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-testbench.dtb"); type = "flat_dt"; arch = "arm"; compression = "none"; }; fdt-2 { + description = ".dtb"; + data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + }; + + fdt-3 { description = ".dtb"; data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtb"); type = "flat_dt"; @@ -38,18 +46,25 @@ config-1 { /* DT+SoM+board model */ - description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1"; + description = "dh,stm32mp15xx-dhcor-testbench_somrev0_boardrev1"; firmware = "uboot"; fdt = "fdt-1"; }; config-2 { /* DT+SoM+board model */ - description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0"; + description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1"; firmware = "uboot"; fdt = "fdt-2"; }; + config-3 { + /* DT+SoM+board model */ + description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0"; + firmware = "uboot"; + fdt = "fdt-3"; + }; + /* Add 586-200..586-400 with fdt-2..fdt-4 here */ }; }; From 1587e689b328702f8d1f64a1e259de1443797f65 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 11 Oct 2022 22:42:44 +0200 Subject: [PATCH 5/7] ARM: dts: stm32: Fix and expand PLL configuration comments Fix the frequencies listed in PLL configuration comments to match the actual frequencies programmed into hardware. Furthermore, add a comment which explains how those frequencies are calculated, so it won't be necessary to look it up all over the datasheet and make more mistakes in the calculation in the future. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 17 ++++++++++++++++- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 17 ++++++++++++++++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 8a7156c93bf..b72a2f63f16 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -190,6 +190,21 @@ CLK_LPTIM45_LSE >; + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; @@ -208,7 +223,7 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ + /* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 19f4221f876..25a288b0475 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -144,6 +144,21 @@ CLK_LPTIM45_LSE >; + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; @@ -162,7 +177,7 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; From 637a370251d352ab86a35a8f6ebc7e22e4860adc Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 10 Oct 2022 10:56:14 +0200 Subject: [PATCH 6/7] ARM: dts: stm32: update SCMI dedicated file The PWR regulators don't need be removed as they are already deactivated. This patches is a alignment with the accepted patch in Linux device tree in commit a34b42f8690c ("ARM: dts: stm32: fix pwr regulators references to use scmi"). Fixes: 69ef98b209e7 ("ARM: dts: stm32mp15: alignment with v5.19") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15-scmi.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi index 37d4547b3e8..543f24c2f4f 100644 --- a/arch/arm/dts/stm32mp15-scmi.dtsi +++ b/arch/arm/dts/stm32mp15-scmi.dtsi @@ -103,7 +103,3 @@ /delete-node/ &clk_lse; /delete-node/ &clk_lsi; /delete-node/ &clk_csi; -/delete-node/ ®11; -/delete-node/ ®18; -/delete-node/ &usb33; -/delete-node/ &pwr_regulators; From c37a6684818d41051c54f814863429536aa972be Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 11 Oct 2022 16:44:26 +0200 Subject: [PATCH 7/7] stm32mp: fix compilation issue with DEBUG_UART Fix the compilation issue when CONFIG_DEBUG_UART is activated drivers/serial/serial_stm32.o: in function `debug_uart_init': drivers/serial/serial_stm32.c:291: undefined reference to \ `board_debug_uart_init' The board_debug_uart_init is needed for SPL boot, called in cpu.c::mach_cpu_init(); it is defined in board/st/stm32mp1/spl.c. But with the removal #ifdefs patch, the function debug_uart_init() is always compiled even if not present in the final U-Boot image. This patch adds a file to provided this function when DEBUG_UART and SPL are activated. Fixes: c8b2eef52b6c ("stm32mp15: tidy up #ifdefs in cpu.c") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/Kconfig.15x | 2 +- board/engicam/stm32mp1/Makefile | 2 ++ board/engicam/stm32mp1/spl.c | 25 ------------------------- board/st/stm32mp1/Makefile | 2 ++ board/st/stm32mp1/debug_uart.c | 29 +++++++++++++++++++++++++++++ board/st/stm32mp1/spl.c | 28 ---------------------------- 6 files changed, 34 insertions(+), 54 deletions(-) create mode 100644 board/st/stm32mp1/debug_uart.c diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x index d516270292a..5bd9b53a5d8 100644 --- a/arch/arm/mach-stm32mp/Kconfig.15x +++ b/arch/arm/mach-stm32mp/Kconfig.15x @@ -117,7 +117,7 @@ endif if DEBUG_UART config DEBUG_UART_BOARD_INIT - default y + default y if SPL # debug on UART4 by default config DEBUG_UART_BASE diff --git a/board/engicam/stm32mp1/Makefile b/board/engicam/stm32mp1/Makefile index 65560df2900..155d33f9eec 100644 --- a/board/engicam/stm32mp1/Makefile +++ b/board/engicam/stm32mp1/Makefile @@ -8,3 +8,5 @@ obj-y += spl.o else obj-y += stm32mp1.o endif + +obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += ../../st/stm32mp1/debug_uart.o diff --git a/board/engicam/stm32mp1/spl.c b/board/engicam/stm32mp1/spl.c index 3aa738b3faa..2b7779cc01d 100644 --- a/board/engicam/stm32mp1/spl.c +++ b/board/engicam/stm32mp1/spl.c @@ -6,7 +6,6 @@ */ #include -#include /* board early initialisation in board_f: need to use global variable */ static u32 opp_voltage_mv __section(".data"); @@ -22,27 +21,3 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_DEBUG_UART_BOARD_INIT -void board_debug_uart_init(void) -{ -#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) - -#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) -#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) - - /* UART4 clock enable */ - setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); - -#define GPIOG_BASE 0x50008000 - /* GPIOG clock enable */ - writel(BIT(6), RCC_MP_AHB4ENSETR); - /* GPIO configuration for ST boards: Uart4 TX = G11 */ - writel(0xffbfffff, GPIOG_BASE + 0x00); - writel(0x00006000, GPIOG_BASE + 0x24); -#else - -#error("CONFIG_DEBUG_UART_BASE: not supported value") - -#endif -} -#endif diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile index 65560df2900..f2d720b67b3 100644 --- a/board/st/stm32mp1/Makefile +++ b/board/st/stm32mp1/Makefile @@ -8,3 +8,5 @@ obj-y += spl.o else obj-y += stm32mp1.o endif + +obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += debug_uart.o diff --git a/board/st/stm32mp1/debug_uart.c b/board/st/stm32mp1/debug_uart.c new file mode 100644 index 00000000000..24e3f9f2201 --- /dev/null +++ b/board/st/stm32mp1/debug_uart.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) +#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) + +#define GPIOG_BASE 0x50008000 + +void board_debug_uart_init(void) +{ + if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) { + /* UART4 clock enable */ + setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + + /* GPIOG clock enable */ + writel(BIT(6), RCC_MP_AHB4ENSETR); + /* GPIO configuration for ST boards: Uart4 TX = G11 */ + writel(0xffbfffff, GPIOG_BASE + 0x00); + writel(0x00006000, GPIOG_BASE + 0x24); + } +} diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index 8e4549a1b35..747ec7e445a 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -5,11 +5,7 @@ #include #include -#include -#include #include -#include -#include #include "../common/stpmic1.h" /* board early initialisation in board_f: need to use global variable */ @@ -29,27 +25,3 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_DEBUG_UART_BOARD_INIT -void board_debug_uart_init(void) -{ -#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) - -#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) -#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) - - /* UART4 clock enable */ - setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); - -#define GPIOG_BASE 0x50008000 - /* GPIOG clock enable */ - writel(BIT(6), RCC_MP_AHB4ENSETR); - /* GPIO configuration for ST boards: Uart4 TX = G11 */ - writel(0xffbfffff, GPIOG_BASE + 0x00); - writel(0x00006000, GPIOG_BASE + 0x24); -#else - -#error("CONFIG_DEBUG_UART_BASE: not supported value") - -#endif -} -#endif