pci: imx: Pass driver private data around

Pass the driver private data around the driver as much as possible, instead
of having it as a static global variable. This is done in preparation for
the DM conversion, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Marek Vasut 2019-06-09 03:50:54 +02:00 committed by Stefano Babic
parent 90f87fb525
commit d2cc2e86f8

View File

@ -97,13 +97,6 @@ struct imx_pcie_priv {
void __iomem *cfg_base; void __iomem *cfg_base;
}; };
static struct imx_pcie_priv imx_pcie_priv = {
.dbi_base = (void __iomem *)MX6_DBI_ADDR,
.cfg_base = (void __iomem *)MX6_ROOT_ADDR,
};
static struct imx_pcie_priv *priv = &imx_pcie_priv;
/* /*
* PHY access functions * PHY access functions
*/ */
@ -237,7 +230,7 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
return 0; return 0;
} }
static int imx6_pcie_link_up(void) static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
{ {
u32 rc, ltssm; u32 rc, ltssm;
int rx_valid, temp; int rx_valid, temp;
@ -282,7 +275,7 @@ static int imx6_pcie_link_up(void)
/* /*
* iATU region setup * iATU region setup
*/ */
static int imx_pcie_regions_setup(void) static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
{ {
/* /*
* i.MX6 defines 16MB in the AXI address map for PCIe. * i.MX6 defines 16MB in the AXI address map for PCIe.
@ -325,7 +318,8 @@ static int imx_pcie_regions_setup(void)
/* /*
* PCI Express accessors * PCI Express accessors
*/ */
static void __iomem *get_bus_address(pci_dev_t d, int where) static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
pci_dev_t d, int where)
{ {
void __iomem *va_address; void __iomem *va_address;
@ -392,6 +386,7 @@ static void imx_pcie_fix_dabt_handler(bool set)
static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 *val) int where, u32 *val)
{ {
struct imx_pcie_priv *priv = hose->priv_data;
void __iomem *va_address; void __iomem *va_address;
int ret; int ret;
@ -401,7 +396,7 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
return 0; return 0;
} }
va_address = get_bus_address(d, where); va_address = get_bus_address(priv, d, where);
/* /*
* Read the PCIe config space. We must replace the DABT handler * Read the PCIe config space. We must replace the DABT handler
@ -421,6 +416,7 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 val) int where, u32 val)
{ {
struct imx_pcie_priv *priv = hose->priv_data;
void __iomem *va_address = NULL; void __iomem *va_address = NULL;
int ret; int ret;
@ -428,7 +424,7 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
if (ret) if (ret)
return ret; return ret;
va_address = get_bus_address(d, where); va_address = get_bus_address(priv, d, where);
/* /*
* Write the PCIe config space. We must replace the DABT handler * Write the PCIe config space. We must replace the DABT handler
@ -445,7 +441,8 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
/* /*
* Initial bus setup * Initial bus setup
*/ */
static int imx6_pcie_assert_core_reset(bool prepare_for_boot) static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
bool prepare_for_boot)
{ {
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -617,17 +614,17 @@ static int imx6_pcie_deassert_core_reset(void)
return 0; return 0;
} }
static int imx_pcie_link_up(void) static int imx_pcie_link_up(struct imx_pcie_priv *priv)
{ {
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
uint32_t tmp; uint32_t tmp;
int count = 0; int count = 0;
imx6_pcie_assert_core_reset(false); imx6_pcie_assert_core_reset(priv, false);
imx6_pcie_init_phy(); imx6_pcie_init_phy();
imx6_pcie_deassert_core_reset(); imx6_pcie_deassert_core_reset();
imx_pcie_regions_setup(); imx_pcie_regions_setup(priv);
/* /*
* By default, the subordinate is set equally to the secondary * By default, the subordinate is set equally to the secondary
@ -654,7 +651,7 @@ static int imx_pcie_link_up(void)
/* LTSSM enable, starting link. */ /* LTSSM enable, starting link. */
setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
while (!imx6_pcie_link_up()) { while (!imx6_pcie_link_up(priv)) {
udelay(10); udelay(10);
count++; count++;
if (count >= 4000) { if (count >= 4000) {
@ -671,6 +668,13 @@ static int imx_pcie_link_up(void)
return 0; return 0;
} }
static struct imx_pcie_priv imx_pcie_priv = {
.dbi_base = (void __iomem *)MX6_DBI_ADDR,
.cfg_base = (void __iomem *)MX6_ROOT_ADDR,
};
static struct imx_pcie_priv *priv = &imx_pcie_priv;
void imx_pcie_init(void) void imx_pcie_init(void)
{ {
/* Static instance of the controller. */ /* Static instance of the controller. */
@ -680,6 +684,8 @@ void imx_pcie_init(void)
memset(&pcc, 0, sizeof(pcc)); memset(&pcc, 0, sizeof(pcc));
hose->priv_data = priv;
/* PCI I/O space */ /* PCI I/O space */
pci_set_region(&hose->regions[0], pci_set_region(&hose->regions[0],
MX6_IO_ADDR, MX6_IO_ADDR, MX6_IO_ADDR, MX6_IO_ADDR,
@ -706,7 +712,7 @@ void imx_pcie_init(void)
imx_pcie_write_config); imx_pcie_write_config);
/* Start the controller. */ /* Start the controller. */
ret = imx_pcie_link_up(); ret = imx_pcie_link_up(priv);
if (!ret) { if (!ret) {
pci_register_hose(hose); pci_register_hose(hose);
@ -716,7 +722,7 @@ void imx_pcie_init(void)
void imx_pcie_remove(void) void imx_pcie_remove(void)
{ {
imx6_pcie_assert_core_reset(true); imx6_pcie_assert_core_reset(priv, true);
} }
/* Probe function. */ /* Probe function. */