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pci: imx: Pass driver private data around
Pass the driver private data around the driver as much as possible, instead of having it as a static global variable. This is done in preparation for the DM conversion, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -97,13 +97,6 @@ struct imx_pcie_priv {
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void __iomem *cfg_base;
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void __iomem *cfg_base;
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};
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};
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static struct imx_pcie_priv imx_pcie_priv = {
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.dbi_base = (void __iomem *)MX6_DBI_ADDR,
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.cfg_base = (void __iomem *)MX6_ROOT_ADDR,
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};
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static struct imx_pcie_priv *priv = &imx_pcie_priv;
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/*
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/*
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* PHY access functions
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* PHY access functions
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*/
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*/
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@ -237,7 +230,7 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
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return 0;
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return 0;
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}
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}
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static int imx6_pcie_link_up(void)
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static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
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{
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{
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u32 rc, ltssm;
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u32 rc, ltssm;
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int rx_valid, temp;
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int rx_valid, temp;
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@ -282,7 +275,7 @@ static int imx6_pcie_link_up(void)
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/*
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/*
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* iATU region setup
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* iATU region setup
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*/
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*/
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static int imx_pcie_regions_setup(void)
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static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
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{
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{
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/*
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/*
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* i.MX6 defines 16MB in the AXI address map for PCIe.
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* i.MX6 defines 16MB in the AXI address map for PCIe.
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@ -325,7 +318,8 @@ static int imx_pcie_regions_setup(void)
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/*
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/*
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* PCI Express accessors
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* PCI Express accessors
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*/
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*/
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static void __iomem *get_bus_address(pci_dev_t d, int where)
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static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
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pci_dev_t d, int where)
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{
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{
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void __iomem *va_address;
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void __iomem *va_address;
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@ -392,6 +386,7 @@ static void imx_pcie_fix_dabt_handler(bool set)
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static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 *val)
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int where, u32 *val)
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{
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{
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struct imx_pcie_priv *priv = hose->priv_data;
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void __iomem *va_address;
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void __iomem *va_address;
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int ret;
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int ret;
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@ -401,7 +396,7 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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return 0;
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return 0;
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}
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}
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va_address = get_bus_address(d, where);
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va_address = get_bus_address(priv, d, where);
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/*
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/*
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* Read the PCIe config space. We must replace the DABT handler
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* Read the PCIe config space. We must replace the DABT handler
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@ -421,6 +416,7 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 val)
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int where, u32 val)
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{
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{
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struct imx_pcie_priv *priv = hose->priv_data;
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void __iomem *va_address = NULL;
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void __iomem *va_address = NULL;
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int ret;
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int ret;
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@ -428,7 +424,7 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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if (ret)
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if (ret)
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return ret;
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return ret;
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va_address = get_bus_address(d, where);
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va_address = get_bus_address(priv, d, where);
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/*
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/*
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* Write the PCIe config space. We must replace the DABT handler
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* Write the PCIe config space. We must replace the DABT handler
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@ -445,7 +441,8 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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/*
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/*
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* Initial bus setup
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* Initial bus setup
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*/
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*/
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static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
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static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
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bool prepare_for_boot)
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{
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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@ -617,17 +614,17 @@ static int imx6_pcie_deassert_core_reset(void)
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return 0;
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return 0;
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}
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}
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static int imx_pcie_link_up(void)
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static int imx_pcie_link_up(struct imx_pcie_priv *priv)
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{
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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uint32_t tmp;
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uint32_t tmp;
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int count = 0;
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int count = 0;
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imx6_pcie_assert_core_reset(false);
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imx6_pcie_assert_core_reset(priv, false);
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imx6_pcie_init_phy();
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imx6_pcie_init_phy();
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imx6_pcie_deassert_core_reset();
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imx6_pcie_deassert_core_reset();
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imx_pcie_regions_setup();
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imx_pcie_regions_setup(priv);
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/*
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/*
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* By default, the subordinate is set equally to the secondary
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* By default, the subordinate is set equally to the secondary
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@ -654,7 +651,7 @@ static int imx_pcie_link_up(void)
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/* LTSSM enable, starting link. */
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/* LTSSM enable, starting link. */
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setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
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setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
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while (!imx6_pcie_link_up()) {
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while (!imx6_pcie_link_up(priv)) {
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udelay(10);
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udelay(10);
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count++;
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count++;
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if (count >= 4000) {
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if (count >= 4000) {
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@ -671,6 +668,13 @@ static int imx_pcie_link_up(void)
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return 0;
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return 0;
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}
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}
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static struct imx_pcie_priv imx_pcie_priv = {
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.dbi_base = (void __iomem *)MX6_DBI_ADDR,
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.cfg_base = (void __iomem *)MX6_ROOT_ADDR,
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};
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static struct imx_pcie_priv *priv = &imx_pcie_priv;
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void imx_pcie_init(void)
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void imx_pcie_init(void)
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{
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{
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/* Static instance of the controller. */
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/* Static instance of the controller. */
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@ -680,6 +684,8 @@ void imx_pcie_init(void)
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memset(&pcc, 0, sizeof(pcc));
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memset(&pcc, 0, sizeof(pcc));
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hose->priv_data = priv;
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/* PCI I/O space */
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/* PCI I/O space */
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pci_set_region(&hose->regions[0],
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pci_set_region(&hose->regions[0],
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MX6_IO_ADDR, MX6_IO_ADDR,
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MX6_IO_ADDR, MX6_IO_ADDR,
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@ -706,7 +712,7 @@ void imx_pcie_init(void)
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imx_pcie_write_config);
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imx_pcie_write_config);
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/* Start the controller. */
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/* Start the controller. */
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ret = imx_pcie_link_up();
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ret = imx_pcie_link_up(priv);
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if (!ret) {
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if (!ret) {
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pci_register_hose(hose);
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pci_register_hose(hose);
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@ -716,7 +722,7 @@ void imx_pcie_init(void)
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void imx_pcie_remove(void)
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void imx_pcie_remove(void)
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{
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{
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imx6_pcie_assert_core_reset(true);
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imx6_pcie_assert_core_reset(priv, true);
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}
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}
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/* Probe function. */
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/* Probe function. */
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