Merge tag 'u-boot-imx-next-20260402' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/29745 - Migrate imx95-toradex-smarc to use upstream devicetree. - Force fsl crypto driver to select ARCH_MISC_INIT to avoid crashes when using CAAM. - Support upstream Linux reset-gpios property for the i.MX PCI driver. - Avoid duplication of DDR tables on i.MX8MP DHCOM SoM. - Several cleanups on tqma6 platform. - Convert i.MX8MP boards to DM_PMIC. - Add phyCORE-i.MX91 support. - Drop unnecessary BOARD_EARLY_INIT_F usage.
2026-05-05 04:36:13 +02:00 · 2026-04-02 11:13:38 -06:00 · 2026-04-02 11:13:38 -06:00 · d1cd673391
commit d1cd673391
parent 91c27b21b1 4d612ec435
97 changed files with 3716 additions and 4320 deletions
--- a/12
+++ b/12
@ -1859,10 +1859,14 @@ F:	drivers/tpm/
 F:	include/tpm*
 F:	lib/tpm*

-TQ GROUP
-#M:	Martin Krause <martin.krause@tq-systems.de>
-S:	Orphaned (Since 2016-02)
-T:	git git://git.denx.de/u-boot-tq-group.git
+TQ-SYSTEMS
+L:	u-boot@ew.tq-group.com
+S:	Maintained
+W:	https://www.tq-group.com/en/products/tq-embedded/
+F:	board/tq/*
+F:	doc/board/tq/*
+F:	include/configs/tq*.h
+F:	include/env/tq/*

 TEE
 M:	Jens Wiklander <jens.wiklander@linaro.org>
--- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@ -22,6 +22,18 @@
 	bootph-pre-ram;
 };

+&pca9450 {
+	bootph-all;
+};
+
+&pinctrl_i2c1 {
+	bootph-all;
+};
+
+&pinctrl_pmic {
+	bootph-all;
+};
+
 &pinctrl_uart2 {
 	bootph-pre-ram;
 };
@ -63,7 +75,7 @@
 };

 &i2c1 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &i2c2 {
@ -118,3 +130,7 @@
 	phy-reset-duration = <15>;
 	phy-reset-post-delay = <100>;
 };
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+	bootph-all;
+};
--- a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
@ -33,6 +33,18 @@
 	};
 };

+&pinctrl_i2c1 {
+	bootph-all;
+};
+
+&pinctrl_pmic {
+	bootph-all;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+	bootph-all;
+};
+
 &reg_usdhc2_vmmc {
 	bootph-pre-ram;
 };
@ -78,11 +90,11 @@
 };

 &i2c1 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &pmic {
-	bootph-pre-ram;
+	bootph-all;
 };

 /* USB1 Type-C */
@ -120,6 +132,12 @@

 &usdhc2 {
 	bootph-pre-ram;
+	/*
+	 * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
+	 * when using SDHC controller VSELECT to control SD2_VSEL. So drop
+	 * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
+	 */
+	 /delete-property/ vqmmc-supply;
 };

 &usdhc3 {
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@ -34,6 +34,18 @@
 	};
 };

+&pinctrl_i2c1 {
+	bootph-all;
+};
+
+&pinctrl_pmic {
+	bootph-all;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+	bootph-all;
+};
+
 &reg_usdhc2_vmmc {
 	bootph-pre-ram;
 };
@ -83,11 +95,11 @@
 };

 &i2c1 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &pmic {
-	bootph-pre-ram;
+	bootph-all;
 };

 &usb_dwc3_0 {
@ -96,6 +108,12 @@

 &usdhc2 {
 	bootph-pre-ram;
+	/*
+	 * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
+	 * when using SDHC controller VSELECT to control SD2_VSEL. So drop
+	 * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
+	 */
+	/delete-property/ vqmmc-supply;
 };

 &usdhc3 {
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@ -70,7 +70,7 @@
 };

 &i2c1 {
-	bootph-pre-ram;
+	bootph-all;

 	eeprom_module: eeprom@50 {
 		compatible = "i2c-eeprom";
@ -104,7 +104,7 @@
 };

 &pca9450 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &pinctrl_ctrl_sleep_moci {
@ -112,7 +112,11 @@
 };

 &pinctrl_i2c1 {
-	bootph-pre-ram;
+	bootph-all;
+};
+
+&pinctrl_pmic {
+	bootph-all;
 };

 &pinctrl_usdhc2_pwr_en {
@ -159,6 +163,12 @@
 	sd-uhs-ddr50;
 	sd-uhs-sdr104;
 	bootph-pre-ram;
+	/*
+	 * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
+	 * when using SDHC controller VSELECT to control SD2_VSEL. So drop
+	 * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
+	 */
+	 /delete-property/ vqmmc-supply;
 };

 &usdhc3 {
@ -173,3 +183,7 @@
 &wdog1 {
 	bootph-pre-ram;
 };
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+	bootph-all;
+};
--- a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
+++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ *
+ */
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	aliases {
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
+	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc0", "mmc1", "ethernet";
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&{/soc@0} {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&aips1 {
+	bootph-pre-ram;
+	bootph-all;
+};
+
+&aips2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&aips3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&iomuxc {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_cd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_default {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpuart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pmic@25 {
+		bootph-pre-ram;
+		bootph-some-ram;
+
+		regulators {
+			bootph-pre-ram;
+			bootph-some-ram;
+		};
+	};
+
+	eeprom@50 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
+
+&s4muap {
+	bootph-pre-ram;
+	bootph-some-ram;
+	status = "okay";
+};
+
+&clk {
+	bootph-all;
+	bootph-pre-ram;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&osc_24m {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&clk_ext1 {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&wdog3 {
+	bootph-all;
+	bootph-pre-ram;
+};
--- a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ *
+ */
+
+#include "imx91-u-boot.dtsi"
+#include "imx91-93-phyboard-segin-common-u-boot.dtsi"
+
+/ {
+	/*
+	 * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as
+	 * reference, but does only make use of its SoM (phyCORE) contained
+	 * periphery.
+	 */
+	model = "PHYTEC phyCORE-i.MX91";
+};
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@ -9,6 +9,7 @@
 */

 #include "imx93-u-boot.dtsi"
+#include "imx91-93-phyboard-segin-common-u-boot.dtsi"

 / {
 	/*
@ -17,224 +18,4 @@
 	 * periphery.
 	 */
 	model = "PHYTEC phyCORE-i.MX93";
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog3>;
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-
-	aliases {
-		ethernet0 = &fec;
-		ethernet1 = &eqos;
-	};
-
-	bootstd {
-		bootph-verify;
-		compatible = "u-boot,boot-std";
-
-		filename-prefixes = "/", "/boot/";
-		bootdev-order = "mmc0", "mmc1", "ethernet";
-
-		rauc {
-			compatible = "u-boot,distro-rauc";
-		};
-
-		script {
-			compatible = "u-boot,script";
-		};
-	};
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-};
-
-&{/soc@0} {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&aips1 {
-	bootph-pre-ram;
-	bootph-all;
-};
-
-&aips2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&aips3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&iomuxc {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&reg_usdhc2_vmmc {
-	u-boot,off-on-delay-us = <20000>;
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
-
-&pinctrl_uart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_cd {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_default {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpuart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-	fsl,signal-voltage-switch-extra-delay-ms = <8>;
-};
-
-&lpi2c1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-
-	pmic@25 {
-		bootph-pre-ram;
-		bootph-some-ram;
-
-		regulators {
-			bootph-pre-ram;
-			bootph-some-ram;
-		};
-	};
-
-	eeprom@50 {
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-};
-
-&s4muap {
-	bootph-pre-ram;
-	bootph-some-ram;
-	status = "okay";
-};
-
-&clk {
-	bootph-all;
-	bootph-pre-ram;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-rates;
-	/delete-property/ assigned-clock-parents;
-};
-
-&osc_32k {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&osc_24m {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&clk_ext1 {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&wdog3 {
-	bootph-all;
-	bootph-pre-ram;
 };
--- a/arch/arm/dts/imx95-toradex-smarc-dev.dts
+++ b/arch/arm/dts/imx95-toradex-smarc-dev.dts
@ -1,277 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (C) 2025 Toradex
- *
- * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95
- * https://www.toradex.com/products/carrier-board/smarc-development-board-kit
- */
-
-/dts-v1/;
-
-#include <dt-bindings/pwm/pwm.h>
-#include "imx95-toradex-smarc.dtsi"
-
-/ {
-	model = "Toradex SMARC iMX95 on Toradex SMARC Development Board";
-	compatible = "toradex,smarc-imx95-dev",
-		     "toradex,smarc-imx95",
-		     "fsl,imx95";
-
-	reg_carrier_1p8v: regulator-carrier-1p8v {
-		compatible = "regulator-fixed";
-		regulator-max-microvolt = <1800000>;
-		regulator-min-microvolt = <1800000>;
-		regulator-name = "On-carrier 1V8";
-	};
-
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,bitclock-master = <&codec_dai>;
-		simple-audio-card,format = "i2s";
-		simple-audio-card,frame-master = <&codec_dai>;
-		simple-audio-card,mclk-fs = <256>;
-		simple-audio-card,name = "tdx-smarc-wm8904";
-		simple-audio-card,routing =
-			"Headphone Jack", "HPOUTL",
-			"Headphone Jack", "HPOUTR",
-			"IN2L", "Line In Jack",
-			"IN2R", "Line In Jack",
-			"Microphone Jack", "MICBIAS",
-			"IN1L", "Microphone Jack";
-		simple-audio-card,widgets =
-			"Microphone", "Microphone Jack",
-			"Headphone", "Headphone Jack",
-			"Line", "Line In Jack";
-
-		codec_dai: simple-audio-card,codec {
-			clocks = <&scmi_clk IMX95_CLK_SAI3>;
-			sound-dai = <&wm8904_1a>;
-		};
-
-		simple-audio-card,cpu {
-			sound-dai = <&sai3>;
-		};
-	};
-};
-
-/* SMARC GBE0 */
-&enetc_port0 {
-	status = "okay";
-};
-
-/* SMARC GBE1 */
-&enetc_port1 {
-	status = "okay";
-};
-
-/* SMARC CAN0 */
-&flexcan1 {
-	status = "okay";
-};
-
-/* SMARC CAN1 */
-&flexcan2 {
-	status = "okay";
-};
-
-&gpio2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio12>, <&pinctrl_gpio13>;
-};
-
-&gpio4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio10>, <&pinctrl_gpio11>;
-};
-
-&gpio5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio2>,
-		    <&pinctrl_gpio3>,
-		    <&pinctrl_gpio4>,
-		    <&pinctrl_gpio6>,
-		    <&pinctrl_gpio8>,
-		    <&pinctrl_gpio9>;
-};
-
-/* SMARC I2C_CAM0 */
-&i2c_cam0 {
-	status = "okay";
-};
-
-/* SMARC I2C_CAM1 */
-&i2c_cam1 {
-	status = "okay";
-};
-
-/* SMARC I2C_GP */
-&lpi2c2 {
-	status = "okay";
-
-	wm8904_1a: audio-codec@1a {
-		compatible = "wlf,wm8904";
-		reg = <0x1a>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_sai3>, <&pinctrl_sai3_mclk>;
-		#sound-dai-cells = <0>;
-		clocks = <&scmi_clk IMX95_CLK_SAI3>;
-		clock-names = "mclk";
-		AVDD-supply = <&reg_carrier_1p8v>;
-		CPVDD-supply = <&reg_carrier_1p8v>;
-		DBVDD-supply = <&reg_carrier_1p8v>;
-		DCVDD-supply = <&reg_carrier_1p8v>;
-		MICVDD-supply = <&reg_carrier_1p8v>;
-	};
-
-	temperature-sensor@4f {
-		compatible = "ti,tmp1075";
-		reg = <0x4f>;
-	};
-
-	eeprom@57 {
-		compatible = "st,24c02", "atmel,24c02";
-		reg = <0x57>;
-		pagesize = <16>;
-	};
-
-};
-
-/* SMARC I2C_PM */
-&lpi2c3 {
-	clock-frequency = <100000>;
-	status = "okay";
-
-	fan_controller: fan@18 {
-		compatible = "ti,amc6821";
-		reg = <0x18>;
-		#pwm-cells = <2>;
-
-		fan {
-			cooling-levels = <255>;
-			pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
-		};
-	};
-
-	/* Current measurement into module VCC */
-	hwmon@40 {
-		compatible = "ti,ina226";
-		reg = <0x40>;
-		shunt-resistor = <5000>;
-	};
-};
-
-/* SMARC I2C_LCD */
-&lpi2c5 {
-	status = "okay";
-
-	i2c-mux@70 {
-		compatible = "nxp,pca9543";
-		reg = <0x70>;
-		i2c-mux-idle-disconnect;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* I2C on DSI Connector Pins 4/6 */
-		i2c_dsi_0: i2c@0 {
-			reg = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		/* I2C on DSI Connector Pins 52/54 */
-		i2c_dsi_1: i2c@1 {
-			reg = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
-};
-
-/* SMARC SPI0 */
-&lpspi6 {
-	status = "okay";
-};
-
-/* SMARC SER1, used as the Linux Console */
-&lpuart1 {
-	status = "okay";
-};
-
-/* SMARC SER0, RS485 */
-&lpuart2 {
-	linux,rs485-enabled-at-boot-time;
-	rs485-rts-active-low;
-	rs485-rx-during-tx;
-	status = "okay";
-};
-
-/* SMARC SER3, RS232 */
-&lpuart3 {
-	status = "okay";
-};
-
-/* SMARC MDIO, shared between all ethernet ports */
-&netc_emdio {
-	status = "okay";
-
-	ethphy3: ethernet-phy@4 {
-		reg = <4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio7>;
-		interrupt-parent = <&gpio5>;
-		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-/* SMARC PCIE_A / M2 Key B */
-&pcie0 {
-	status = "okay";
-};
-
-/* SMARC PCIE_B /  M2 Key E */
-&pcie1 {
-	status = "okay";
-};
-
-/* SMARC I2S0 */
-&sai3 {
-	status = "okay";
-};
-
-/* SMARC LCD0_BKLT_PWM */
-&tpm3 {
-	status = "okay";
-};
-
-/* SMARC LCD1_BKLT_PWM */
-&tpm4 {
-	status = "okay";
-};
-
-/* SMARC GPIO5 as PWM */
-&tpm5 {
-	status = "okay";
-};
-
-/* SMARC USB0 */
-&usb2 {
-	status = "okay";
-};
-
-/* SMARC USB1..4 */
-&usb3 {
-	status = "okay";
-};
-
-&usb3_dwc3 {
-	status = "okay";
-};
-
-&usb3_phy {
-	status = "okay";
-};
-
-/* SMARC SDIO */
-&usdhc2 {
-	status = "okay";
-};
--- a/arch/arm/dts/imx95-toradex-smarc.dtsi
+++ b/arch/arm/dts/imx95-toradex-smarc.dtsi
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@ -129,6 +129,14 @@ config TARGET_KONTRON_MX93
 	  Kontron Electronics BL i.MX93 using SoM module conformant to OSM
 	  standard 1.1 size S.

+config TARGET_PHYCORE_IMX91
+	bool "phycore_imx91"
+	select IMX91
+	select IMX9_LPDDR4X
+	imply OF_UPSTREAM
+	select OF_BOARD_FIXUP
+	select OF_BOARD_SETUP
+
 config TARGET_PHYCORE_IMX93
 	bool "phycore_imx93"
 	select IMX93
@ -161,6 +169,7 @@ config TARGET_IMX943_EVK
 config TARGET_TORADEX_SMARC_IMX95
 	bool "Support Toradex SMARC iMX95"
 	select IMX95
+	imply OF_UPSTREAM

 config TARGET_IMX952_EVK
 	bool "imx952_evk"
@ -181,7 +190,7 @@ source "board/nxp/imx93_evk/Kconfig"
 source "board/nxp/imx93_frdm/Kconfig"
 source "board/nxp/imx93_qsb/Kconfig"
 source "board/kontron/osm-s-mx93/Kconfig"
-source "board/phytec/phycore_imx93/Kconfig"
+source "board/phytec/phycore_imx91_93/Kconfig"
 source "board/variscite/imx93_var_som/Kconfig"
 source "board/nxp/imx94_evk/Kconfig"
 source "board/nxp/imx95_evk/Kconfig"
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@ -664,7 +664,8 @@ int low_drive_freq_update(void *blob)
 	return 0;
 }

-#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) && \
+	!defined(CONFIG_TARGET_PHYCORE_IMX91)
 #ifndef CONFIG_XPL_BUILD
 int board_fix_fdt(void *fdt)
 {
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@ -419,7 +419,6 @@ config TARGET_MX6SXSABRESD
 config TARGET_MX6SXSABREAUTO
 	bool "mx6sxsabreauto"
 	depends on MX6SX
-	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 	select DM
 	select DM_THERMAL
--- a/board/dhelectronics/dh_imx8mp/Makefile
+++ b/board/dhelectronics/dh_imx8mp/Makefile
@ -5,7 +5,7 @@
 #

 ifdef CONFIG_XPL_BUILD
-obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o
+obj-y += spl.o lpddr4_timing_2G_32.o
 else
 obj-y += imx8mp_dhcom_pdk2.o
 endif
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@ -28,12 +28,11 @@ int mach_cpu_init(void)

 int board_phys_sdram_size(phys_size_t *size)
 {
-	const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
 	const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
 	u8 memcfg = dh_get_memcfg();

 	/* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */
-	*size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0));
+	*size = (u64)dh_imx8mp_dhcom_dram_size[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0));

 	return 0;
 }
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@ -6,12 +6,16 @@
 #ifndef __LPDDR4_TIMING_H__
 #define __LPDDR4_TIMING_H__

-extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
-extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
+static const u16 dh_imx8mp_dhcom_dram_size[] = {
+	4096, 1024, 1536, 2048, 3072, 4096, 6144, 8192
+};

-typedef void (*scrub_func_t)(void);
-extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
-extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);
+extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
+static __maybe_unused struct dram_timing_info *dh_imx8mp_dhcom_dram_timing =
+	&dh_imx8mp_dhcom_dram_timing_16g_x32;
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void);
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void);
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void);

 u8 dh_get_memcfg(void);

--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
@ -1854,16 +1854,197 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = {
 	.fsp_table = { 3600, 400, 100, },
 };

-#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
-void dh_imx8mp_dhcom_dram_scrub_16g_x32(void)
+/*
+ * Convert 2 GiB DRAM settings to 2 GiB DRAM settings.
+ * This does nothing and is only a placeholder to indicate
+ * that the 2 GiB DRAM settings are valid themselves.
+ */
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void)
 {
-	ddrc_inline_ecc_scrub(0x0,0x3ffffff);
-	ddrc_inline_ecc_scrub(0x4000000,0x7ffffff);
-	ddrc_inline_ecc_scrub(0x8000000,0xbffffff);
-	ddrc_inline_ecc_scrub(0xc000000,0xfffffff);
-	ddrc_inline_ecc_scrub(0x10000000,0x13ffffff);
-	ddrc_inline_ecc_scrub(0x14000000,0x17ffffff);
-	ddrc_inline_ecc_scrub(0x18000000,0x1bffffff);
-	ddrc_inline_ecc_scrub_end(0x0,0x1fffffff);
 }
+
+/* Convert 2 GiB DRAM settings to 4 GiB 2-rank DRAM settings. */
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) {
+		if (ddr_ddrc_cfg[i].reg == 0x3d400000)
+			ddr_ddrc_cfg[i].val = 0xa3080020;
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+		if (ddr_ddrc_cfg[i].reg == 0x3d400200)
+			ddr_ddrc_cfg[i].val = 0x14;
+		if (ddr_ddrc_cfg[i].reg == 0x3d40020c)
+			ddr_ddrc_cfg[i].val = 0x14141400;
+#else
+		if (ddr_ddrc_cfg[i].reg == 0x3d400200)
+			ddr_ddrc_cfg[i].val = 0x17;
 #endif
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp0_cfg); i++) {
+		if (ddr_fsp0_cfg[i].reg == 0x54012)
+			ddr_fsp0_cfg[i].val = 0x310;
+		if (ddr_fsp0_cfg[i].reg == 0x5402c)
+			ddr_fsp0_cfg[i].val = 0x3;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) {
+		if (ddr_fsp1_cfg[i].reg == 0x54012)
+			ddr_fsp1_cfg[i].val = 0x310;
+		if (ddr_fsp1_cfg[i].reg == 0x5402c)
+			ddr_fsp1_cfg[i].val = 0x3;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) {
+		if (ddr_fsp2_cfg[i].reg == 0x54012)
+			ddr_fsp2_cfg[i].val = 0x310;
+		if (ddr_fsp2_cfg[i].reg == 0x5402c)
+			ddr_fsp2_cfg[i].val = 0x3;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp0_2d_cfg); i++) {
+		if (ddr_fsp0_2d_cfg[i].reg == 0x54012)
+			ddr_fsp0_2d_cfg[i].val = 0x310;
+		if (ddr_fsp0_2d_cfg[i].reg == 0x5402c)
+			ddr_fsp0_2d_cfg[i].val = 0x3;
+	}
+};
+
+/* Convert 2 GiB DRAM settings to 4 GiB 1-rank DRAM settings. */
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) {
+		if (ddr_ddrc_cfg[i].reg == 0x3d400064)
+			ddr_ddrc_cfg[i].val = 0x6d0156;
+		if (ddr_ddrc_cfg[i].reg == 0x3d400138)
+			ddr_ddrc_cfg[i].val = 0x15d;
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+		if (ddr_ddrc_cfg[i].reg == 0x3d400200)
+			ddr_ddrc_cfg[i].val = 0x1f;
+		if (ddr_ddrc_cfg[i].reg == 0x3d40020c)
+			ddr_ddrc_cfg[i].val = 0x14141400;
+#else
+		if (ddr_ddrc_cfg[i].reg == 0x3d400200)
+			ddr_ddrc_cfg[i].val = 0x17;
+#endif
+		if (ddr_ddrc_cfg[i].reg == 0x3d40021c)
+			ddr_ddrc_cfg[i].val = 0xf04;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402024)
+			ddr_ddrc_cfg[i].val = 0x61a800;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402064)
+			ddr_ddrc_cfg[i].val = 0x18004c;
+		if (ddr_ddrc_cfg[i].reg == 0x3d4020dc)
+			ddr_ddrc_cfg[i].val = 0x940009;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402100)
+			ddr_ddrc_cfg[i].val = 0xc080609;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402104)
+			ddr_ddrc_cfg[i].val = 0x3040d;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402108)
+			ddr_ddrc_cfg[i].val = 0x3060a0c;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402110)
+			ddr_ddrc_cfg[i].val = 0x4040204;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402114)
+			ddr_ddrc_cfg[i].val = 0x2030303;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402138)
+			ddr_ddrc_cfg[i].val = 0x4e;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402144)
+			ddr_ddrc_cfg[i].val = 0x280014;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402180)
+			ddr_ddrc_cfg[i].val = 0xc80006;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402190)
+			ddr_ddrc_cfg[i].val = 0x3878202;
+		if (ddr_ddrc_cfg[i].reg == 0x3d4021b4)
+			ddr_ddrc_cfg[i].val = 0x702;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403024)
+			ddr_ddrc_cfg[i].val = 0x493fe1;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403064)
+			ddr_ddrc_cfg[i].val = 0x12003a;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403100)
+			ddr_ddrc_cfg[i].val = 0xa070507;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403104)
+			ddr_ddrc_cfg[i].val = 0x3040a;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403108)
+			ddr_ddrc_cfg[i].val = 0x203070b;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403110)
+			ddr_ddrc_cfg[i].val = 0x3040203;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403114)
+			ddr_ddrc_cfg[i].val = 0x2030303;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403138)
+			ddr_ddrc_cfg[i].val = 0x3b;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403144)
+			ddr_ddrc_cfg[i].val = 0x1f0010;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403180)
+			ddr_ddrc_cfg[i].val = 0x970005;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_ddrphy_cfg); i++) {
+		if (ddr_ddrphy_cfg[i].reg == 0x12002e)
+			ddr_ddrphy_cfg[i].val = 0x1;
+		if (ddr_ddrphy_cfg[i].reg == 0x22002e)
+			ddr_ddrphy_cfg[i].val = 0x1;
+		if (ddr_ddrphy_cfg[i].reg == 0x120008)
+			ddr_ddrphy_cfg[i].val = 0xc8;
+		if (ddr_ddrphy_cfg[i].reg == 0x220008)
+			ddr_ddrphy_cfg[i].val = 0x96;
+		if (ddr_ddrphy_cfg[i].reg == 0x200f0)
+			ddr_ddrphy_cfg[i].val = 0x500;
+		if (ddr_ddrphy_cfg[i].reg == 0x200f4)
+			ddr_ddrphy_cfg[i].val = 0x5555;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) {
+		if (ddr_fsp1_cfg[i].reg == 0x54002)
+			ddr_fsp1_cfg[i].val = 0x1;
+		if (ddr_fsp1_cfg[i].reg == 0x54003)
+			ddr_fsp1_cfg[i].val = 0x320;
+		if (ddr_fsp1_cfg[i].reg == 0x54019)
+			ddr_fsp1_cfg[i].val = 0x994;
+		if (ddr_fsp1_cfg[i].reg == 0x5401f)
+			ddr_fsp1_cfg[i].val = 0x994;
+		if (ddr_fsp1_cfg[i].reg == 0x54032)
+			ddr_fsp1_cfg[i].val = 0x9400;
+		if (ddr_fsp1_cfg[i].reg == 0x54033)
+			ddr_fsp1_cfg[i].val = 0xf309;
+		if (ddr_fsp1_cfg[i].reg == 0x54038)
+			ddr_fsp1_cfg[i].val = 0x9400;
+		if (ddr_fsp1_cfg[i].reg == 0x54039)
+			ddr_fsp1_cfg[i].val = 0xf309;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) {
+		if (ddr_fsp2_cfg[i].reg == 0x54002)
+			ddr_fsp2_cfg[i].val = 0x2;
+		if (ddr_fsp2_cfg[i].reg == 0x54003)
+			ddr_fsp2_cfg[i].val = 0x258;
+		if (ddr_fsp2_cfg[i].reg == 0x54019)
+			ddr_fsp2_cfg[i].val = 0x994;
+		if (ddr_fsp2_cfg[i].reg == 0x5401f)
+			ddr_fsp2_cfg[i].val = 0x994;
+		if (ddr_fsp2_cfg[i].reg == 0x54032)
+			ddr_fsp2_cfg[i].val = 0x9400;
+		if (ddr_fsp2_cfg[i].reg == 0x54033)
+			ddr_fsp2_cfg[i].val = 0xf309;
+		if (ddr_fsp2_cfg[i].reg == 0x54038)
+			ddr_fsp2_cfg[i].val = 0x9400;
+		if (ddr_fsp2_cfg[i].reg == 0x54039)
+			ddr_fsp2_cfg[i].val = 0xf309;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_phy_pie); i++) {
+		if (ddr_phy_pie[i].reg == 0x12000b)
+			ddr_phy_pie[i].val = 0xe1;
+		if (ddr_phy_pie[i].reg == 0x12000c)
+			ddr_phy_pie[i].val = 0x32;
+		if (ddr_phy_pie[i].reg == 0x12000d)
+			ddr_phy_pie[i].val = 0x1f4;
+		if (ddr_phy_pie[i].reg == 0x22000b)
+			ddr_phy_pie[i].val = 0xa8;
+		if (ddr_phy_pie[i].reg == 0x22000c)
+			ddr_phy_pie[i].val = 0x25;
+		if (ddr_phy_pie[i].reg == 0x22000d)
+			ddr_phy_pie[i].val = 0x177;
+	}
+};
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@ -104,34 +104,36 @@ static int dh_imx8mp_board_power_init(void)
 	return 0;
 }

-static struct dram_timing_info *dram_timing_info[8] = {
-	NULL,					/* 512 MiB */
-	NULL,					/* 1024 MiB */
-	NULL,					/* 1536 MiB */
-	&dh_imx8mp_dhcom_dram_timing_16g_x32,	/* 2048 MiB */
-	NULL,					/* 3072 MiB */
-	&dh_imx8mp_dhcom_dram_timing_32g_x32,	/* 4096 MiB */
-	NULL,					/* 6144 MiB */
-	NULL,					/* 8192 MiB */
+typedef void (*patch_func_t)(void);
+
+static const patch_func_t dram_patch_fn[8] = {
+	dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r,	/* 4096 MiB 1-rank */
+	NULL,							/* 1024 MiB */
+	NULL,							/* 1536 MiB */
+	dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32,		/* 2048 MiB */
+	NULL,							/* 3072 MiB */
+	dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r,	/* 4096 MiB 2-rank */
+	NULL,							/* 6144 MiB */
+	NULL,							/* 8192 MiB */
 };

 static void spl_dram_init(void)
 {
-	const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
 	u8 memcfg = dh_get_memcfg();
 	int i;

-	printf("DDR:   %d MiB [0x%x]\n", size[memcfg], memcfg);
+	printf("DDR:   %d MiB [0x%x]\n", dh_imx8mp_dhcom_dram_size[memcfg], memcfg);

-	if (!dram_timing_info[memcfg]) {
+	if (!dram_patch_fn[memcfg]) {
 		printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
 		       memcfg);
-		for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++)
-			if (dram_timing_info[i])	/* Configuration found */
+		for (i = 0; i < ARRAY_SIZE(dram_patch_fn); i++)
+			if (dram_patch_fn[i])	/* Configuration found */
 				break;
 	}

-	ddr_init(dram_timing_info[memcfg]);
+	dram_patch_fn[memcfg]();
+	ddr_init(dh_imx8mp_dhcom_dram_timing);

 	printf("DDR:   Inline ECC %sabled\n",
 	       (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
@ -139,13 +141,39 @@ static void spl_dram_init(void)
 }

 #if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+static void dh_imx8mp_dhcom_dram_scrub_16g_x32(void)
+{
+	ddrc_inline_ecc_scrub(0x0,0x3ffffff);
+	ddrc_inline_ecc_scrub(0x4000000,0x7ffffff);
+	ddrc_inline_ecc_scrub(0x8000000,0xbffffff);
+	ddrc_inline_ecc_scrub(0xc000000,0xfffffff);
+	ddrc_inline_ecc_scrub(0x10000000,0x13ffffff);
+	ddrc_inline_ecc_scrub(0x14000000,0x17ffffff);
+	ddrc_inline_ecc_scrub(0x18000000,0x1bffffff);
+	ddrc_inline_ecc_scrub_end(0x0,0x1fffffff);
+}
+
+static void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)
+{
+	ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+	ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+	ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+	ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+	ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+	ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+	ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+	ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+
+typedef void (*scrub_func_t)(void);
+
 static const scrub_func_t dram_scrub_fn[8] = {
-	NULL,					/* 512 MiB */
+	dh_imx8mp_dhcom_dram_scrub_32g_x32,	/* 4096 MiB 1-rank */
 	NULL,					/* 1024 MiB */
 	NULL,					/* 1536 MiB */
 	dh_imx8mp_dhcom_dram_scrub_16g_x32,	/* 2048 MiB */
 	NULL,					/* 3072 MiB */
-	dh_imx8mp_dhcom_dram_scrub_32g_x32,	/* 4096 MiB */
+	dh_imx8mp_dhcom_dram_scrub_32g_x32,	/* 4096 MiB 2-rank */
 	NULL,					/* 6144 MiB */
 	NULL,					/* 8192 MiB */
 };
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@ -52,11 +52,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif

-int board_early_init_f(void)
-{
-       return 0;
-}
-
 void board_init_f(ulong dummy)
 {
 	int ret;
@ -65,8 +60,6 @@ void board_init_f(ulong dummy)

 	init_uart_clk(1);

-	board_early_init_f();
-
 	timer_init();

 	/* Clear the BSS. */
--- a/board/engicam/imx8mp/spl.c
+++ b/board/engicam/imx8mp/spl.c
@ -16,9 +16,6 @@
 #include <asm/arch/imx8mp_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch/ddr.h>
 #include <power/pmic.h>
 #include <power/pca9450.h>
@ -33,36 +30,22 @@ void spl_dram_init(void)
 	ddr_init(&dram_timing);
 }

-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-		.gp = IMX_GPIO_NR(5, 14),
-	},
-	.sda = {
-		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-		.gp = IMX_GPIO_NR(5, 15),
-	},
-};
-
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
-#define I2C_PMIC	0
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
 	int ret;

-	ret = power_pca9450_init(I2C_PMIC, 0x25);
-	if (ret)
-		printf("power init failed");
-	p = pmic_get("PCA9450");
-	pmic_probe(p);
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic@25\n");
+		return 0;
+	}
+	if (ret < 0)
+		return ret;

 	/* BUCKxOUT_DVS0/1 control BUCK123 output */
-	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

 #ifdef CONFIG_IMX8M_LPDDR4
 	/*
@ -73,22 +56,22 @@ int power_init_board(void)
 	 */
 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
 	/* set DVS0 to 0.85v for special case*/
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
 #else
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
 #endif
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
-	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

 	/* Kernel uses OD/OD freq for SOC */
 	/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
-	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
 #elif defined(CONFIG_IMX8M_DDR4)
 	/* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
-	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

 	/* Set NVCC_DRAM to 1.2v for DDR4 */
-	pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
+	pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18);
 #endif

 	return 0;
@ -136,8 +119,6 @@ void board_init_f(ulong dummy)

 	enable_tzc380();

-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
 	power_init_board();

 	/* DDR initialization */
--- a/board/kontron/osm-s-mx93/osm-s-mx93.c
+++ b/board/kontron/osm-s-mx93/osm-s-mx93.c
@ -22,11 +22,6 @@

 #include "../common/hw-uid.h"

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_KONTRON_HW_UID)
 struct uid_otp_loc uid_otp_locations[] = {
 	{
--- a/board/kontron/osm-s-mx93/spl.c
+++ b/board/kontron/osm-s-mx93/spl.c
@ -132,8 +132,6 @@ void board_init_f(ulong dummy)

 	arch_cpu_init();

-	board_early_init_f();
-
 	spl_early_init();

 	preloader_console_init();
--- a/board/nxp/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.c
@ -101,11 +101,6 @@ int board_init(void)
 	return 0;
 }

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_late_init(void)
 {
 	ulong addr;
--- a/board/nxp/imx8ulp_evk/spl.c
+++ b/board/nxp/imx8ulp_evk/spl.c
@ -74,8 +74,6 @@ void spl_board_init(void)
 	if (ret)
 		return;

-	board_early_init_f();
-
 	preloader_console_init();

 	puts("Normal Boot\n");
--- a/board/nxp/imx93_frdm/imx93_frdm.c
+++ b/board/nxp/imx93_frdm/imx93_frdm.c
@ -90,11 +90,6 @@ static int clear_pd_alert(void)
 	return 0;
 }

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	return 0;
--- a/board/nxp/imx93_frdm/spl.c
+++ b/board/nxp/imx93_frdm/spl.c
@ -156,8 +156,6 @@ void board_init_f(ulong dummy)

 	arch_cpu_init();

-	board_early_init_f();
-
 	spl_early_init();

 	preloader_console_init();
--- a/board/nxp/mx6sllevk/mx6sllevk.c
+++ b/board/nxp/mx6sllevk/mx6sllevk.c
@ -76,11 +76,6 @@ int power_init_board(void)
 }
 #endif

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	/* Address of boot parameters */
--- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c
@ -199,11 +199,6 @@ int board_ehci_hcd_init(int port)
 }
 #endif

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 #ifdef CONFIG_FSL_QSPI
 int board_qspi_init(void)
 {
--- a/board/nxp/mx6ullevk/mx6ullevk.c
+++ b/board/nxp/mx6ullevk/mx6ullevk.c
@ -41,11 +41,6 @@ int mmc_map_to_kernel_blk(int devno)
 	return devno;
 }

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(int fec_id)
 {
--- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c
+++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c
@ -16,11 +16,6 @@ int dram_init(void)
 	return 0;
 }

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 static int setup_fec_clock(void)
 {
 	if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) {
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@ -19,13 +19,13 @@ config PHYTEC_IMX8M_SOM_DETECTION
 	  Support of I2C EEPROM based SoM detection. Supported
 	  for PHYTEC i.MX8MM/i.MX8MP boards

-config PHYTEC_IMX93_SOM_DETECTION
-	bool "Support SoM detection for i.MX93 PHYTEC platforms"
+config PHYTEC_IMX91_93_SOM_DETECTION
+	bool "Support SoM detection for i.MX91/93 PHYTEC platforms"
 	depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION
 	default y
 	help
 	  Support of I2C EEPROM based SoM detection. Supported
-	  for PHYTEC i.MX93 based boards
+	  for PHYTEC i.MX91/93 based boards

 config PHYTEC_AM62_SOM_DETECTION
 	bool "Support SoM detection for AM62x PHYTEC platforms"
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@ -10,4 +10,4 @@ endif
 obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
 obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
 obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
-obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o
+obj-$(CONFIG_ARCH_IMX9) += imx91_93_som_detection.o
--- a/board/phytec/common/imx91_93_som_detection.c
+++ b/board/phytec/common/imx91_93_som_detection.c
@ -10,18 +10,19 @@
 #include <i2c.h>
 #include <u-boot/crc.h>

-#include "imx93_som_detection.h"
+#include "imx91_93_som_detection.h"

 extern struct phytec_eeprom_data eeprom_data;

-#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION)
+#if IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION)

 /* Check if the SoM is actually one of the following products:
+ * - i.MX91
 * - i.MX93
 *
 * Returns 0 in case it's a known SoM. Otherwise, returns 1.
 */
-u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data)
 {
 	u8 som;

@ -35,7 +36,7 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
 	som = data->payload.data.data_api2.som_no;
 	debug("%s: som id: %u\n", __func__, som);

-	if (som == PHYTEC_IMX93_SOM && is_imx93())
+	if (som == PHYTEC_IMX91_93_SOM && (is_imx91() || is_imx93()))
 		return 0;

 	pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
@ -43,15 +44,15 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
 }

 /*
- * Filter PHYTEC i.MX93 SoM options by option index
+ * Filter PHYTEC i.MX91/93 SoM options by option index
 *
 * Returns:
 *  - option value
 *  - PHYTEC_EEPROM_INVAL when the data is invalid
 *
 */
-u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
-				       enum phytec_imx93_option_index idx)
+u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data,
+					  enum phytec_imx91_93_option_index idx)
 {
 	char *opt;
 	u8 opt_id;
@ -73,39 +74,41 @@ u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
 }

 /*
- * Filter PHYTEC i.MX93 SoM voltage
+ * Filter PHYTEC i.MX91/93 SoM voltage
 *
 * Returns:
- *  - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3
+ *  - PHYTEC_IMX91_93_VOLTAGE_1V8 or PHYTEC_IMX91_93_VOLTAGE_3V3
 *  - PHYTEC_EEPROM_INVAL when the data is invalid
 *
 */
-enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data)
+enum phytec_imx91_93_voltage __maybe_unused
+phytec_imx91_93_get_voltage(struct phytec_eeprom_data *data)
 {
-	u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
+	u8 option = phytec_imx91_93_get_opt(data, PHYTEC_IMX91_93_OPT_FEAT);

 	if (option == PHYTEC_EEPROM_INVAL)
-		return PHYTEC_IMX93_VOLTAGE_INVALID;
-	return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3;
+		return PHYTEC_IMX91_93_VOLTAGE_INVALID;
+	return (option & 0x01) ? PHYTEC_IMX91_93_VOLTAGE_1V8 :
+				 PHYTEC_IMX91_93_VOLTAGE_3V3;
 }

 #else

-inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data)
 {
 	return 1;
 }

-inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
-					      enum phytec_imx93_option_index idx)
+inline u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data,
+						 enum phytec_imx91_93_option_index idx)
 {
 	return PHYTEC_EEPROM_INVAL;
 }

-inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+inline enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage
 	(struct phytec_eeprom_data *data)
 {
 	return PHYTEC_EEPROM_INVAL;
 }

-#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) */
--- a/board/phytec/common/imx91_93_som_detection.h
+++ b/board/phytec/common/imx91_93_som_detection.h
@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#ifndef _PHYTEC_IMX91_93_SOM_DETECTION_H
+#define _PHYTEC_IMX91_93_SOM_DETECTION_H
+
+#include "phytec_som_detection.h"
+
+#define PHYTEC_IMX91_93_SOM	77
+
+enum phytec_imx91_93_option_index {
+	PHYTEC_IMX91_93_OPT_DDR = 0,
+	PHYTEC_IMX91_93_OPT_EMMC = 1,
+	PHYTEC_IMX91_93_OPT_CPU = 2,
+	PHYTEC_IMX91_93_OPT_FREQ = 3,
+	PHYTEC_IMX91_93_OPT_NPU = 4,
+	PHYTEC_IMX91_93_OPT_DISP = 5,
+	PHYTEC_IMX91_93_OPT_ETH = 6,
+	PHYTEC_IMX91_93_OPT_FEAT = 7,
+	PHYTEC_IMX91_93_OPT_TEMP = 8,
+	PHYTEC_IMX91_93_OPT_BOOT = 9,
+	PHYTEC_IMX91_93_OPT_LED = 10,
+	PHYTEC_IMX91_93_OPT_EEPROM = 11,
+};
+
+enum phytec_imx91_93_voltage {
+	PHYTEC_IMX91_93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX91_93_VOLTAGE_3V3 = 0,
+	PHYTEC_IMX91_93_VOLTAGE_1V8 = 1,
+};
+
+enum phytec_imx91_93_ddr_eeprom_code {
+	PHYTEC_IMX91_93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX91_93_LPDDR4X_512MB = 0,
+	PHYTEC_IMX91_93_LPDDR4X_1GB = 1,
+	PHYTEC_IMX91_93_LPDDR4X_2GB = 2,
+	PHYTEC_IMX91_93_LPDDR4_512MB = 3,
+	PHYTEC_IMX91_93_LPDDR4_1GB = 4,
+	PHYTEC_IMX91_93_LPDDR4_2GB = 5,
+};
+
+u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data,
+					  enum phytec_imx91_93_option_index idx);
+enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage
+	(struct phytec_eeprom_data *data);
+
+#endif /* _PHYTEC_IMX91_93_SOM_DETECTION_H */
--- a/board/phytec/common/imx93_som_detection.h
+++ b/board/phytec/common/imx93_som_detection.h
@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2024 PHYTEC Messtechnik GmbH
- * Author: Primoz Fiser <primoz.fiser@norik.com>
- */
-
-#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
-#define _PHYTEC_IMX93_SOM_DETECTION_H
-
-#include "phytec_som_detection.h"
-
-#define PHYTEC_IMX93_SOM	77
-
-enum phytec_imx93_option_index {
-	PHYTEC_IMX93_OPT_DDR = 0,
-	PHYTEC_IMX93_OPT_EMMC = 1,
-	PHYTEC_IMX93_OPT_CPU = 2,
-	PHYTEC_IMX93_OPT_FREQ = 3,
-	PHYTEC_IMX93_OPT_NPU = 4,
-	PHYTEC_IMX93_OPT_DISP = 5,
-	PHYTEC_IMX93_OPT_ETH = 6,
-	PHYTEC_IMX93_OPT_FEAT = 7,
-	PHYTEC_IMX93_OPT_TEMP = 8,
-	PHYTEC_IMX93_OPT_BOOT = 9,
-	PHYTEC_IMX93_OPT_LED = 10,
-	PHYTEC_IMX93_OPT_EEPROM = 11,
-};
-
-enum phytec_imx93_voltage {
-	PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
-	PHYTEC_IMX93_VOLTAGE_3V3 = 0,
-	PHYTEC_IMX93_VOLTAGE_1V8 = 1,
-};
-
-enum phytec_imx93_ddr_eeprom_code {
-	PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
-	PHYTEC_IMX93_LPDDR4X_512MB = 0,
-	PHYTEC_IMX93_LPDDR4X_1GB = 1,
-	PHYTEC_IMX93_LPDDR4X_2GB = 2,
-	PHYTEC_IMX93_LPDDR4_512MB = 3,
-	PHYTEC_IMX93_LPDDR4_1GB = 4,
-	PHYTEC_IMX93_LPDDR4_2GB = 5,
-};
-
-u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
-u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
-				       enum phytec_imx93_option_index idx);
-enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
-	(struct phytec_eeprom_data *data);
-
-#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
--- a/board/phytec/imx8mp-libra-fpsc/spl.c
+++ b/board/phytec/imx8mp-libra-fpsc/spl.c
@ -9,9 +9,6 @@
 #include <asm/arch/imx8mp_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/iomux-v3.h>
 #include <hang.h>
 #include <init.h>
 #include <log.h>
@ -46,45 +43,32 @@ void spl_dram_init(void)
 	ddr_init(&dram_timing);
 }

-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-		.gp = IMX_GPIO_NR(5, 14),
-	},
-	.sda = {
-		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-		.gp = IMX_GPIO_NR(5, 15),
-	},
-};
-
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
 	int ret;

-	ret = power_pca9450_init(0, 0x25);
-	if (ret)
-		printf("power init failed");
-	p = pmic_get("PCA9450");
-	pmic_probe(p);
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic@25\n");
+		return 0;
+	}
+	if (ret < 0)
+		return ret;

 	/* BUCKxOUT_DVS0/1 control BUCK123 output */
-	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

 	/* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
-	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);

 	/* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
-	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

 	/* Set WDOG_B_CFG to cold reset */
-	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);

 	return 0;
 }
@ -120,8 +104,6 @@ void board_init_f(ulong dummy)

 	enable_tzc380();

-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
 	power_init_board();

 	/* DDR initialization */
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@ -117,45 +117,32 @@ out:
 	ddr_init(&dram_timing);
 }

-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-		.gp = IMX_GPIO_NR(5, 14),
-	},
-	.sda = {
-		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-		.gp = IMX_GPIO_NR(5, 15),
-	},
-};
-
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
 	int ret;

-	ret = power_pca9450_init(0, 0x25);
-	if (ret)
-		printf("power init failed");
-	p = pmic_get("PCA9450");
-	pmic_probe(p);
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic@25\n");
+		return 0;
+	}
+	if (ret < 0)
+		return ret;

 	/* BUCKxOUT_DVS0/1 control BUCK123 output */
-	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

 	/* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
-	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);

 	/* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
-	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

 	/* Set WDOG_B_CFG to cold reset */
-	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);

 	return 0;
 }
@ -193,8 +180,6 @@ void board_init_f(ulong dummy)

 	enable_tzc380();

-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
 	power_init_board();

 	/* DDR initialization */
--- a/board/phytec/phycore_imx91_93/Kconfig
+++ b/board/phytec/phycore_imx91_93/Kconfig
@ -0,0 +1,47 @@
+
+if TARGET_PHYCORE_IMX91 || TARGET_PHYCORE_IMX93
+
+config SYS_BOARD
+	default "phycore_imx91_93"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "phycore_imx91_93"
+
+config PHYCORE_IMX91_93_RAM_TYPE_FIX
+	bool "Set phyCORE-i.MX91/93 RAM type and size fix instead of detecting"
+	default false
+	help
+	  RAM type and size is being automatically detected with the help
+	  of the PHYTEC EEPROM introspection data.
+	  Set RAM type to a fix value instead.
+
+choice
+	prompt "phyCORE-i.MX91/93 RAM type"
+	depends on PHYCORE_IMX91_93_RAM_TYPE_FIX
+	default PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB
+
+config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB
+	bool "LPDDR4 1GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4 and RAM size fixed to 1GB
+	  for phyCORE-i.MX91/93.
+
+config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB
+	bool "LPDDR4X 1GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
+	  for phyCORE-i.MX91/93.
+
+config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB
+	bool "LPDDR4X 2GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
+	  for phyCORE-i.MX91/93.
+
+endchoice
+
+source "board/phytec/common/Kconfig"
+endif
--- a/board/phytec/phycore_imx91_93/MAINTAINERS
+++ b/board/phytec/phycore_imx91_93/MAINTAINERS
@ -0,0 +1,16 @@
+phyCORE-i.MX91/93
+M:      Mathieu Othacehe <m.othacehe@gmail.com>
+R:      Christoph Stoidner <c.stoidner@phytec.de>
+L:      upstream@lists.phytec.de
+W:      https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
+S:      Maintained
+F:      arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
+F:      arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
+F:      arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+F:      board/phytec/phycore_imx91_93/
+F:      board/phytec/common/imx91_93_som_detection.c
+F:      board/phytec/common/imx91_93_som_detection.h
+F:      configs/imx91-phycore_defconfig
+F:      configs/imx93-phycore_defconfig
+F:      include/configs/phycore_imx91_93.h
+F:      doc/board/phytec/imx91-93-phycore.rst
--- a/board/phytec/phycore_imx91_93/Makefile
+++ b/board/phytec/phycore_imx91_93/Makefile
@ -7,8 +7,13 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #

-obj-y += phycore-imx93.o
+obj-y += phycore-imx91-93.o

 ifdef CONFIG_XPL_BUILD
-obj-y += spl.o lpddr4_timing.o
+obj-y += spl.o
+ifdef CONFIG_IMX91
+obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx91.o
+else
+obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx93.o
+endif
 endif
--- a/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c
+++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c
--- a/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c
+++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c
--- a/board/phytec/phycore_imx91_93/phycore-imx91-93.c
+++ b/board/phytec/phycore_imx91_93/phycore-imx91-93.c
@ -11,7 +11,7 @@
 #include <env.h>
 #include <fdt_support.h>

-#include "../common/imx93_som_detection.h"
+#include "../common/imx91_93_som_detection.h"

 #define EEPROM_ADDR            0x50

@ -55,13 +55,13 @@ int board_late_init(void)

 static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
 {
-	enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data);
+	enum phytec_imx91_93_voltage voltage = phytec_imx91_93_get_voltage(data);
 	int offset;

-	if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID)
+	if (voltage == PHYTEC_IMX91_93_VOLTAGE_INVALID)
 		goto err;

-	if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) {
+	if (voltage == PHYTEC_IMX91_93_VOLTAGE_1V8) {
 		offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
 						       0x42850000);
 		if (offset)
--- a/board/phytec/phycore_imx91_93/phycore_imx91_93.env
+++ b/board/phytec/phycore_imx91_93/phycore_imx91_93.env
@ -9,6 +9,8 @@ fdtoverlay_addr_r=0x900c0000
 ip_dyn=yes
 kernel_addr_r=0x88000000
 nfsroot=/srv/nfs
+#ifdef CONFIG_IMX93
 prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted"
+#endif
 scriptaddr=0x83500000
 sd_dev=1    /* This is needed by built-in uuu flash scripts */
--- a/board/phytec/phycore_imx91_93/spl.c
+++ b/board/phytec/phycore_imx91_93/spl.c
@ -19,7 +19,7 @@
 #include <power/pca9450.h>
 #include <spl.h>

-#include "../common/imx93_som_detection.h"
+#include "../common/imx91_93_som_detection.h"

 DECLARE_GLOBAL_DATA_PTR;

@ -50,32 +50,38 @@ void spl_board_init(void)
 void spl_dram_init(void)
 {
 	int ret;
-	enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
+	enum phytec_imx91_93_ddr_eeprom_code ddr_opt = PHYTEC_IMX91_93_DDR_INVALID;

 	ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
-	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
+	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX))
 		goto out;

-	ret = phytec_imx93_detect(NULL);
+	ret = phytec_imx91_93_detect(NULL);
 	if (!ret)
 		phytec_print_som_info(NULL);

-	if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
-		if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
-			ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
-		else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
-			ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB))
+			ddr_opt = PHYTEC_IMX91_93_LPDDR4_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB))
+			ddr_opt = PHYTEC_IMX91_93_LPDDR4X_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB))
+			ddr_opt = PHYTEC_IMX91_93_LPDDR4X_2GB;
 	} else {
-		ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
+		ddr_opt = phytec_imx91_93_get_opt(NULL, PHYTEC_IMX91_93_OPT_DDR);
 	}

 	switch (ddr_opt) {
-	case PHYTEC_IMX93_LPDDR4X_1GB:
-		if (is_voltage_mode(VOLT_LOW_DRIVE))
+	case PHYTEC_IMX91_93_LPDDR4_1GB:
+		/* Timings statically set for i.MX91 LPDDR4 1GB. */
+		break;
+	case PHYTEC_IMX91_93_LPDDR4X_1GB:
+		if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE))
 			set_dram_timings_1gb_lpddr4x_900mhz();
 		break;
-	case PHYTEC_IMX93_LPDDR4X_2GB:
-		set_dram_timings_2gb_lpddr4x();
+	case PHYTEC_IMX91_93_LPDDR4X_2GB:
+		if (IS_ENABLED(CONFIG_IMX93))
+			set_dram_timings_2gb_lpddr4x();
 		break;
 	default:
 		goto out;
@ -84,7 +90,7 @@ void spl_dram_init(void)
 	return;
 out:
 	puts("Could not detect correct RAM type and size. Fall back to default.\n");
-	if (is_voltage_mode(VOLT_LOW_DRIVE))
+	if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE))
 		set_dram_timings_1gb_lpddr4x_900mhz();
 	ddr_init(&dram_timing);
 }
@ -185,10 +191,12 @@ void board_init_f(ulong dummy)
 	/* DDR initialization */
 	spl_dram_init();

-	/* Put M33 into CPUWAIT for following kick */
-	ret = m33_prepare();
-	if (!ret)
-		printf("M33 prepare ok\n");
+	if (IS_ENABLED(CONFIG_IMX93)) {
+		/* Put M33 into CPUWAIT for following kick */
+		ret = m33_prepare();
+		if (!ret)
+			printf("M33 prepare ok\n");
+	}

 	board_init_r(NULL, 0);
 }
--- a/board/phytec/phycore_imx93/Kconfig
+++ b/board/phytec/phycore_imx93/Kconfig
@ -1,41 +0,0 @@
-
-if TARGET_PHYCORE_IMX93
-
-config SYS_BOARD
-	default "phycore_imx93"
-
-config SYS_VENDOR
-	default "phytec"
-
-config SYS_CONFIG_NAME
-	default "phycore_imx93"
-
-config PHYCORE_IMX93_RAM_TYPE_FIX
-	bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting"
-	default false
-	help
-	  RAM type and size is being automatically detected with the help
-	  of the PHYTEC EEPROM introspection data.
-	  Set RAM type to a fix value instead.
-
-choice
-	prompt "phyCORE-i.MX93 RAM type"
-	depends on PHYCORE_IMX93_RAM_TYPE_FIX
-	default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
-
-config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
-	bool "LPDDR4X 1GB RAM"
-	help
-	  Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
-	  for phyCORE-i.MX93.
-
-config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB
-	bool "LPDDR4X 2GB RAM"
-	help
-	  Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
-	  for phyCORE-i.MX93.
-
-endchoice
-
-source "board/phytec/common/Kconfig"
-endif
--- a/board/phytec/phycore_imx93/MAINTAINERS
+++ b/board/phytec/phycore_imx93/MAINTAINERS
@ -1,12 +0,0 @@
-phyCORE-i.MX93
-M:      Mathieu Othacehe <m.othacehe@gmail.com>
-R:      Christoph Stoidner <c.stoidner@phytec.de>
-L:      upstream@lists.phytec.de
-W:      https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
-S:      Maintained
-F:      arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
-F:      board/phytec/phycore_imx93/
-F:      board/phytec/common/imx93_som_detection.c
-F:      board/phytec/common/imx93_som_detection.h
-F:      configs/imx93-phycore_defconfig
-F:      include/configs/phycore_imx93.h
--- a/board/purism/librem5/librem5.c
+++ b/board/purism/librem5/librem5.c
@ -31,11 +31,6 @@
 #include <usb/xhci.h>
 #include "librem5.h"

-int board_early_init_f(void)
-{
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION)
 uint board_mmc_get_env_part(struct mmc *mmc)
 {
--- a/board/purism/librem5/spl.c
+++ b/board/purism/librem5/spl.c
@ -547,8 +547,6 @@ void board_init_f(ulong dummy)
 	gpio_direction_output(WIFI_EN, 1);
 #endif

-	board_early_init_f();
-
 	timer_init();

 	preloader_console_init();
--- a/board/toradex/smarc-imx95/MAINTAINERS
+++ b/board/toradex/smarc-imx95/MAINTAINERS
@ -1,6 +1,4 @@
 Toradex SMARC iMX95
-F:	arch/arm/dts/imx95-toradex-smarc.dtsi
-F:	arch/arm/dts/imx95-toradex-smarc-dev.dts
 F:	arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi
 F:	board/toradex/smarc-imx95/
 F:	configs/toradex-smarc-imx95_defconfig
--- a/board/toradex/verdin-imx8mp/spl.c
+++ b/board/toradex/verdin-imx8mp/spl.c
@ -8,12 +8,8 @@
 #include <log.h>
 #include <spl.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/imx8mp_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch/ddr.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
@ -68,36 +64,21 @@ void spl_board_init(void)
 	puts("Normal Boot\n");
 }

-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-		.gp = IMX_GPIO_NR(5, 14),
-	},
-	.sda = {
-		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-		.gp = IMX_GPIO_NR(5, 15),
-	},
-};
-
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
-#define I2C_PMIC	0
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
 	int ret;

-	ret = power_pca9450_init(I2C_PMIC, 0x25);
-	if (ret)
-		printf("power init failed\n");
-	p = pmic_get("PCA9450");
-	pmic_probe(p);
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic@25\n");
+		return 0;
+	}
+	if (ret < 0)
+		return ret;

 	/* BUCKxOUT_DVS0/1 control BUCK123 output */
-	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

 	/*
 	 * increase VDD_SOC to typical value 0.95V before first
@ -107,23 +88,22 @@ int power_init_board(void)
 	 */
 	if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
 		/* set DVS0 to 0.85v for special case */
-		pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
 	else
-		pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1c);
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
-	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

 	/* Kernel uses OD/OD freq for SoC */
 	/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */
-	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c);
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);

 	/* set LDO4 and CONFIG2 to enable the I2C level translator */
-	pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59);
-	pmic_reg_write(p, PCA9450_CONFIG2, 0x1);
+	pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
+	pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);

 	return 0;
 }
-#endif

 #if IS_ENABLED(CONFIG_SPL_LOAD_FIT)
 int board_fit_config_name_match(const char *name)
@ -156,9 +136,6 @@ void board_init_f(ulong dummy)

 	enable_tzc380();

-	/* Adjust PMIC voltage to 1.0V for 800 MHz */
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
 	/* PMIC initialization */
 	power_init_board();

--- a/board/tq/MAINTAINERS
+++ b/board/tq/MAINTAINERS
@ -0,0 +1,8 @@
+TQMA6
+M:	Max Merchel <max.merchel@ew.tq-group.com>
+L:	u-boot@ew.tq-group.com
+S:	Maintained
+W:	https://www.tq-group.com/en/products/tq-embedded/
+F:	arch/arm/dts/*mba6*.dts*
+F:	arch/arm/dts/*tqma6*.dts*
+F:	configs/tqma6*config
--- a/board/tq/common/Kconfig
+++ b/board/tq/common/Kconfig
@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+# D-82229 Seefeld, Germany.
+# Author: Markus Niebel, Max Merchel
+#
+
+config TQ_COMMON_BB
+	bool
+	default y
+
+config TQ_COMMON_SDMMC
+	bool
--- a/board/tq/common/Makefile
+++ b/board/tq/common/Makefile
@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+# D-82229 Seefeld, Germany.
+# Author: Markus Niebel
+#
+
+obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o
+obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o
--- a/board/tq/common/tq_bb.c
+++ b/board/tq/common/tq_bb.c
@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Markus Niebel
+ */
+
+#include <linux/types.h>
+
+#include "tq_bb.h"
+
+int __weak tq_bb_board_mmc_getwp(struct mmc *mmc)
+{
+	return 0;
+}
+
+int __weak tq_bb_board_mmc_getcd(struct mmc *mmc)
+{
+	return 0;
+}
+
+int __weak tq_bb_board_mmc_init(struct bd_info *bis)
+{
+	return 0;
+}
+
+int __weak tq_bb_board_early_init_f(void)
+{
+	return 0;
+}
+
+int __weak tq_bb_board_init(void)
+{
+	return 0;
+}
+
+int __weak tq_bb_board_late_init(void)
+{
+	return 0;
+}
+
+int __weak tq_bb_checkboard(void)
+{
+	return 0;
+}
+
+void __weak tq_bb_board_quiesce_devices(void)
+{
+	;
+}
+
+const char * __weak tq_bb_get_boardname(void)
+{
+	return "INVALID";
+}
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void __weak tq_bb_board_init_f(ulong dummy)
+{
+	;
+}
+
+void __weak tq_bb_spl_board_init(void)
+{
+	;
+}
+#endif /* IS_ENABLED(CONFIG_SPL_BUILD) */
+
+/*
+ * Device Tree Support
+ */
+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)
+int __weak tq_bb_ft_board_setup(void *blob, struct bd_info *bis)
+{
+	return 0;
+}
+
+#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */
--- a/board/tq/common/tq_bb.h
+++ b/board/tq/common/tq_bb.h
@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2013-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Markus Niebel
+ */
+
+#ifndef __TQ_BB_H
+#define __TQ_BB_H
+
+struct mmc;
+struct bd_info;
+struct node_info;
+
+int tq_bb_board_mmc_getwp(struct mmc *mmc);
+int tq_bb_board_mmc_getcd(struct mmc *mmc);
+int tq_bb_board_mmc_init(struct bd_info *bis);
+
+int tq_bb_board_early_init_f(void);
+int tq_bb_board_init(void);
+int tq_bb_board_late_init(void);
+int tq_bb_checkboard(void);
+void tq_bb_board_quiesce_devices(void);
+
+const char *tq_bb_get_boardname(void);
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void tq_bb_board_init_f(ulong dummy);
+void tq_bb_spl_board_init(void);
+#endif
+
+/*
+ * Device Tree Support
+ */
+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)
+int tq_bb_ft_board_setup(void *blob, struct bd_info *bis);
+#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */
+
+#endif /* __TQ_BB_H */
--- a/board/tq/common/tq_sdmmc.c
+++ b/board/tq/common/tq_sdmmc.c
@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ */
+
+#include <command.h>
+#include <env.h>
+#include <mmc.h>
+#include <stdbool.h>
+#include <vsprintf.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+
+#include "tq_bb.h"
+
+static int check_mmc_autodetect(void)
+{
+	/* NO or unset: 0 / YES: 1 */
+	return (env_get_yesno("mmcautodetect") > 0);
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+	return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+	char cmd[32];
+	u32 dev_no;
+
+	dev_no = mmc_get_env_dev();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+	env_set_ulong("mmcblkdev", mmc_map_to_kernel_blk(dev_no));
+
+	snprintf(cmd, ARRAY_SIZE(cmd), "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
--- a/board/tq/tqma6/Kconfig
+++ b/board/tq/tqma6/Kconfig
@ -7,7 +7,8 @@ config SYS_VENDOR
 	default "tq"

 config SYS_CONFIG_NAME
-	default "tqma6"
+	default "tqma6_mba6" if MBA6
+	default "tqma6_wru4" if WRU4

 choice
 	prompt "TQMa6 SoC variant"
@ -71,6 +72,8 @@ choice

 config MBA6
 	bool "TQMa6 on MBa6 Starterkit"
+	select TQ_COMMON_BB
+	select TQ_COMMON_SDMMC
 	select USB
 	select CMD_USB
 	select USB_STORAGE
@ -91,6 +94,7 @@ config MBA6

 config WRU4
 	bool "OHB WRU-IV"
+	select TQ_COMMON_BB
 	help
 	  Select the
 	  OHB Systems AG WRU-IV baseboard.
@ -106,4 +110,6 @@ config IMX_CONFIG
 	default "board/tq/tqma6/tqma6dl.cfg" if TQMA6DL
 	default "board/tq/tqma6/tqma6s.cfg" if TQMA6S

+source "board/tq/common/Kconfig"
+
 endif
--- a/board/tq/tqma6/MAINTAINERS
+++ b/board/tq/tqma6/MAINTAINERS
@ -1,7 +0,0 @@
-TQ-SYSTEMS TQMA6 BOARD
-M:	Markus Niebel <Markus.Niebel@ew.tq-group.com>
-L:	TQ-Systems OSS Team <u-boot@ew.tq-group.com>
-S:	Maintained
-F:	board/tq/tqma6/
-F:	include/configs/tqma6.h
-F:	configs/tqma6*_defconfig
--- a/board/tq/tqma6/Makefile
+++ b/board/tq/tqma6/Makefile
@ -6,6 +6,7 @@
 #

 obj-y  := tqma6.o
+obj-y  += tqma6_emmc.o

 obj-$(CONFIG_MBA6) += tqma6_mba6.o
 obj-$(CONFIG_WRU4) += tqma6_wru4.o
--- a/board/tq/tqma6/tqma6.c
+++ b/board/tq/tqma6/tqma6.c
@ -26,7 +26,8 @@
 #include <power/pfuze100_pmic.h>
 #include <power/pmic.h>

-#include "tqma6_bb.h"
+#include "tqma6_emmc.h"
+#include "../common/tq_bb.h"

 DECLARE_GLOBAL_DATA_PTR;

@ -37,19 +38,21 @@ int dram_init(void)
 	return 0;
 }

-static const uint16_t tqma6_emmc_dsr = 0x0100;
-
 int board_early_init_f(void)
 {
-	return tqma6_bb_board_early_init_f();
+	return tq_bb_board_early_init_f();
 }

 int board_init(void)
 {
+	struct mmc *mmc = find_mmc_device(0);
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

-	tqma6_bb_board_init();
+	tqma6_mmc_detect_card_type(mmc);
+
+	tq_bb_board_init();

 	return 0;
 }
@ -96,11 +99,12 @@ int board_late_init(void)
 {
 	env_set("board_name", tqma6_get_boardname());

-	tqma6_bb_board_late_init();
+	tq_bb_board_late_init();

 	printf("Board: %s on a %s\n", tqma6_get_boardname(),
-	       tqma6_bb_get_boardname());
-	return 0;
+	       tq_bb_get_boardname());
+
+	return tq_bb_checkboard();
 }

 /*
@ -110,17 +114,24 @@ int board_late_init(void)
 #define MODELSTRLEN 32u
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
+	struct mmc *mmc = find_mmc_device(0);
 	char modelstr[MODELSTRLEN];

 	snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
-		 tqma6_bb_get_boardname());
+		 tq_bb_get_boardname());
 	do_fixup_by_path_string(blob, "/", "model", modelstr);
 	fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
-	/* bring in eMMC dsr settings */
-	do_fixup_by_path_u32(blob,
-			     "/soc/aips-bus@02100000/usdhc@02198000",
-			     "dsr", tqma6_emmc_dsr, 2);
-	tqma6_bb_ft_board_setup(blob, bd);
+
+	/* bring in eMMC dsr settings if needed */
+	if (mmc && (!mmc_init(mmc))) {
+		if (tqma6_emmc_need_dsr(mmc) > 0) {
+			tqma6_ft_fixup_emmc_dsr(blob,
+						"/soc/bus@2100000/mmc@2198000",
+						TQMA6_EMMC_DSR);
+		}
+	} else {
+		puts("eMMC: not present?\n");
+	}

 	return 0;
 }
--- a/board/tq/tqma6/tqma6.env
+++ b/board/tq/tqma6/tqma6.env
@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ * TQMa6 environment
+ */
+
+#include <env/tq/tq-imx-shared.env>
+
+board=tqma6
+boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}"
+emmc_bootp_start=TQMA6_MMC_UBOOT_SECTOR_START
+emmc_dev=0
+fdt_addr_r=TQMA6_FDT_ADDRESS
+fdtoverlay_addr_r=TQMA6_FDT_OVERLAY_ADDR
+image=zImage
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+pxefile_addr_r=CONFIG_SYS_LOAD_ADDR
+ramdisk_addr_r=TQMA6_INITRD_ADDRESS
+mmcautodetect=yes
+mmcblkdev=0
+mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
+netdev=eth0
+sd_dev=1
+uboot=u-boot-with-spl.imx
+uboot_mmc_start=TQMA6_MMC_UBOOT_SECTOR_START
+uboot_mmc_size=TQMA6_MMC_UBOOT_SECTOR_COUNT
+uboot_spi_sector_size=TQMA6_SPI_FLASH_SECTOR_SIZE
+uboot_spi_start=TQMA6_SPI_UBOOT_START
+uboot_spi_size=TQMA6_SPI_UBOOT_SIZE
+
+#ifdef CONFIG_USB_FUNCTION_FASTBOOT
+
+/* 0=user 1=boot1 2=boot2 */
+fastboot_mmc_boot_partition = 1
+
+fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0
+
+fastboot_raw_partition_bootloader=
+	TQMA6_MMC_UBOOT_SECTOR_START TQMA6_MMC_UBOOT_SECTOR_COUNT mmcpart
+	"${fastboot_mmc_boot_partition}"
+
+fastbootcmd=fastboot usb 0
+
+#endif /* CONFIG_USB_FUNCTION_FASTBOOT */
--- a/board/tq/tqma6/tqma6_bb.h
+++ b/board/tq/tqma6/tqma6_bb.h
@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2013-2014 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
- * D-82229 Seefeld, Germany.
- * Author: Markus Niebel
- */
-
-#ifndef __TQMA6_BB__
-#define __TQMA6_BB__
-
-int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
-int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
-int tqma6_bb_board_mmc_init(struct bd_info *bis);
-
-int tqma6_bb_board_early_init_f(void);
-int tqma6_bb_board_init(void);
-int tqma6_bb_board_late_init(void);
-int tqma6_bb_checkboard(void);
-
-const char *tqma6_bb_get_boardname(void);
-/*
- * Device Tree Support
- */
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd);
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
-
-#endif
--- a/board/tq/tqma6/tqma6_emmc.c
+++ b/board/tq/tqma6/tqma6_emmc.c
@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2017-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Markus Niebel
+ */
+
+#include <fdt_support.h>
+#include <mmc.h>
+
+#include "tqma6_emmc.h"
+
+struct emmc_dsr_lookup {
+	uint mfgid;
+	char *pnm;
+	int dsr_needed;
+};
+
+static const struct emmc_dsr_lookup dsr_tbl[] = {
+	/* Micron, eMMC 4.41 */
+	{ 0xfe, "MMC02G", 1 },
+	{ 0xfe, "MMC04G", 1 },
+	{ 0xfe, "MMC08G", 1 },
+	/* Micron, eMMC 5.0 4 GB*/
+	{ 0x13, "Q1J54A", 1 },
+	{ 0x13, "Q2J54A", 1 },
+	/* Micron, eMMC 5.0 8 GB*/
+	{ 0x13, "Q2J55L", 0 },
+	/* Samsung, eMMC 5.0 */
+	{ 0x15, "8GSD3R", 0 },
+	{ 0x15, "AGSD3R", 0 },
+	{ 0x15, "BGSD3R", 0 },
+	{ 0x15, "CGSD3R", 0 },
+	/* SanDisk, iNAND 7250 5.1 */
+	{ 0x45, "DG4008", 0 },
+	{ 0x45, "DG4016", 0 },
+	{ 0x45, "DG4032", 0 },
+	{ 0x45, "DG4064", 0 },
+	/* Kingston */
+	{ 0x100, "?????", 0 },
+};
+
+int tqma6_emmc_need_dsr(const struct mmc *mmc)
+{
+	uint mfgid = mmc->cid[0] >> 24;
+	char name[7];
+	int ret = -1;
+	size_t i;
+
+	if (IS_SD(mmc))
+		return 0;
+
+	sprintf(name, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, (mmc->cid[1] >> 24),
+		(mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff,
+		mmc->cid[1] & 0xff, (mmc->cid[2] >> 24));
+
+	for (i = 0; i < ARRAY_SIZE(dsr_tbl) && (ret < 0); ++i) {
+		if (dsr_tbl[i].mfgid == mfgid &&
+		    (!strncmp(name, dsr_tbl[i].pnm, 6))) {
+			ret = dsr_tbl[i].dsr_needed;
+			debug("MFG: %x PNM: %s\n", mfgid, name);
+		}
+	}
+
+	if (ret < 0) {
+		printf("eMMC unknown: MFG: %x PNM: %s\n", mfgid, name);
+		/* request DSR, even if not known if supported to be safe */
+		ret = 1;
+	}
+
+	return ret;
+}
+
+void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value)
+{
+	do_fixup_by_path_u32(blob, path, "dsr", value, 1);
+}
+
+void tqma6_mmc_detect_card_type(struct mmc *mmc)
+{
+	struct mmc *emmc = find_mmc_device(0);
+
+	if (emmc != mmc)
+		return;
+
+	if (tqma6_emmc_need_dsr(mmc) > 0)
+		mmc_set_dsr(mmc, TQMA6_EMMC_DSR);
+}
--- a/board/tq/tqma6/tqma6_emmc.h
+++ b/board/tq/tqma6/tqma6_emmc.h
@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2017-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Markus Niebel
+ */
+
+#ifndef __TQMA6_EMMC_H__
+#define __TQMA6_EMMC_H__
+
+#define TQMA6_EMMC_DSR		0x0100
+
+struct mmc;
+
+int tqma6_emmc_need_dsr(const struct mmc *mmc);
+void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value);
+void tqma6_mmc_detect_card_type(struct mmc *mmc);
+
+#endif /* __TQMA6_EMMC_H__ */
--- a/board/tq/tqma6/tqma6_mba6.c
+++ b/board/tq/tqma6/tqma6_mba6.c
@ -31,7 +31,7 @@
 #include <mmc.h>
 #include <netdev.h>

-#include "tqma6_bb.h"
+#include "../common/tq_bb.h"

 #if defined(CONFIG_TQMA6Q)

@ -126,34 +126,20 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }

-int tqma6_bb_board_early_init_f(void)
-{
-	return 0;
-}
-
-int tqma6_bb_board_init(void)
+int tq_bb_board_init(void)
 {
 	mba6_setup_iomuxc_enet();

 	return 0;
 }

-int tqma6_bb_board_late_init(void)
-{
-	return 0;
-}
-
-const char *tqma6_bb_get_boardname(void)
+const char *tq_bb_get_boardname(void)
 {
 	return "MBa6x";
 }

-/*
- * Device Tree Support
- */
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
+int tq_bb_board_late_init(void)
 {
- /* TBD */
+	board_late_mmc_env_init();
+	return 0;
 }
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
--- a/board/tq/tqma6/tqma6_wru4.c
+++ b/board/tq/tqma6/tqma6_wru4.c
@ -33,7 +33,7 @@
 #include <mmc.h>
 #include <netdev.h>

-#include "tqma6_bb.h"
+#include "../common/tq_bb.h"

 /* UART */
 #define UART4_PAD_CTRL (			\
@ -95,7 +95,7 @@ static struct fsl_esdhc_cfg usdhc2_cfg = {
 	.max_bus_width = 4,
 };

-int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
+int tq_bb_board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
@ -106,7 +106,7 @@ int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
 	return ret;
 }

-int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
+int tq_bb_board_mmc_getwp(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
@ -117,7 +117,7 @@ int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
 	return ret;
 }

-int tqma6_bb_board_mmc_init(struct bd_info *bis)
+int tq_bb_board_mmc_init(struct bd_info *bis)
 {
 	int ret;

@ -256,14 +256,14 @@ static void gpio_init(void)
 		gpio_direction_output(GPIO_UART3_PWRON, 0);
 }

-int tqma6_bb_board_early_init_f(void)
+int tq_bb_board_early_init_f(void)
 {
 	setup_iomuxc_uart4();

 	return 0;
 }

-int tqma6_bb_board_init(void)
+int tq_bb_board_init(void)
 {
 	setup_iomuxc_enet();

@ -279,12 +279,7 @@ int tqma6_bb_board_init(void)
 	return 0;
 }

-int tqma6_bb_board_late_init(void)
-{
-	return 0;
-}
-
-const char *tqma6_bb_get_boardname(void)
+const char *tq_bb_get_boardname(void)
 {
 	return "WRU-IV";
 }
@ -331,13 +326,3 @@ int board_ehci_power(int port, int on)

 	return 0;
 }
-
-/*
- * Device Tree Support
- */
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
-{
-	/* TBD */
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2"
 CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y
@ -78,8 +75,6 @@ CONFIG_CLK_IMX8MP=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_SUPPORT_EMMC_BOOT=y
@ -98,12 +93,13 @@ CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_SPL_POWER_LEGACY=y
-CONFIG_POWER_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
--- a/configs/imx8mp-libra-fpsc_defconfig
+++ b/configs/imx8mp-libra-fpsc_defconfig
@ -9,7 +9,6 @@ CONFIG_SF_DEFAULT_SPEED=80000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3C0000
 CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc"
 CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000
@ -105,8 +104,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
 CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x51
 CONFIG_SUPPORT_EMMC_BOOT=y
@ -138,15 +135,16 @@ CONFIG_PHY_IMX8MQ_USB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_SPL_POWER_LEGACY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8M_POWER_DOMAIN=y
 CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_POWER_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_RNG=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@ -32,7 +32,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2068
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
--- a/configs/imx91-phycore_defconfig
+++ b/configs/imx91-phycore_defconfig
@ -0,0 +1,167 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SOURCE_FILE="phycore_imx91_93"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_PHYTEC_SOM_DETECTION=y
+CONFIG_PHYTEC_EEPROM_BUS=2
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-phyboard-segin"
+CONFIG_TARGET_PHYCORE_IMX91=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x204E0000
+CONFIG_SPL_TEXT_BASE=0x204A0000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20498000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x720000
+CONFIG_CMD_DEKBLOB=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_REMAKE_ELF=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_BOOTDEV is not set
+# CONFIG_CMD_BOOTMETH is not set
+# CONFIG_CMD_BOOTSTD is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=4096
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_REDUNDANT=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_MMC_DEVICE_INDEX=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_IMX93=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_ULP_WATCHDOG=y
+# CONFIG_RSA is not set
+# CONFIG_SPL_SHA256 is not set
+CONFIG_LZO=y
+CONFIG_BZIP2=y
--- a/configs/imx93-phycore_defconfig
+++ b/configs/imx93-phycore_defconfig
@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x20000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SOURCE_FILE="phycore_imx93"
+CONFIG_ENV_SOURCE_FILE="phycore_imx91_93"
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_PHYTEC_SOM_DETECTION=y
 CONFIG_PHYTEC_EEPROM_BUS=2
--- a/configs/imx93_frdm_defconfig
+++ b/configs/imx93_frdm_defconfig
@ -35,7 +35,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x26000
 CONFIG_SPL_BOARD_INIT=y
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@ -36,7 +36,6 @@ CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_SYS_DEVICE_NULLDEV is not set
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_BOOTZ=y
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_BOOTZ=y
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_BOOTZ=y
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_BOOTZ=y
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_BOOTZ=y
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@ -10,7 +10,6 @@ CONFIG_SF_DEFAULT_SPEED=80000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3C0000
 CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
 CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000
@ -113,8 +112,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
 CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x51
 CONFIG_SUPPORT_EMMC_BOOT=y
@ -144,15 +141,16 @@ CONFIG_PHY_IMX8MQ_USB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_SPL_POWER_LEGACY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8M_POWER_DOMAIN=y
 CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_POWER_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_RNG=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
--- a/configs/toradex-smarc-imx95_defconfig
+++ b/configs/toradex-smarc-imx95_defconfig
@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=3
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx95-toradex-smarc-dev"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx95-toradex-smarc-dev"
 CONFIG_TARGET_TORADEX_SMARC_IMX95=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@ -125,6 +125,7 @@ CONFIG_SPL_FIRMWARE=y
 # CONFIG_SCMI_AGENT_SMCCC is not set
 CONFIG_IMX_SM_CPU=y
 CONFIG_IMX_SM_LMM=y
+CONFIG_GPIO_HOG=y
 CONFIG_IMX_RGPIO2P=y
 CONFIG_DM_PCA953X=y
 CONFIG_SPL_DM_PCA953X=y
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-verdin-wifi-dev"
 CONFIG_TARGET_VERDIN_IMX8MP=y
@ -119,8 +115,6 @@ CONFIG_SPL_GPIO_HOG=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_I2C_EEPROM=y
@ -152,14 +146,15 @@ CONFIG_PHY_IMX8M_PCIE=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_SPL_POWER_LEGACY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8M_POWER_DOMAIN=y
 CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_POWER_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_RNG=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
--- a/doc/board/phytec/imx91-93-phycore.rst
+++ b/doc/board/phytec/imx91-93-phycore.rst
@ -1,9 +1,11 @@
 .. SPDX-License-Identifier: GPL-2.0+

-phyCORE-i.MX 93
-===============
+phyCORE-i.MX 91/93
+==================

-U-Boot for the phyCORE-i.MX 93.
+U-Boot for the phyCORE-i.MX 91/93. Both SoC variants, that is i.MX 91 and i.MX 93,
+are supported by same board code, however each variant uses different defconfig
+and ATF/ELE firmware blobs. Please follow the correct steps for the populated SoC.

 Quick Start
 -----------
@ -18,7 +20,17 @@ Get and Build the ARM Trusted firmware

 Note: srctree is U-Boot source directory
 Get ATF from: https://github.com/nxp-imx/imx-atf/
-branch: lf_v2.8
+branch: lf_v2.12
+
+For phyCORE-i.MX 91 variant:
+
+.. code-block:: bash
+
+   $ unset LDFLAGS
+   $ make PLAT=imx91 bl31
+   $ cp build/imx91/release/bl31.bin $(srctree)
+
+For phyCORE-i.MX 93 variant:

 .. code-block:: bash

@ -41,14 +53,24 @@ Get ahab-container.img

 .. code-block:: bash

-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin
-   $ chmod +x firmware-sentinel-0.11.bin
-   $ ./firmware-sentinel-0.11.bin
-   $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree)
+   $ wget  https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin
+   $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin
+   $ ./firmware-ele-imx-1.3.0-17945fc.bin
+   $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree)
+   $ cp firmware-ele-imx-1.3.0-17945fc/mx93a1-ahab-container.img $(srctree)

 Build U-Boot
 ------------

+For phyCORE-i.MX 91 variant:
+
+.. code-block:: bash
+
+   $ make imx91-phycore_defconfig
+   $ make
+
+For phyCORE-i.MX 93 variant:
+
 .. code-block:: bash

   $ make imx93-phycore_defconfig
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@ -8,7 +8,7 @@ PHYTEC

   imx8mp-libra-fpsc
   imx8mm-phygate-tauri-l
-   imx93-phycore
+   imx91-93-phycore
   phycore-am62x
   phycore-am62ax
   phycore-am64x
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@ -3,6 +3,7 @@ if ARM || PPC
 config FSL_CAAM
 	bool "Freescale Crypto Driver Support"
 	select SHA_HW_ACCEL
+	select ARCH_MISC_INIT
 	# hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
 	select MISC if DM
 	imply SPL_CRYPTO if (ARM && SPL)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@ -728,15 +728,31 @@ static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
 static int imx_pcie_dm_probe(struct udevice *dev)
 {
 	struct imx_pcie_priv *priv = dev_get_priv(dev);
+	int ret;

 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 	device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie);
 #endif

 	/* if PERST# valid from dt then assert it */
-	gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
-			     GPIOD_IS_OUT);
-	priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high");
+	ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
+				   GPIOD_IS_OUT);
+	if (!ret) {
+		/*
+		 * Legacy property, invert assert logic based on
+		 * reset-gpio-active-high. This won't work if flags are not
+		 * matching the reset-gpio-active-high.
+		 */
+		priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high");
+	} else {
+		/*
+		 * Linux kernel upstream property, assert active level based on
+		 * GPIO flags, thus leave priv->reset_active_high=0.
+		 */
+		gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
+				     GPIOD_IS_OUT);
+	}
+
 	if (dm_gpio_is_valid(&priv->reset_gpio)) {
 		dm_gpio_set_value(&priv->reset_gpio,
 				  priv->reset_active_high ? 0 : 1);
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@ -275,7 +275,7 @@ int espi_xfer(struct fsl_spi_slave *fsl,  uint cs, unsigned int bitlen,
 			}
 		}
 		if (data_in) {
-			memcpy(data_in, buffer + 2 * cmd_len, tran_len);
+			memcpy(data_in, buffer + rx_offset, tran_len);
 			if (*buffer == 0x0b) {
 				data_in += tran_len;
 				data_len -= tran_len;
--- a/include/configs/phycore_imx91_93.h
+++ b/include/configs/phycore_imx91_93.h
@ -6,8 +6,8 @@
 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
 */

-#ifndef __PHYCORE_IMX93_H
-#define __PHYCORE_IMX93_H
+#ifndef __PHYCORE_IMX91_93_H
+#define __PHYCORE_IMX91_93_H

 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
@ -25,4 +25,4 @@
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR          WDG3_BASE_ADDR

-#endif /* __PHYCORE_IMX93_H */
+#endif /* __PHYCORE_IMX91_93_H */
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@ -7,256 +7,22 @@
 * Configuration settings for the TQ-Systems TQMa6<Q,D,DL,S> module.
 */

-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* place code in last 4 MiB of RAM */
+#ifndef __TQMA6_CONFIG_H
+#define __TQMA6_CONFIG_H

 #include "mx6_common.h"

-#if defined(CONFIG_TQMA6S)
-#define PHYS_SDRAM_SIZE			(512u * SZ_1M)
-#elif defined(CONFIG_TQMA6DL)
-#define PHYS_SDRAM_SIZE			(SZ_1G)
-#elif defined(CONFIG_TQMA6Q)
-#define PHYS_SDRAM_SIZE			(SZ_1G)
-#endif
-
-/* SPI Flash */
-
-#define TQMA6_SPI_FLASH_SECTOR_SIZE	SZ_64K
-
-#if !defined(CONFIG_DM_PMIC)
-#define CFG_POWER_PFUZE100_I2C_ADDR	0x08
-#define TQMA6_PFUZE100_I2C_BUS		2
-#endif
-
 /* MMC Configs */
 #define CFG_SYS_FSL_ESDHC_ADDR	0

-#if defined(CONFIG_TQMA6X_MMC_BOOT)
-
-#define TQMA6_UBOOT_OFFSET		SZ_1K
-#define TQMA6_UBOOT_SECTOR_START	0x2
-#define TQMA6_UBOOT_SECTOR_COUNT	0x7fe
-
-#define TQMA6_FDT_OFFSET		(2 * SZ_1M)
-#define TQMA6_FDT_SECTOR_START		0x1000
-#define TQMA6_FDT_SECTOR_COUNT		0x800
-
-#define TQMA6_KERNEL_SECTOR_START	0x2000
-#define TQMA6_KERNEL_SECTOR_COUNT	0x2000
-
-#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS                                       \
-	"uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0"                \
-	"uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0"                 \
-	"fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0"                    \
-	"fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0"                     \
-	"kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0"              \
-	"kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0"               \
-	"mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0"                       \
-	"loadimage=mmc dev ${mmcdev}; "                                        \
-		"mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0"       \
-	"loadfdt=mmc dev ${mmcdev}; "                                          \
-		"mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0"             \
-	"update_uboot=if tftp ${uboot}; then "                                 \
-		"if itest ${filesize} > 0; then "                              \
-			"mmc dev ${mmcdev}; mmc rescan; "                      \
-			"setexpr blkc ${filesize} + 0x1ff; "                   \
-			"setexpr blkc ${blkc} / 0x200; "                       \
-			"if itest ${blkc} <= ${uboot_size}; then "             \
-				"mmc write ${loadaddr} ${uboot_start} "        \
-					"${blkc}; "                            \
-			"fi; "                                                 \
-		"fi; fi; "                                                     \
-		"setenv filesize; setenv blkc \0"                              \
-	"update_kernel=run kernel_name; "                                      \
-		"if tftp ${kernel}; then "                                     \
-			"if itest ${filesize} > 0; then "                      \
-				"mmc dev ${mmcdev}; mmc rescan; "              \
-				"setexpr blkc ${filesize} + 0x1ff; "           \
-				"setexpr blkc ${blkc} / 0x200; "               \
-				"if itest ${blkc} <= ${kernel_size}; then "    \
-					"mmc write ${loadaddr} "               \
-						"${kernel_start} ${blkc}; "    \
-				"fi; "                                         \
-			"fi; "                                                 \
-		"fi; "                                                         \
-		"setenv filesize; setenv blkc \0"                              \
-	"update_fdt=if tftp ${fdt_file}; then "                                \
-		"if itest ${filesize} > 0; then "                              \
-			"mmc dev ${mmcdev}; mmc rescan; "                      \
-			"setexpr blkc ${filesize} + 0x1ff; "                   \
-			"setexpr blkc ${blkc} / 0x200; "                       \
-			"if itest ${blkc} <= ${fdt_size}; then "               \
-				"mmc write ${loadaddr} ${fdt_start} ${blkc}; " \
-			"fi; "                                                 \
-		"fi; fi; "                                                     \
-		"setenv filesize; setenv blkc \0"                              \
-
-#elif defined(CONFIG_TQMA6X_SPI_BOOT)
-
-#define TQMA6_UBOOT_OFFSET		0x400
-#define TQMA6_UBOOT_SECTOR_START	0x0
-/* max u-boot size: 512k */
-#define TQMA6_UBOOT_SECTOR_SIZE		TQMA6_SPI_FLASH_SECTOR_SIZE
-#define TQMA6_UBOOT_SECTOR_COUNT	0x8
-#define TQMA6_UBOOT_SIZE		(TQMA6_UBOOT_SECTOR_SIZE * \
-					 TQMA6_UBOOT_SECTOR_COUNT)
-
-#define TQMA6_FDT_OFFSET		(CONFIG_ENV_OFFSET_REDUND + \
-					 CONFIG_ENV_SECT_SIZE)
-#define TQMA6_FDT_SECT_SIZE		(TQMA6_SPI_FLASH_SECTOR_SIZE)
-
-#define TQMA6_FDT_SECTOR_START		0x0a /* 8 Sector u-boot, 2 Sector env */
-#define TQMA6_FDT_SECTOR_COUNT		0x01
-
-#define TQMA6_KERNEL_SECTOR_START	0x10
-#define TQMA6_KERNEL_SECTOR_COUNT	0x60
-
-#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS                                       \
-	"mmcblkdev=0\0"                                                        \
-	"uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0"                     \
-	"uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0"              \
-	"fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0"                    \
-	"fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0"                  \
-	"kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0"              \
-	"kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0"            \
-	"update_uboot=if tftp ${uboot}; then "                                 \
-		"if itest ${filesize} > 0; then "                              \
-			"setexpr blkc ${filesize} + "                          \
-				__stringify(TQMA6_UBOOT_OFFSET) "; "           \
-			"setexpr size ${uboot_sectors} * "                     \
-				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
-			"if itest ${blkc} <= ${size}; then "                   \
-				"sf probe; "                                   \
-				"sf erase 0 ${size}; "                         \
-				"sf write ${loadaddr} ${uboot_offset} "        \
-					"${filesize}; "                        \
-			"fi; "                                                 \
-		"fi; fi; "                                                     \
-		"setenv filesize 0; setenv blkc; setenv size \0"               \
-	"update_kernel=run kernel_name; if tftp ${kernel}; then "              \
-		"if itest ${filesize} > 0; then "                              \
-			"setexpr size ${kernel_sectors} * "                    \
-				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
-			"setexpr offset ${kernel_start} * "                    \
-				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
-			"if itest ${filesize} <= ${size}; then "               \
-				"sf probe; "                                   \
-				"sf erase ${offset} ${size}; "                 \
-				"sf write ${loadaddr} ${offset} "              \
-					"${filesize}; "                        \
-			"fi; "                                                 \
-		"fi; fi; "                                                     \
-		"setenv filesize 0; setenv size ; setenv offset\0"             \
-	"update_fdt=if tftp ${fdt_file}; then "                                \
-		"if itest ${filesize} > 0; then "                              \
-			"setexpr size ${fdt_sectors} * "                       \
-				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
-			"setexpr offset ${fdt_start} * "                       \
-				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
-			"if itest ${filesize} <= ${size}; then "               \
-				"sf probe; "                                   \
-				"sf erase ${offset} ${size}; "                 \
-				"sf write ${loadaddr} ${offset} "              \
-					"${filesize}; "                        \
-			"fi; "                                                 \
-		"fi; fi; "                                                     \
-		"setenv filesize 0; setenv size ; setenv offset\0"             \
-	"loadimage=sf probe; "                                                 \
-		"setexpr size ${kernel_sectors} * "                            \
-			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
-		"setexpr offset ${kernel_start} * "                            \
-			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
-		"sf read ${loadaddr} ${offset} ${size}; "                      \
-		"setenv size ; setenv offset\0"                                \
-	"loadfdt=sf probe; "                                                   \
-		"setexpr size ${fdt_sectors} * "                               \
-			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
-		"setexpr offset ${fdt_start} * "                               \
-			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
-		"sf read ${fdt_addr} ${offset} ${size}; "                      \
-		"setenv size ; setenv offset\0"
-#else
-
-#error "need to define boot source"
-
-#endif
-
 /* 128 MiB offset as in ARM related docu for linux suggested */
 #define TQMA6_FDT_ADDRESS		0x18000000

-/* set to a resonable value, changeable by user */
-#define TQMA6_CMA_SIZE                 160M
+/* 256KiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_256K) */
+#define TQMA6_FDT_OVERLAY_ADDR		0x18040000

-#define CFG_EXTRA_ENV_SETTINGS                                              \
-	"board=tqma6\0"                                                        \
-	"uimage=uImage\0"                                                      \
-	"zimage=zImage\0"                                                      \
-	"boot_type=bootz\0"                                                    \
-	"kernel_name=if test \"${boot_type}\" != bootz; then "                 \
-		"setenv kernel ${uimage}; "                                    \
-		"else setenv kernel ${zimage}; fi\0"                           \
-	"uboot=u-boot.imx\0"                                                   \
-	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0"                               \
-	"fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0"                          \
-	"console=" CONSOLE_DEV "\0"                                            \
-	"cma_size="__stringify(TQMA6_CMA_SIZE)"\0"                             \
-	"initrd_high=0xffffffff\0"                                             \
-	"rootfsmode=ro\0"                                                      \
-	"addcma=setenv bootargs ${bootargs} cma=${cma_size}\0"                 \
-	"addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0"  \
-	"addfb=setenv bootargs ${bootargs} "                                   \
-		"imx-fbdev.legacyfb_depth=32 consoleblank=0\0"                 \
-	"mmcpart=2\0"                                                          \
-	"mmcblkdev=0\0"                                                        \
-	"mmcargs=run addmmc addtty addfb addcma\0"                             \
-	"addmmc=setenv bootargs ${bootargs} "                                  \
-		"root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} "       \
-		"rootwait\0"                                                   \
-	"mmcboot=echo Booting from mmc ...; "                                  \
-		"setenv bootargs; "                                            \
-		"run mmcargs; "                                                \
-		"run loadimage; "                                              \
-		"if run loadfdt; then "                                        \
-			"echo boot device tree kernel ...; "                   \
-			"${boot_type} ${loadaddr} - ${fdt_addr}; "             \
-		"else "                                                        \
-			"${boot_type}; "                                       \
-		"fi;\0"                                                        \
-		"setenv bootargs \0"                                           \
-	"netdev=eth0\0"                                                        \
-	"rootpath=/srv/nfs/tqma6\0"                                            \
-	"ipmode=static\0"                                                      \
-	"netargs=run addnfs addip addtty addfb addcma\0"                       \
-	"addnfs=setenv bootargs ${bootargs} "                                  \
-		"root=/dev/nfs rw "                                            \
-		"nfsroot=${serverip}:${rootpath},v3,tcp;\0"                    \
-	"addip_static=setenv bootargs ${bootargs} "                            \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"            \
-		"${hostname}:${netdev}:off\0"                                  \
-	"addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0"                  \
-	"addip=if test \"${ipmode}\" != static; then "                         \
-		"run addip_dynamic; else run addip_static; fi\0"               \
-	"set_getcmd=if test \"${ipmode}\" != static; then "                    \
-		"setenv getcmd dhcp; setenv autoload yes; "                    \
-		"else setenv getcmd tftp; setenv autoload no; fi\0"            \
-	"netboot=echo Booting from net ...; "                                  \
-		"run kernel_name; "                                            \
-		"run set_getcmd; "                                             \
-		"setenv bootargs; "                                            \
-		"run netargs; "                                                \
-		"if ${getcmd} ${kernel}; then "                                \
-			"if ${getcmd} ${fdt_addr} ${fdt_file}; then "          \
-				"${boot_type} ${loadaddr} - ${fdt_addr}; "     \
-			"fi; "                                                 \
-		"fi; "                                                         \
-		"echo ... failed\0"                                            \
-	"panicboot=echo No boot device !!! reset\0"                            \
-	TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS                                      \
+/* 16MiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_16M) */
+#define TQMA6_INITRD_ADDRESS		0x19000000

 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
@ -265,19 +31,11 @@
 #define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
 #define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE

-/*
- * All the defines above are for the TQMa6 SoM
- *
- * Now include the baseboard specific configuration
- */
-#ifdef CONFIG_MBA6
-#include "tqma6_mba6.h"
-#elif CONFIG_WRU4
-#include "tqma6_wru4.h"
-#else
-#error "No baseboard for the TQMa6 defined!"
-#endif
+#define TQMA6_MMC_UBOOT_SECTOR_START	0x2
+#define TQMA6_MMC_UBOOT_SECTOR_COUNT	0x7fe

-/* Support at least the sensor on TQMa6 SOM */
+#define TQMA6_SPI_FLASH_SECTOR_SIZE	SZ_64K
+#define TQMA6_SPI_UBOOT_START		0x400
+#define TQMA6_SPI_UBOOT_SIZE		0xc0000

-#endif /* __CONFIG_H */
+#endif /* __TQMA6_CONFIG_H */
--- a/include/configs/tqma6_mba6.h
+++ b/include/configs/tqma6_mba6.h
@ -11,9 +11,8 @@
 #ifndef __CONFIG_TQMA6_MBA6_H
 #define __CONFIG_TQMA6_MBA6_H

-#define CFG_FEC_MXC_PHYADDR		0x03
+#include "tqma6.h"

 #define CFG_MXC_UART_BASE		UART2_BASE
-#define CONSOLE_DEV		"ttymxc1"

 #endif /* __CONFIG_TQMA6_MBA6_H */
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@ -6,6 +6,8 @@
 #ifndef __CONFIG_TQMA6_WRU4_H
 #define __CONFIG_TQMA6_WRU4_H

+#include "tqma6.h"
+
 /* Ethernet */
 #define CFG_FEC_MXC_PHYADDR		0x01

--- a/include/env/tq/mmc.env
+++ b/include/env/tq/mmc.env
@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ * shared mmc environment for TQ boards
+ */
+
+addmmc=
+	setenv bootargs "${bootargs}"
+	root=/dev/mmcblk"${mmcblkdev}"p"${mmcrootpart}" "${rootfsmode}" rootwait;
+
+get_blockcount=
+	setexpr blkc "${filesize}" + 0x1ff;
+	setexpr blkc "${blkc}" / 0x200;
+
+load_mmc=
+	mmc dev "${mmcdev}"; mmc rescan;
+	load mmc "${mmcdev}":"${mmcpart}" "${kernel_addr_r}" /boot/"${image}";
+	load mmc "${mmcdev}":"${mmcpart}" "${fdt_addr_r}" /boot/"${fdtfile}";
+	fdt address "${fdt_addr_r}";
+        fdt resize 0x100000;
+	for overlay in "${fdt_overlays}"; do
+		load mmc "${mmcdev}":"${mmcpart}" "${fdtoverlay_addr_r}"
+                        /boot/"${overlay}" && fdt apply "${fdtoverlay_addr_r}";
+	done;
+
+mmcargs=run addtty addmmc
+
+mmcboot=
+	echo "Booting from mmc ...";
+	setenv bootargs && run mmcargs &&
+	if run load_mmc; then
+		run boot_os;
+	else
+		echo "ERROR: loading from mmc";
+	fi;
+
+mmcpart=2
+
+mmc_finish_update_uboot=
+	mmc write "${loadaddr}" "${update_start_blk}" "${blkc}";
+	mmc dev "${mmcdev}" 0;
+	setenv update_part;
+	setenv update_start_blk;
+	setenv blkc;
+
+mmc_prepare_update_uboot=
+	echo "Write U-Boot to mmc "${mmcdev}" ...";
+	mmc dev "${mmcdev}"; mmc rescan;
+	run get_blockcount;
+	setenv update_start_blk "${uboot_mmc_start}";
+	setenv update_part 0;
+
+mmc_switch_part=
+	mmc partconf "${mmcdev}" update_part;
+	mmc dev "${mmcdev}" "${update_part}";
+
+mmcrootpart=2
+
+update_uboot_mmc=
+	run check_ipaddr;
+	if tftp "${uboot}"; then
+		run mmc_prepare_update_uboot;
+		if itest "${blkc}" >= "${uboot_mmc_size}"; then
+			echo "ERROR: size to large ...";
+			exit;
+		fi;
+		if itest "${mmcdev}" == "${emmc_dev}"; then
+			run mmc_switch_part;
+			if itest "${update_part}" > 0 ; then
+				if env exists emmc_bootp_start; then
+					setenv update_start_blk "${emmc_bootp_start}";
+				else
+					echo "ERROR: eMMC boot partition block unset";
+					exit;
+				fi;
+			fi;
+		fi;
+		run mmc_finish_update_uboot;
+	fi;
--- a/include/env/tq/nfs.env
+++ b/include/env/tq/nfs.env
@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ * shared nfs environment for TQ boards
+ */
+
+addnfs=
+	setenv bootargs "${bootargs}" root=/dev/nfs rw
+        nfsroot="${serverip}":"${rootpath}",v3,tcp
+
+load_nfs=
+	nfs "${kernel_addr_r}" "${serverip}":"${rootpath}"/boot/"${image}";
+	nfs "${fdt_addr_r}" "${serverip}":"${rootpath}"/boot/"${fdtfile}";
+	fdt address "${fdt_addr_r}";
+	fdt resize 0x100000;
+	for overlay in "${fdt_overlays}"; do
+		nfs "${fdtoverlay_addr_r}"
+		        "${serverip}":"${rootpath}"/boot/"${overlay}" &&
+			fdt apply "${fdtoverlay_addr_r}";
+	done;
+
+load_tftp=
+	tftp "${kernel_addr_r}" "${image}";
+	tftp "${fdt_addr_r}" "${fdtfile}";
+	fdt address "${fdt_addr_r}";
+	fdt resize 0x100000;
+	for overlay in "${fdt_overlays}"; do
+		if tftp "${fdtoverlay_addr_r}" "${overlay}"; then
+			fdt apply "${fdtoverlay_addr_r}";
+		else
+			exit;
+		fi;
+	done;
+
+netargs=run addnfs addip addtty
+
+netloadcmd=load_tftp
+
+nfsboot=
+	echo "Booting from NFS ...";
+	setenv bootargs;
+	run netargs;
+	run check_ipaddr;
+	if run ${netloadcmd}; then
+		run boot_os;
+	else
+		echo "ERROR: loading from NFS";
+	fi;
--- a/include/env/tq/spi.env
+++ b/include/env/tq/spi.env
@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ * shared spi environment for TQ boards
+ */
+
+update_uboot_spi=
+	run check_ipaddr;
+	if tftp ${uboot}; then
+		if itest "${filesize}" >= "${uboot_spi_size}"; then
+			echo "ERROR: size to large ...";
+			exit;
+		fi;
+		echo "Write u-boot image to SPI NOR ...";
+		if sf probe; then
+			run write_uboot_spi;
+		fi;
+	fi;
+
+write_uboot_spi=sf update "${loadaddr}" "${uboot_spi_start}" "${filesize}"
--- a/include/env/tq/tq-imx-shared.env
+++ b/include/env/tq/tq-imx-shared.env
@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ * shared environment for TQ imx boards
+ */
+
+#ifdef CONFIG_CMD_SF
+#include "spi.env"
+#ifdef CONFIG_CMD_UBIFS
+#include "ubi.env"
+#endif /* CONFIG_CMD_UBIFS */
+#endif /* CONFIG_CMD_SF */
+
+#ifdef CONFIG_CMD_MMC
+#include "mmc.env"
+#endif
+
+#ifdef CONFIG_CMD_NFS
+#include "nfs.env"
+#endif
+
+addip=
+	run check_ipaddr;
+	setenv bootargs "${bootargs}"
+	ip="${ipaddr}":"${serverip}":"${gatewayip}":"${netmask}":"${hostname}":"${netdev}":off
+
+addtty=setenv bootargs "${bootargs}" "${console}"
+
+check_ipaddr=
+	if test -z "${ipaddr}" || test -z "${serverip}"; then
+		echo "ipaddr or serverip unset, falling back to DHCP...";
+		dhcp;
+	fi;
+
+rootfsmode=ro
--- a/include/env/tq/ubi.env
+++ b/include/env/tq/ubi.env
@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ * shared ubi environment for TQ boards
+ */
+
+addubi=
+	setenv bootargs "${bootargs}" rootfstype=ubifs ubi.mtd="${ubimtdname}"
+        root=ubi0:"${ubirootfsvol}" "${rootfsmode}" rootwait;
+
+load_spi=
+	if sf probe; then
+                if ubi part "${ubirootfspart}"; then
+			if ubifsmount ubi0:"${ubirootfsvol}"; then
+				ubifsload "${kernel_addr_r}" /boot/"${image}";
+				ubifsload "${fdt_addr_r}" /boot/"${fdtfile}";
+                                fdt address "${fdt_addr_r}";
+				fdt resize 0x100000;
+				for overlay in "${fdt_overlays}"; do
+					ubifsload "${fdtoverlay_addr_r}"
+					/boot/"${overlay}" &&
+					fdt apply "${fdtoverlay_addr_r}";
+				done;
+				ubifsumount;
+			fi;
+			ubi detach;
+		fi;
+	fi
+
+ubiargs=run addubi addtty
+
+ubiboot=
+	echo "Booting from UBI ...";
+	setenv bootargs;
+	run ubiargs;
+	if run load_spi; then
+		run boot_os;
+	else
+		echo "ERROR: loading kernel";
+	fi;
+
+ubimtdname=mtdname
+ubirootfspart=ubi
+ubirootfsvol=root