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arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma

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The u2phy1_host port is the part of the USB PHY1 (namely the
HOST1_DP/DM lanes) which routes directly to the USB2.0 HOST
controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG
controller (dwc3), which we do use.

The HOST1_DP/DM lanes aren't routed on RK3399 Puma so let's simply
disable the USB2.0 controllers and associated part in USB2.0 PHY.

No intended functional change.

[1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
    Chapter 2 USB2.0 PHY

Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-4-4a76a474a010@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 3373af1d76bacd054b37f3e10266dd335ce425f8 ]

(cherry picked from commit 97640da1f41d022484c1a4725bed943a5ae56073)
This commit is contained in:
Quentin Schulz 2025-07-30 13:10:21 +02:00 committed by Tom Rini
parent 6dd61725a2
commit d0681cf0c8
1 changed files with 0 additions and 12 deletions
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12
dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
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@ -579,10 +579,6 @@
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
status = "okay";
};
};
&usbdrd3_1 {
@ -616,11 +612,3 @@
vdd2-supply = <&vcc3v3_sys>;
};
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};